FT8010MPX [ONSEMI]
带有可配置延迟的重置计时器;
| 型号： | FT8010MPX |
| 厂家： | 
ONSEMI |
| 描述： | 带有可配置延迟的重置计时器 |
| 文件： | 总15页 (文件大小：860K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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2013年7月
FT8010
延迟时间可配置的复位定时器
特性
说明
. 长延迟可配置为7.5或11.25秒
FT8010是定时器，用于复位那些复位时间较长的移动设备
。长时延迟可避免因意外按键所引起的非预期复位。可以
通过硬接线DSR引脚选择两种延迟： 7.5 ±20%秒或
11.25±20%秒。
. 初级和次级输入重置引脚
. 推挽和开路漏极输出引脚
. 1.8 工作范围为V至5.0 V（TA=-40°C至+85°C）
. 1.7 工作范围为V至5.0 V（TA=-25°C至+85°C）
. 1.65 工作范围为V至5.0 V（TA=0°C至+85°C）
FT8010有两个输入，用于单按钮或双按钮复位功能。该器
件有两个输出： 0.5 mA驱动的推挽式输出和0.5 mA下拉
驱动的漏极开路输出。
FT8010不工作时消耗的ICC 电流最少，它可在1.65 V至
5.0 V宽电源电压范围内工作
. 提供10引脚UMLP (1.4 mm x 1.8 mm)封装和8引脚MLP
(2.0 mm x 2.0 mm)封装
订购信息
器件编号
工作温度范围
封装
包装方法
10引脚超薄MLP（1.4 x 1.8 x 0.55 mm封装，
0.40 mm间距）
每卷5000装卷
带和卷盘
FT8010UMX
-40C 至 +85C
8引脚MLP（2.0 x 2.0 x 0.8 mm封装，0.5 mm间
每卷3000装
FT8010MPX
-40C 至 +85C
距）
卷带和卷盘
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
框图
图1.框图
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
2
引脚布局
图2.MLP引脚配置(1)
（俯视图）
图3.UMLP引脚配置(2)
（俯视图）
注意：
1. DAP可以不接，或连接至地。
2. NC =不接线。
引脚说明
MLP引脚编号 UMLP引脚编号
名称
RST2
GND
说明
1
2
3
4
5
6
7
8
10
推挽式输出，有源高电平
接地
1
2
/SR1
/RST1
DSR
次级重置输入，有源低电平
漏极开路输出，低电平有效
3
5
延迟选择输入（必须直接连接至GND或VCC； 不使用上拉或下拉电阻）
6
TRIG
/SR0
VCC
测试引脚，在正常使用时连接至GND
7
8
初级重置输入，有源低电平
电源
4, 9,
NC
未连接
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
3
功能说明
FT8010复位定时器包含了一个内部振荡器和一个两级、21
位计数器，用于确定输出引脚转换的时间。借助DSR引脚
的硬连接逻辑电平，可以设置时间N。当DSR为低时，N 为
7.5 s±20%， 当DSR为高时，N 为11.25 s ±20%。
/RST1输出为一个开漏驱动器。当计数时间超过时间N后，
/RST1输出驱动为低。/RST2输出为一个推挽驱动器。当计
数时间超过时间N后，RST2输出驱动为高。
正常使用时，TRIG引脚应该连接到地（GND）或低电平。
TRIG引脚为测试模式引脚，用于扫描（SCAN）测试。
Table 1. FT8010 真值表
应用指南
DSR
0
复位定时器( +-20%)
7.50 s
重要声明： DSR引脚必须连接至VCC或GND，以提供高或低
电压电平。DSR引脚的电压电平决定可配置延迟的时间长
度。需要指出的是，在正常工作中，DSR引脚的电压电平
维持不变。DSR引脚必须在SR0或SR1按键变低之前直接连
接至VCC或GND。请勿在DSR引脚上使用上拉或下拉电阻。
1
11.25 s
输入引脚/SR0和/SR1用来驱动电压比较器，比较电压为输
入电压和由参考模块设置的电压。/SR0和/SR1的输入信号
同时为低时，振荡器启动。振荡器向数字芯片发送数字脉
冲，其中包括计数器。有两种计数情景，如下所述： 短
时持续和长时持续。对于短时持续情况，/RST1 和RST2引
脚不受影响。长时持续情况下，输出在时间N后更改状态
。/SR0或/SR1的输入信号为高时，输出返回至其原始状态
。
短时持续(tW < N)
在这种情况下，输入/SR0和/SR1在比时间N短的持续时间tW
均为低电平。当输入变为低电平时，内部定时器开始计数
。输入在时间N前变为高电平。定时器停止计数并复位，并
且输出无变化（参见图4）。
/SR0
L
/SR1 /RST1 /RST2
说明
L
H
H
L
L
当两个引脚均低时，定时器开始计数。当任意一个引脚变高时，定时器停止
计数。/SR0 和/SR1都需要变低时，才能激活（启动）定时器。
图4.短时持续波形
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
4
长时持续(tW > N)
在这种情况下，输入/SR0和/SR1在比时间N长的持续时
间tW均为低电平。当输入变为低电平时，内部定时器开
始计数。在时间N之后，各输出转换，定时器停止计数
。N秒后的某个时刻，该输入变高。当输入变为高电平
时，一段传播延迟后，定时器复位，各输出切换回各自
的原始状态（参见图5）。
/SR0
L
/SR1
L
/RST1
RST2
说明
当两个引脚均低时，定时器开始计数。时间N后，各输出转换。当任意
一个输入变高时，定时器复位，各输出转换回到原始状态。/SR0 和
/SR1都需要变低时，才能激活（启动）定时器。
图5.长时持续波形
注意：
3. 波形绘制没有按照比例(tpHL1, tpLH1 >> tpHL2, tpLH2)。
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
5
绝对最大额定值
应力超过绝对最大额定值，可能会损坏设备。在超出推荐的工作条件的情况下，该器件可能无法正常运行或操作，且不
建议让器件在这些条件下长期工作。此外，过度暴露在高于推荐的工作条件下，会影响器件的可靠性。绝对最大额定值
仅是额定应力值。
符号
VCC
参数
条件
最小值
-0.5
最大值 单位
电源电压
7
7
V
V
VIN
DC输入电压
/SR0, /SR1, TRIG, DSR
/RST1高电平或低电平
RST2高电平或低电平
/RST1, RST2, VCC=0
VIN < 0 V
-0.5
-0.5
7
VOUT
输出电压(4)
-0.5
Vcc+0.5
7
V
-0.5
IIK
IOK
直流输入二极管电流
-50
-50
+50
+50
100
+150
+150
+260
5
mA
mA
VOUT < 0 V
DC输出二极管电流
VOUT > VCC
IOH/IOL DC输出源/灌电流
-50
-65
mA
mA
C
C
C
mW
ICC
TSTG
TJ
每个电源引脚的DC VCC或接地电流
存储温度范围
偏压下结温
TL
结点焊接温度，焊接10秒
功耗
PD
人体模式，JESD22-A114
4
ESD
静电放电能力
kV
充电器件模式，JESD22-C101
2
注意：
4. 必须注意IO绝对最大额定值。
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
6
推荐工作条件
推荐的操作条件表定义了器件的真实工作条件。指定推荐的工作条件，以确保设备的最佳性能达到数据表中的规格。飞兆半导
体建议不要超过推荐工作条件，也不能按照绝对最大额定值进行设计。
符号
参数
条件
-40C°至+85C°
最小值
1.8
最大值
5.0
单位
-25C°至+85C°
1.7
5.0
VCC
电源电压
V
0C°至+85C°
1.65
5
5.00
tRFC
ms
V
VCC=0 V断电后，上升至0.5 V
断电后，VCC 恢复时间
VIN
输入电压
/SR0, /SR1
0
5
0
0
0
5
VCC
/RST1高电平或低电平
VOUT
输出电压
RST2高电平或低电平
V
5
/RST1、RST2、VCC=0 V
RST2, 1.8 V ≤ VCC ≤ 3.0 V
RST2, 3.0 V ≤ VCC ≤ 5.0 V
-0.1
-0.5
IOH
DC输出源电流
mA
/RST1, RST2, VCC=1.8 V to
5.0 V
IOL
TA
+0.5
DC输出灌电流
空气流通时的工作温度
-40
+85
245
200
C
MLP-8
JA
°C/W
热阻
UMLP-10
注意：
5. 所有未用的输入端必须保持为VCC 或GND。
直流电气特性
除非另行说明，以下性能特性需满足条件：TA=-40至80C且VCC=1.8 - 5.0V或 TA=-25至85C且VCC=1.7 – 5 V或 TA=0至85C且
VCC=1.65 – 5 V。
符号
参数
条件
最小值
1.2
最大值
单位
/SR0, /SR1
DSR
VIH
输入高电平
输入低电平
V
0.65 x VCC
/SR0, /SR1
DSR
0.32
VIL
V
V
0.25 x VCC
RST2, IOH=-100 µA
0.8 x VCC
0.8 x VCC
VOH
高电平输出电压
RST2、IOH=-500 µA
VCC=3.0至5.0 V
RST2, IOL=500 µA
/RST1, IOL=500 µA
0 V VIN 5.0 V
0.3
0.3
VOL
IIN
低电平输出电压
输入漏电流
V
1.0
µA
静态电源电流
/SR0 or /SR1=VCC
/SR0=/SR1=0 V
20
（定时器关闭）
ICC
µA
动态电源电流
（定时器运行）
100
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
7
交流电气特性
除非另行说明，以下性能特性需满足条件：TA=-40至80C且VCC=1.8 - 5.0 V或 TA=-25至85C且VCC=1.7 – 5 V或 TA=0至
85C且VCC=1.65 – 5 V。
符号
参数
工作条件
最小值
典型值
最大值
单位
定时器延迟，/SRn至/RST1， CL=5 pF，RL=5 k
(DSR=0) 参见图6
6.0
7.5
9.0
s
tPHL1
定时器延迟，/SRn至/RST1， CL=5 pF，RL=5 k
9.00
11.25
220
13.50
310
s
ns
s
(DSR=1)
参见图6
传播延迟，/SRn至/RST1，
（DSR=0或1）
CL=5 pF，RL=5 k
参见图6
tPLH2
tPLH1
tPHL2
定时器延迟，/SRn至/RST2， CL=5 pF，RL=10 k
(DSR=0) 参见图7
6.0
7.5
9.0
定时器延迟，/SRn至/RST2， CL=5 pF，RL=10 k
9.00
11.25
210
13.50
300
s
(DSR=1)
参见图7
传播延迟，/SRn至/RST2，
（DSR=0或1）
CL=5 pF，RL=10 k
参见图7
ns
电容规格
TA=+25C.
符号
CIN
参数
工作条件
典型值
单位
输入电容
VCC=GND
4.0
5.0
pF
pF
COUT
输出电容
VCC=5.0 V
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
8
交流测试电路与波形
图6./RST1 输出
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
9
交流测试电路和波形（续）
图7.RST2 输出
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
10
物理尺寸测试
0.10 C
2X
1.40
A
B
(9X)
0.563
1.70
0.663
1.80
1
PIN#1 IDENT
2.10
0.10 C
0.40
TOP VIEW
2X
0.225
(10X)
RECOMMENDED
LAND PATTERN
0.55 MAX.
(0.15)
0.10 C
0.08 C
9X
0.45
1.45
SEATING
PLANE
0.55
0.40
C
0.05
0.00
SIDE VIEW
1.85
0.35
(9X)
0.45
0.225
(10X)
3
OPTIONAL MINIMIAL
TOE LAND PATTERN
0.40
6
DETAIL A
1
NOTES:
PIN#1 IDENT
A. PACKAGE DOES NOT CONFORM TO
ANY JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
0.15
0.25
10
(10X)
0.10 C A B
0.05 C
BOTTOM VIEW
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
0.55
0.45
E. DRAWING FILENAME: MKT-UMLP10Arev5.
F. FAIRCHILD SEMICONDUCTOR.
PACKAGE
EDGE
45°
LEAD
OPTION 2
LEAD
OPTION 1
0.25
0.15
DETAIL A
SCALE : 2X
SCALE : 2X
SCALE : 2X
图8.10引脚超薄MLP，1.4 x 1.8 x 0.55 mm封装
封装图纸是作为一项服务而提供给考虑选用飞兆半导体产品的客户。具体参数可进行改动，且无需做出相应通知。请注意图纸上的版
本和/或日期，并联系飞兆半导体代表核实或获得最新版本。封装规格并不超出飞兆公司全球范围内的条款与条件，尤其指保修，保修涉
及飞兆半导体的全部产品。
随时访问飞兆半导体在线封装网页，可以获得最新的封装图:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
11
物理尺寸 (续)
TOP LAYER
CU KEEP
OUT AREA
0.10 C
2.00
A
0.90
0.50
2X
1.80
B
E
(0.90)
8X
PIN1
IDENT
(0.25)
8X
2.00
OPTION #1: NO CENTER PAD
0.10 C
2X
(1.35)
TOP VIEW
(0.35)
0.90
0.50
0.80 MAX
0.10 C
1.80
(0.20)
C
(0.90)
8X
0.05
0.00
0.08 C
(0.25)
8X
SEATING
PLANE
SIDE VIEW
OPTION #2: WITH CENTER PAD
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
A
0.25
0.15
8X
0.65
0.45
1
4
8X
NOTES:
A. PACKAGE CONFORMS TO JEDEC MO-229,
VARIATION W2020D EXCEPT WHERE NOTED.
0.40 MAX
PIN 1
IDENT
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
0.10
0.05
C
C
A B
8
5
0.50
D. LAND PATTERN RECOMMENDATION BASED
ON PCB MATRIX CALCULATOR V2009.
1.35 MAX
E. IF CENTER PAD IS NOT SOLDERED TO, NO
EXPOSED METAL IS ALLOWED IN THE TOP
LAYER OF THE BOARD IN THE AREA SHOWN.
BOTTOM VIEW
F. DRAWING FILENAME: MKT-MLP08Rrev2.
图9.8引脚模塑无铅封装(MLP)，2.0 x 2.0 x 0.8 mm
封装图纸是作为一项服务而提供给考虑选用飞兆半导体产品的客户。具体参数可进行改动，且无需做出相应通知。请注意图纸上的版
本和/或日期，并联系飞兆半导体代表核实或获得最新版本。封装规格并不超出飞兆公司全球范围内的条款与条件，尤其指保修，保修涉
及飞兆半导体的全部产品。
随时访问飞兆半导体在线封装网页，可以获得最新的封装图:
http://www.fairchildsemi.com/packaging/。
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
12
© 2009 Fairchild Semiconductor Corporation
FT8010 • Rev. 1.0.8
www.fairchildsemi.com
13
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
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