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March 2012

FSSD06 — SD/SDIO and MMC Two-Port Multiplexer

Features

Description

The FSSD06 is a two-port multiplexer that allows Secure

Digital (SD), Secure Digital I/O (SDIO), and Multimedia

Card (MMC) host controllers to be expanded out to

multiple cards or peripherals. This configuration enables

the CMD, CLK, and D[3:0] signals to be multiplexed to

dual-card peripherals. It is optimized for 1-bit / 4-bit SD /

MMC applications.

. On Resistance Typically 4Ω, V_DDH=2.7V

. f_toggle: > 120MHz

. Low On Capacitance: 9pF Typical

. Low Power Consumption: 1µA Maximum

. Conforms to Secure Digital (SD), Secure Digital I/O

(SDIO), and Multimedia Card (MMC) Specifications

The architecture includes the necessary bi-directional

data and command transfer capability for single high-

voltage cards or dual-voltage supply cards. The clock

path for the FSSD06 is a uni-directional buffer with an

integrated pull-up for high-impedance mode.

. Supports 1-Bit / 4-Bit Host Controllers (V_DDH=1.65V to

3.6V) Communicating with High-Voltage (2.7-3.6V)

and Dual-Voltage Cards (1.65-1.95V, 2.7-3.6V)

-

V_DDH=1.65 to 3.6V, V_DDC1/C2=V_DDHto 3.6V

Typical applications involve switching in portables and

consumer applications: cell phones, digital cameras,

home theater monitors, portable GPS units, and printers.

. 24-Lead MLP (3.5 x 4.5mm) and UMLP Packages

Applications

. Cell Phone, PDA, Digital Camera, Portable GPS

. LCD Monitor, Home Theater PC/TV, All-in-One Printer

Analog Symbol Diagram

VDDC1

VDDC2

VDDH

/OE

S

Control

5

1DAT[0:3], 1CMD

5

DAT[0:3], CMD

2DAT[0:3], 2CMD

V_DDC1

V_DDC2

R_PU

1CLK

2CLK

CLK

GND

Figure 1.

Analog Symbol Diagram

Ordering Information

Operating

Temperature Range

Packing

Method

Part Number

Package Description

24-Lead Molded Leadless Package (MLP), JEDEC MO-

220, 3.5 x 4.5mm

FSSD06BQX

FSSD06UMX

-40°C to +85°C

Tape & Reel

-40°C to +85°C

24-Lead Ultrathin Molded Leadless Package (UMLP)

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

Pin Configuration

2

1

24 23

24

23

22

21

20

19

DAT[2]

DAT[3]

22

21

20

19

18

17

3

4

5

6

7

8

9

VDDC1

1CLK

DAT[3]

CMD

18

1CLK

1

2

17

16

15

14

13

1DAT[0]

1DAT[1]

1DAT[0]

1DAT[1]

2DAT[2]

2DAT[3]

2CMD

CMD

VDDH

GND

VDDH

GND

CLK

3

4

2DAT[2]

CLK

5

6

2DAT[3]

2CMD

DAT[0]

16

15

DAT[0]

DAT[1] 10

VDDC2

11

7

9

12

10

8

11 12 13 14

Figure 2.

MLP Pin Assignments

Figure 3.

UMLP Pin Assignments

Pin Definitions

Name

Description

VDDH

Power Supply (Host ASIC)

VDDC1, VDDC2

Power Supply (SDIO Peripheral Card Ports)

Output Enable (Active Low)

Select Pin

/OE

S

1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD

DAT[3:0], CMD

SDIO Card Ports

SDIO Common Ports

Clock Path Ports

CLK, 1CLK, 2CLK

Truth Table

/OE

S

Function

LOW

HIGH

LOW

HIGH

X

CMD, CLK, DAT[3:0] connected to 1CMD, 1CLK, 1DAT[3:0]; 2CLK pulled HIGH via R_PU

CMD, CLK, DAT[3:0] connected to 2CMD, 2CLK, 2DAT[3:0]; 1CLK pulled HIGH via R_PU

All Ports High Impedance; 1CLK, 2CLK pulled HIGH via R_PU

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

2

Typical Application Diagram

VDDH

VDDC1

1.65 – 3.60V

FSSD06

V_{DD H}to 3.6V

R_T

GND

1CMD, 1DAT[3:0]

WiFi,

CMD, DAT[3:0]

Bluetooth,

MMC or SD

Module

5

Processor

1CLK

Secure Data /

Multimedia Card

2:1 Peripheral

Expander

VDDC2

CLK

V_{DD H}to 3.6V

R_T

Note: External resistors (R _T) are

recommended if card supplies are

allowed to float in the application.

The resistors should be >500K to

minimize power consumption.

GND

2CMD, 2DAT[3:0]

WiFi,

5

Bluetooth,

MMC or SD

Module

2CLK

/OE

S

GND

Figure 4.

Typical Application Diagram

Functional Description

The FSSD06 enables sharing the ASIC/baseband

processor SDIO port(s) to two peripheral cards,

providing bi-directional support for dual-voltage

SD/SDIO or MMC cards available in the marketplace.

Each SDIO port of the FSSD06 has its own supply rail,

allowing peripheral cards with different supplies to be

interfaced to the host. The peripheral card supplies must

be equal or greater than the host to minimize power

consumption. The independent V_DDH, V_DDC1, and V_DDC2

are defined by the supplies connected from the

application Power Management ICs (PMICs) to the

FSSD06. The clock path is a uni-directional buffered

path rather than a bi-directional switch port.

CLK Bus

The 1CLK and 2CLK outputs are bi-state buffer

architectures, rather than a switch I/O, to ensure 52MHz

incident wave switching. When there is no

communication on the bus (IDLE), the FSSD06 can be

disabled with the /OE pin. When this pin is pulled HIGH,

the nCLK outputs are also pulled HIGH. Along with

nCMD, nDAT[3:0] goes high-impedance to ensure that

the CLK path between the FSSD06 and the peripheral

does not float.

IDLE State CMD/DAT Bus “Parking”

The SD and MMC card specifications were written for a

direct point-to-point communication between host

controller and card. The introduction of the FSSD06 in

that path, as an expander, requires that the functional

operation and system latency not be impacted by the

FSSD06 switch characteristics. Since there are various

card formats, protocols, and configurable controllers, a

/OE pin is available to facilitate a fast IDLE transition for

the nCMD/nDAT[3:0] outputs. Some controllers, rather

than simply placing CMD/DAT into high-impedance

mode, may pull their outputs HIGH for a clock cycle prior

to going into high-impedance mode (referred to as

“parking” the output). Some legacy controllers pull their

outputs HIGH versus high impedance.

CMD, DAT Bus Pull-ups

The 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0] ports do

not have, internally, the system pull-up resistors as

defined in the MMC or SD card system bus

specifications. The system bus pull-up must be added

external to the FSSD06. The value, within the specific

specification limits, is a function of the individual

application and type of card or peripheral connected. For

SD card applications, the R_CMDand R_DATpull-ups should

be between 10kΩ and 100kΩ. For MMC applications,

the R_CMDpull-ups should be between 4.7kΩ and 100kΩ

and the R_DATpull-ups between 50kΩ and 100kΩ. The

card-side 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0]

outputs have a circuit that facilitates incident wave

switching, so the external pull-up resistors ensure

retention of the output high level.

If the /OE pin is left LOW and the controller places the

CMD/DAT[3:0] outputs into high impedance, the

nCMD/nDAT[3:0] output rise time is a function of the RC

time constant through the switch path. It is

recommended that the host controller pull CMD and

DAT[3:0] HIGH for one cycle before pulling /OE HIGH.

This facilitates parking all nCMD/nDAT[3:0] outputs

HIGH before putting the switch I/Os in high impedance.

The /OE pin can be used to place the 1CMD, 2CMD,

1DAT[3:0] and 2DAT[3:0] into high-impedance mode

when the system enters IDLE state (see IDLE State

CMD/DAT Bus “Parking”).

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Conditions

Min.

-0.5

Max.

4.6

Unit

V

V_DDH

Supply Voltage

V_DDC1,V_DDC2Supply Voltage

-0.5

4.6

V

1DAT[3:0], 2DAT[3:0], 1CMD,

2CMD Pins

V_DDx⁽²⁾+ 0.3V

(4.6V maximum)

V_DDx⁽²⁾+ 0.3V

(4.6V maximum)

-0.5

V

(1)

V_SW

Switch I/O Voltage

DAT[3:0], CMD Pins

(1)

V_CNTRL

Control Input Voltage

CLK Input Voltage

S, /OE

CLK

-0.5

4.6

V

(1)

V_CLKI

V_DDx⁽²⁾+ 0.3V

(4.6V maximum)

(1)

V_CLKO

CLK Output Voltage

1CLK, 2CLK

-0.5

V

I_INDC

I_SW

Input Clamp Diode Current

Switch I/O Current

-50

50

mA

SDIO Continuous

SDIO Pulsed at 1ms Duration,

<10% Duty Cycle

I_SWPEAK

Peak Switch Current

100

mA

T_STG

T_J

Storage Temperature Range

Max Junction Temperature

Lead Temperature

-65

+150

C

+150

T_L

Soldering, 10 Seconds

I/O to GND

+260C

8

9

5

Human Body Model

(JEDEC: JESD22-A114)

Supply to GND

All Other Pins

kV

ESD

Charged Device Model (JEDEC: JESD22-C101)

2

kV

Notes:

1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed.

2. _DDxreferences the specific SDIO port V_DDrail (i.e. V_DDC1, V_DDC2, V_DDH).

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DDH

Parameter

Supply Voltage - Host Side

Minimum

Maximum

3.6V

Unit

V

1.65

V_DDH

0

V_DDC1,V_DDC2

V_CNTRL

Supply Voltage - SDIO Cards

Control Input Voltage - V_S,V_/OE

Clock Input Voltage - V_CLKI

3.6V

V

V_DDH

V

V_CLKI

0

V_DDH

V

Switch I/O Voltage - CMD, DAT[3:0]

Switch I/O Voltage - 1CMD, 1DAT[3:0]

Switch I/O Voltage - 2CMD, 2DAT[3:0]

Operating Temperature

0

V_DDH

V

V_SW

0

V_DDC1

V_DDC2

+85

V

0

V

°C

-40

°C

°C/W

Thermal Resistance (free air), MLP24

50

_JA

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

4

DC Electrical Characteristics at 1.8V V_DDH

All typical values are for V_DDH=1.8V at 25°C unless otherwise specified.

T_A=- 40°C to +85°C

Min. Typ. Max.

V_DDC1

V_DDC2(V)

/

Symbol

Parameter

Conditions

Unit

Common Pins

V_IK

V_IH

V_IL

I_IN

Clamp Diode Voltage

2.7

3.6

I_IK=-18mA

-1.2

Control Input Voltage

High

1.3

V

V_DDH=1.65V

Control Input Voltage Low

0.5

V_DDH=1.95V, V_CNTRL=0V to

V_DDH

S, /OE Input High Current

-1

1

µA

Off Leakage, Current of

all ports

I_OZ

I_PU

3.6

V_DDH=1.95V, V_SW=0V to V_DDX-1.0

0.5

1.0

35

V_CLKI=V_DDHV_CLKO=0V,

/OE=V_DDH

CLK Pull-up Current

2.4

50

V_OHC

V_OLC

R_PU

CLK Output Voltage High

CLK Output Voltage Low

CLK Pull-up Resistance⁽³⁾

2.7

3.6

I_OH=-2mA

I_OL=-2mA

V

90

6

mV

kꢀ

100

4

V_{CMD, DAT[3:0]=}0V, I_ON=-2mA,

See Figure 5

R_ON

Switch On Resistance⁽⁴⁾

Delta On Resistance^{(4, 5)}

2.7

ꢀ

∆R_ON

V_{CMD, DAT[3:0]=}0V, I_ON=- 2mA

0.8

Power Supply

Quiescent Supply Current

V_DDH=1.95V, V_SW=0 or V_DDH

,

I_CC(VDDH)

0

1

µA

(Host)

I

_OUT=0

V_SW=0 or V_DDx,I_OUT=0,

_CLKI=V_DDH, V_CLKO=Open,

/OE=0V

I_CC(VDDC1,Quiescent Supply Current

3.6

V

(SDIO Cards)

VDDC2)

V

_SW=0 or V_DDx,I_OUT=0,

Delta I_{CC(VDDC1, VDDC2)}for

One Card Powered Off

3.6V

/ 0V

∆I_CARD

V_CLKI=V_DDH, V_CLKO=Open,

1

µA

/OE=0V

Notes:

3. Guaranteed by characterization, not production tested.

4. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch.

5. ∆ R_ON=R_{ON max}– R_{ON min}measured at identical V_CC, temperature, and voltage.

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

5

DC Electrical Characteristics at 2.7V V_DDH

All typical values are for V_DDH=2.7V at 25°C unless otherwise specified.

T_A=- 40°C to +85°C

Min. Typ. Max.

V_DDC1

V_DDC2(V)

/

Symbol

Parameter

Conditions

Unit

Common Pins

V_IK

V_IH

V_IL

I_IN

Clamp Diode Voltage

2.7

3.6

I_IK=-18mA

-1.2

Control Input Voltage

High

1.8

V

V_DDH=2.7V

Control Input Voltage Low

0.8

V_DDH=3.6V, V_CNTRL=0V to

V_DDH

S, /OE Input High Current

-1

1

µA

I_OZ

Off Leakage Current of all

ports

V_DDH=3.6V, V_SW=0V to V_DDX

3.6

-1.0

0.5

1.0

50

I_PU

CLK Pull-up Current

V_CLKI=V_DDH,V_CLKO=0V,

/OE=V_DDH

2.4

50

V_OHC

V_OLC

R_PU

CLK Output Voltage High

CLK Output Voltage Low

CLK Pull-up Resistance⁽⁶⁾

2.7

3.6

I_OH=-2mA

I_OL=-2mA

V

90

mV

kꢀ

100

2.5

0.8

V_{CMD, DAT[3:0]=}0V, I_ON=-2mA

See Figure 5

R_ON

Switch On Resistance⁽⁷⁾

Delta On Resistance^(7,8)

2.7

6.0

ꢀ

∆R_ON

V_{CMD, DAT[3:0]=}0V, I_ON=- 2mA

Power Supply

Quiescent Supply Current

V_DDH=3.6V, V_SW=0 or V_DDH

I_OUT=0

,

I_CC(VDDH)

0

1

µA

(Host)

V_SW=0 or V_DDx,I_OUT=0,

_CLKI=V_DDH, V_CLKO=Open,

/OE=0V

I_CC(VDDC1,Quiescent Supply Current

3.6

V

(SDIO Cards)

VDDC2)

V

_SW=0 or V_DDx,I_OUT=0,

Delta I_{CC(VDDC1, VDDC2)}for

∆I_CARD

3.6V/0V

0V/3.6V

V_CLKI=V_DDH, V_CLKO=Open,

1

µA

One Card Powered Off

/OE=0V

Notes:

6. Guaranteed by characterization, not production tested.

7. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the switch.

8. ∆R_ON=R_{ON max}– R_{ON min}measured at identical V_CC, temperature, and voltage.

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

6

AC Electrical Characteristics at 1.8V V_DDH

All typical values are for V_DDH=1.8V at 25°C unless otherwise specified.

T_A=- 40°C to +85°C

Min. Typ. Max.

V_DDC1

/

Symbol

Parameter

Conditions

Unit

V_DDC2(V)

2.7 to 3.6

Turn-On Time,

S, /OE to CMD, DAT[3:0]

V_SW=0V, R_L=1kꢀ, C_L=30pF

See Figure 7, Figure 8

t_ON1

t_OFF1

t_PD

10

7

24

22

ns

dB

Turn-Off Time,

S, /OE to CMD, DAT[3:0]

V_SW=0V, R_L=1kꢀ, C_L=30pF

See Figure 7, Figure 8

Switch Propagation

Delay⁽⁹⁾

Switch Skew^{(9, 10)}

CMD, DAT[3:0]

See Figure 9

1

t_SKEW

t_ON2

R_L=1kꢀ, C_L=30pF

2

Turn-On Time,

S, /OE to 1CLK, 2CLK

V_SW=0V, R_L=1kꢀ, C_L=30pF

See Figure 7, Figure 8

17

10

3.0

-60

35

28

Turn-Off Time

S, /OE to 1CLK, 2CLK

V_SW=0V, R_L=1kꢀ, C_L=30pF

See Figure 7, Figure 8

t_OFF2

t_PDCLK

O_IRR

Xtalk

R_L=1kꢀ, C_L=30pF

See Figure 11

Clock Propagation Delay

Off Isolation⁽⁹⁾

5.5

f=10MHz, R_T=50ꢀ, C_L=30pF,

See Figure 12

Non-Adjacent Channel

Crosstalk⁽⁹⁾

Clock Frequency⁽⁹⁾

f=10MHz, R_T=50ꢀ, C_L=30pF,

See Figure 13

2.7 to 3.6

-60

dB

f_toggle

C_L=30pF

120

MHz

Notes:

9. Guaranteed by characterization, not production tested.

10. Skew is determined by |T_PLH- T_PHL| for worst-case temperature and V_DDX

.

www.fairchildsemi.com

FSSD06 • Rev. 1.0.5

7

AC Electrical Characteristics at 2.7V V_DDH

All typical values are for V_DDH=2.7V at 25°C unless otherwise specified.

T_A=- 40°C to +85°C

Min. Typ. Max.

V_DDC1

/

Symbol

Parameter

Conditions

Unit

V_DDC2(V)

2.7 to 3.6

Turn-On Time

S, /OE to CMD, DAT[3:0]

V_SW=0V, R_L=1kꢀ, C_L=30pF

See Figure 7, Figure 8

t_ON1

t_OFF1

t_PD

8

6

17

13

ns

dB

Turn-Off Time

S, /OE to CMD, DAT[3:0]

V_SW=0V, R_L=1kꢀ, C_L=30pF

See Figure 7, Figure 8

Switch Propagation

Delay⁽¹¹⁾

Switch Skew⁽¹²⁾

CMD, DAT[3:0]

2.7 to 3.6 See Figure 9

1

t_SKEW

t_ON2

2.7 to 3.6 R_L=1kꢀ, C_L=30pF

1.5

15

10

1.5

-60

Turn-On Time

S, /OE to 1CLK, 2CLK

V_SW=0V, R_L=1kꢀ, C_L=30pF

See Figure 7, Figure 8

2.7 to 3.6

25

Turn-Off Time

S, /OE to 1CLK, 2CLK

V_SW=0V, R_L=1kꢀ, C_L=30pF

See Figure 7, Figure 8

t_OFF2

t_PDCLK

O_IRR

Xtalk

R_L=1kꢀ, C_L=30pF

See Figure 11

Clock Propagation Delay

Off Isolation⁽¹¹⁾

3.0

f=10MHz, R_T=50ꢀ, C_L=30pF

See Figure 12

Non-Adjacent Channel

Crosstalk⁽¹¹⁾

f=10MHz, R_T=50ꢀ, C_L=30pF

See Figure 13

-60

dB

f_toggle

Clock Frequency⁽¹¹⁾

2.7 to 3.6 C_L=30pF

120

MHz

Notes:

11. Guaranteed by characterization, not production tested.

12. Skew is determined by |T_PLH- T_PHL| for worst-case temperature and V_DDX

.

Capacitance

T_A=- 40°C to +85°C

Min. Typ. Max.

Symbol

C_{IN (S, /OE, CLK)}

C_ON

Parameter

Conditions

Unit

Control and CLK Pin Input

Capacitance

V

_DDH=0V

2.5

V

_DDH=1.8V,V_DDC1=V_DDC2=2.7V,

_/OE=0V, V_bias=0V, f=1MHz

See Figure 15

Common Port On Capacitance

9.0

(C_{DAT[3:0], CMD}

)

pF

V_DDH=1.8V,V_DDC1=V_DDLH2=2.7V,

C_OFF

Input Source Off Capacitance

V_/OE=3.3V, V_bias=0V, f=1MHz

4.0

See Figure 14

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

8

Test Diagrams

V_ON

I_OZ

NC

nDAT[3:0],nCMD

DAT[3:0],CMD

A

V

IN

I_ON

Select

GND

Select

GND

ddl

V_S= 0 orVddl

V

_S= 0 or

R

_ON= V_ON/ I_ON

Figure 5.

On Resistance

Figure 6.

Off Leakage (Each Switch Port is

Tested Separately)

V

DDx

t_RISE= 2.5ns

t_FALL= 2.5ns

DAT[3:0],

CMD

nDAT[3:0],nCMD

R

L

V_ddx

V

90%

V_ddx/2

90%

SW

V_OUT

Input- V

CNTRL

V_ddx/2

C

R

GND

L

S

10%

50%

GND

V_OH

V

S

Output-V_OUT

V_OL

GND

Vol + 0.15V

t_ON

t_OFF

R_L, R_S, and C_Lare function of application

environment (see AC Tables for specific values)

C_Lincludes test fixture and stray capacitance

Figure 7.

AC Test Circuit Load

Figure 8.

Turn On/Off Time Waveforms

V

DDx

t_RISE= 2.5ns

t_FALL= 2.5ns

CLK

1CLK,

V

R

2CLK

ddx

L

90%

V_ddx/2

90%

V

CLKI

Input- V_SW

10%

V_OUT

V_ddx/2

C

L

R

GND

10%

S

GND

V_OH

V

Output- V_OUT

V_OL

S

50%

t_pLH

GND

t_pHL

R_L, R_S, and C_Lare function of application

environment (see AC Tables for specific values)

C_Lincludes test fixture and stray capacitance

Figure 9.

Switch Propagation Delay Waveform

Figure 10. AC Test Circuit Load (CLK)

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

9

Test Diagrams (Continued)

t

_FALL= 2.5ns

_RISE= 2.5ns

Network Analyzer

R

S

V

ddx

V

90%

V_ddx/2

90%

IN

V

S

GND

R

Input- V

T

CLKI

V_ddx/2

GND

10%

50%

V

GND

S

GND

V

OUT

V_OHC

GND

R

T

Output -V

R_Sand R_Tare function of application

environment (see AC Tables for specific values)

CLKO

50%

t_pLH

GND

V_OLC

t_pHL

Off-Isolation = 20 Log (V_OUT/ V_IN

)

Figure 11. CLK Propagation Delay Waveforms

Figure 12. Channel Off Isolation

Network Analyzer

NC

R

S

V

IN

V

S

GND

V

S

GND

R

T

GND

V

OUT

GND

R

T

R_Sand R_Tare function of application environment

(see AC Tables for specific values)

GND

CROSSTALK = 20 Log (V_OUT/ V_IN

)

Figure 13. Channel-to-Channel Crosstalk

nDAT[3:0], nCMD, nCLK

Capacitance

Meter

S

Capacitance

Meter

V

= 0 orV

ddh

S

V

_S= 0 orV_ddh

f = 1MHz, V_bias= 0V

f = 1MHz,V_bias= 0V

nDAT[3:0], nCMD, nCLK

Figure 14. Channel Off Capacitance

Figure 15. Channel On Capacitance

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

10

Tape and Reel Specifications

Package

Cover Tape

Status

Tape Selection

Designator

Number Cavities

Cavity Status

Leader (Start End)

125 (Typical)

3000

Empty

Filled

Sealed

MPX

Carrier

Trailer (Hub End)

75 (Typical)

Empty

Tape Dimensions

Dimensions are in millimeters unless otherwise noted.

Reel Dimensions

Dimensions are in inches (millimeters) unless otherwise noted.

Tape Size

A

B

C

D

N

W1

W2

13.000

(330.00)

0.059

(1.50)

0.512

(13.00)

0.795

(20.00)

2.165

(55.00)

0.488

(12.40)

0.724

(18.40)

(12.00mm)

FSSD06 • Rev. 1.0.5

www.fairchildsemi.com

11

2.50±0.10

A

B

0.663

0.400

19

24

PIN#1

IDENT

0.563

1

18

2.225 3.700

13

3.40±0.10

6

0.225

7

12

TOP VIEW

2.225

2.800

0.025±0.025

0.50±0.05

LAND PATTERN RECOMMENDATION

0.50±0.05

SEATING PLANE

C

SIDE VIEW - OPTION A

0.10±0.05

0.50±0.05

SEATING PLANE

45°

0.20±0.05

C

0.025±0.025

SIDE VIEW - OPTION B

DETAIL A

0.05

SCALE 2:1

(0.15) 4X

POTENTIAL

PULL BACK

NOTES:

7

12

A. PACKAGE DOES NOT FULLY CONFORM

TO JEDEC STANDARD

B. ALL DIMENSIONS ARE IN MILLIMETERS

C. LAND PATTERN RECOMMENDATION IS

EXISTING INDUSTRY LAND PATTERN

D. DRAWING FILENAME: MKT-UMLP24ArevE

6

13

18

0.40

DETAIL A

1

PIN#1

IDENT

0.40±0.05 (23X)

24

19

0.20±0.05 (24X)

0.10 C A B

0.05 C

0.85

BOTTOM VIEW

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1


型号：	FSSD06UMX
厂家：	ONSEMI
描述：	SD/SDIO 和 MMC 2 端口多路复用器复用器
文件：	总15页 (文件大小：582K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FSSD06UMX [ONSEMI]

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