FSL136MR [ONSEMI]
650V 集成电源开关，带 67kHz 频率和可调电流限值，用于 20W 离线反激转换器;
| 型号： | FSL136MR |
| 厂家： | 
ONSEMI |
| 描述： | 650V 集成电源开关，带 67kHz 频率和可调电流限值，用于 20W 离线反激转换器 开关 PC 电源开关 光电二极管 转换器 |
| 文件： | 总13页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FSL136MR
Green Mode Power Switch
Description
The FSL136MR integrated Pulse Width Modulator (PWM) and
®
SENSEFET is specifically designed for high−performance offline
Switch−Mode Power Supplies (SMPS) with minimal external
components. FSL136MR includes integrated high−voltage power
switching regulators that combine an avalanche−rugged SENSEFET
with a current−mode PWM control block.
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The integrated PWM controller includes: Under−Voltage Lockout
(UVLO) protection, Leading−Edge Blanking (LEB), a frequency
generator for EMI attenuation, an optimized gate turn−on/turn−off
driver, Thermal Shutdown (TSD) protection, and
temperature−compensated precision current sources for loop
compensation and fault protection circuitry. The FSL136MR offers
good soft−start performance. When compared to a discrete MOSFET
and controller or RCC switching converter solution, the FSL136MR
reduces total component count, design size, and weight; while
increasing efficiency, productivity, and system reliability. This device
provides a basic platform that is well suited for the design of
cost−effective flyback converters.
PDIP8 9.42x6.38, 2.54P
CASE 646CM
MARKING DIAGRAM
$Y&E&Z&2&K
FSL136MR
Features
• Internal Avalanche−Rugged SENSEFET (650 V)
• Under 50 mW Standby Power Consumption at 265 Vac, No−load
Condition with Burst Mode
• Precision Fixed Operating Frequency with Frequency Modulation
for Attenuating EMI
$Y
&E
&Z
&2
&K
= ON Semiconductor Logo
= Designated Space
= Assembly Plant Code
= 2−Digit Date code format
= 2−Digits Lot Run Traceability Code
FSL136MR = Specific Device Code Data
• Internal Startup Circuit
• Built−in Soft−Start: 15 ms
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
• Pulse−by−Pulse Current Limit
• Various Protection: Over Voltage Protection (OVP), Overload
Protection (OLP), Output−Short Protection (OSP), Abnormal
Over−Current Protection (AOCP), Internal Thermal Shutdown
Function with Hysteresis (TSD)
Applications
• Auto−Restart Mode
• SMPS for VCR, STB, DVD & DVCD
Players
• SMPS for Home Appliance
• Adapter
• Under−Voltage Lockout (UVLO)
• Low Operating Current: 1.8 mA
• Adjustable Peak Current Limit
Table 1. MAXIMUM OUTPUT POWER (Note 1)
Related Resources
230 Vac + 15% (Note 2)
Adapter (Note 3) Open Frame
19 W 26 W
85−265 Vac
• https://www.onsemi.com/pub/Collateral/
AN−4137.pdf.pdf
• https://www.onsemi.com/pub/Collateral/
AN−4141.pdf.pdf
• https://www.onsemi.com/PowerSolutions/
home.do
Adapter (Note 3)
14 W
Open Frame
20 W
1. The junction temperature can limit the maximum output power.
2. 230 Vac or 100/115 Vac with doubler.
3. Typical continuous power in a non−ventilated enclosed adapter
measured at 50°C ambient.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
July, 2019 − Rev. 2
FSL136MR/D
FSL136MR
Table 2. ORDERING INFORMATION
Part Number
Operating Temperature Range
Top Mark
Package
8−Lead, Dual Inline Package (DIP)
Packing Method
FSL136MR
−40 to 105 °C
FSL136MR
Rail
TYPICAL APPLICATION DIAGRAM
Figure 1. Typical Application
INTERNAL BLOCK DIAGRAM
VSTR
5
Drai n
6,7,8
VCC
2
ICH
VBURL /VBURH
8V/12V
V
Good
Internal
Bias
CC
VREF
V
V
CC
CC
Random
Frequency
Generator
OSC
PWM
IFB
IDELAY
S
R
Q
Q
Gate
Driver
VFB 3
2.5R
R
IPK
4
LEB
On-Time
Detector
Soft
Start
OSP
1
GND
Q
Q
S
R
VSD
VCC
AOCP
V
Good
CC
VAOCP
TSD
VOVP
Figure 2. Internal Block Diagram
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2
FSL136MR
PIN CONFIGURATION
GND
Drain
V
Drain
Drain
CC
8−DIP
V
FB
V
STR
I
PK
Figure 3. Pin Configuration
PIN DEFINITIONS
Pin No.
Name
GND
VCC
Description
1
2
Ground. SENSEFET source terminal on the primary side and internal control ground.
Positive Supply Voltage Input. Although connected to an auxiliary transformer winding, current is supplied from pin
5 (V
) via an internal switch during startup (see Figure 2). Once V reaches the UVLO upper threshold (12 V),
CC
STR
the internal startup switch opens and device power is supplied via the auxiliary transformer winding.
3
VFB
Feedback Voltage. The non−inverting input to the PWM comparator, it has a 0.4 mA current source connected inter-
nally, while a capacitor and opto−coupler are typically connected externally. There is a delay while charging external
capacitor C from 2.4 V to 6 V using an internal 5 mA current source. This delay prevents false triggering under tran-
FB
sient conditions, but still allows the protection mechanism to operate under true overload conditions.
4
5
IPK
Peak Current Limit. Adjusts the peak current limit of the SENSEFET. The feedback 0.4 mA current source is divert-
ed to the parallel combination of an internal 6 kW resistor and any external resistor to GND on this pin to determine
the peak current limit.
VSTR
Drain
Startup. Connected to the rectified AC line voltage source. At startup, the internal switch supplies internal bias and
charges an external storage capacitor placed between the V pin and ground. Once V reaches 12 V, the internal
CC
CC
switch is opened.
6, 7, 8
Drain. Designed to connect directly to the primary lead of the transformer and capable of switching a maximum of
650 V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−0.3
Max
650
650
26
Unit
V
V
STR
V
STR
Pin Voltage
V
Drain Pin Voltage
V
DS
CC
V
Supply Voltage
V
V
I
Feedback Voltage Range
Continuous Drain Current
Drain Current Pulsed (Note 4)
Single Pulsed Avalanche Energy (Note 5)
Total Power Dissipation
−0.3
12.0
3
V
FB
A
D
I
12
A
DM
E
AS
−
−
230
1.5
mJ
W
°C
°C
°C
kV
P
D
T
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
Internally Limited
J
T
−40
−55
5.0
+150
+150
A
T
STG
ESD
Human Body Model, JESD22−A114 (Note 6)
Charged Device Model, JESD22−C101 (Note 6)
1.5
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3
FSL136MR
ABSOLUTE MAXIMUM RATINGS (continued)
Symbol
Parameter
Junction−to−Ambient Thermal Resistance (Note 7, 8)
Min
Max
80
Unit
°C/W
Q
JA
Q
JC
Junction−to−Case Thermal Resistance (Note 7, 9)
Junction−to−Top Thermal Resistance (Note 7, 10)
19
Q
JT
33.7
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. Repetitive rating: pulse width limited by maximum junction temperature.
5. L = 51 mH, starting T = 25°C.
J
6. Meets JEDEC standards JESD 22−A114 and JESD 22−C101.
7. All items are tested with the standards JESD 51−2 and JESD 51−10.
8. Q free−standing, with no heat−sink, under natural convection.
JA
9. Q junction−to−lead thermal characteristics under Q test condition. T is measured on the source #7 pin closed to plastic interface for
JC
JA
JA
C
Q
thermo−couple mounted on soldering.
10.Q junction−to−top of thermal characteristic under Q test condition. Tt is measured on top of package. Thermo−couple is mounted in
JT
JA
epoxy glue.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
SENSEFET SECTION
−
−
−
BV
I
Drain−Source Breakdown Voltage
Zero Gate Voltage Drain Current
Drain−Source On−State Resistance
Input Capacitance
V
CC
V
DS
V
GS
V
GS
V
GS
V
GS
V
DD
V
DD
V
DD
V
DD
= 0 V, I = 250 mA
650
V
DSS
D
−
250
mA
= 650 V, V = 0 V
GS
DSS
−
−
−
−
−
−
−
−
R
= 10 V, V = 0 V, T = 25°C
3.5
290
45
4.0
W
DS(ON)
GS
C
−
C
= 0 V, V = 25 V, f = 1MHz
pF
pF
pF
ns
ns
ns
ns
ISS
DS
−
−
−
−
−
−
C
Output Capacitance
= 0 V, V = 25 V, f = 1MHz
DS
OSS
RSS
C
Reverse Transfer Capacitance
Turn−on Delay
= 0 V, V = 25 V, f = 1MHz
5.5
12
DS
t
= 350 V, I = 3.5 A
D
d(on)
t
Rise Time
= 350 V, I = 3.5 A
22
r
D
t
Turn−off Delay
= 350 V, I = 3.5 A
20
d(off)
D
t
Fall Time
= 350 V, I = 3.5 A
19
f
D
CONTROL SECTION
f
Switching Frequency
V
V
= 650 V, V = 0 V
61
67
5
73
10
kHz
%
OSC
DS
GS
= 10 V, V = 0 V, T = 125°C
Df
Switching Frequency Variation
Frequency Modulation
Maximum Duty Cycle
Minimum Duty Ratio
GS
GS
C
OSC
FM
f
3
kHz
%
D
V
V
= 4 V
= 0 V
71
0
77
0
83
0
MAX
FB
D
%
MIN
FB
V
UVLO Threshold Voltage
11
12
8.0
400
15
13
9.0
V
START
V
After Turn−on
7.0
V
STOP
I
FB
Feedback Source Current
V
= 0
320
10
480
20
mA
ms
FB
FB
t
Internal Soft−Start Time
V
= 4 V
S/S
BURST−MODE SECTION
Burst−Mode Voltage
V
BURH
T = 25°C
J
0.4
0.25
−
0.5
0.35
150
0.6
0.45
−
V
V
V
BURL
BURH(HYS)
V
mV
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4
FSL136MR
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
A
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
PROTECTION SECTION
I
Peak Current Limit
T = 25°C, di/dt = 300 mA/ms
1.89
200
5.5
2.15
2.41
A
ns
V
LIM
J
t
Current Limit Delay Time (Note 11)
Shutdown Feedback Voltage
Shutdown Delay Current
CLD
V
V
CC
V
FB
V
FB
= 15 V
= 5 V
6.0
5.0
6.5
6.5
SD
DELAY
I
3.5
mA
V
V
Over−Voltage Protection Threshold
= 2 V
22.5
24.0
1.00
1.60
25.5
1.35
OVP
t
Output Short
Protection (Note 11)
Threshold Time
T = 25°C
ms
V
OSP
J
OSP Triggered when ton < t
OSP
V
Threshold
Feedback Voltage
1.44
2.0
OSP
V
> V
and (Lasts Longer than
FB
OSP
)
t
OSP_FB
t
Feedback Blanking
Time
2.5
ms
OSP_FB
V
AOCP Voltage (Note 11)
T = 25°C
J
0.85
125
1.00
137
1.15
150
V
AOCP
T
Thermal Shutdown
(Note 11)
Shutdown
Temperature
°C
SD
HYS
Hysteresis
60
°C
TSD
t
Leading−Edge Blanking Time (Note 11)
300
ns
LEB
TOTAL DEVICE SECTION
I
I
Operating Supply Current (Note 11)
(While Switching)
V
V
= 14 V, V > V
2.5
1.8
1.1
3.5
2.5
1.5
mA
mA
OP1
CC
FB
BURH
Operating Switching Current, (Control Part
Only)
= 14 V, V < V
OP2
CC
FB
BURL
I
Startup Charging Current
V
V
= 0 V
0.9
35
mA
V
CH
CC
V
Minimum V
Supply Voltage
= V = 0 V, V
Increase
STR
STR
CC
FB
STR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Though guaranteed by design, it is not 100% tested in production.
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5
FSL136MR
TYPICAL PERFORMANCE CHARACTERISTICS
(These characteristics graphs are normalized T = 25.)
A
)
)
Figure 4. Operating Frequency vs. Temperature
Figure 5. Maximum Duty Cycle vs. Temperature
)
)
Figure 6. Operating Supply Current vs. Temperature
Figure 7. Start Threshold Voltage vs. Temperature
)
)
Figure 8. Stop Threshold Voltage vs. Temperature
Figure 9. Feedback Source Current vs. Temperature
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6
FSL136MR
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(These Characteristic graphs are normalized at T = 25.)
A
)
)
Figure 10. Startup Charging Current vs. Temperature
Figure 11. Peak Current Limit vs. Temperature
)
)
Figure 12. Burst Operating Supply Current vs.
Temperature
Figure 13. Over−Voltage Protection vs. Temperature
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7
FSL136MR
Feedback Control
FUNCTIONAL DESCRIPTION
FSL136MR employs current−mode control, as shown in
Figure 16. An opto−coupler (such as the FOD817A) and
shunt regulator (such as the KA431) are typically used to
implement the feedback network. Comparing the feedback
Startup
At startup, an internal high−voltage current source
supplies the internal bias and charges the external capacitor
(C ) connected with the V pin, as illustrated in Figure 14.
A
CC
voltage with the voltage across the R
resistor makes it
SENSE
When V reaches the start voltage of 12 V, the power
CC
possible to control the switching duty cycle. When the shunt
regulator reference pin voltage exceeds the internal
reference voltage of 2.5 V, the optocoupler LED current
switch begins switching and the internal high−voltage
current source is disabled. The power switch continues
normal switching operation and the power is provided from
the auxiliary transformer winding unless V goes below
the stop voltage of 8 V.
increases, the feedback voltage V is pulled down, and the
FB
CC
duty cycle is reduced. This typically occurs when the input
voltage is increased or the output load is decreased.
Figure 14. Startup Circuit
Figure 16. Pulse−Width−Modulation Circuit
Oscillator Block
Leading−Edge Blanking (LEB)
The oscillator frequency is set internally and the power
switch has a random frequency fluctuation function.
Fluctuation of the switching frequency of a switched power
supply can reduce EMI by spreading the energy over a wider
frequency range than the bandwidth measured by the EMI
test equipment. The amount of EMI reduction is directly
related to the range of the frequency variation. The range of
frequency variation is fixed internally; however, its
selection is randomly chosen by the combination of external
feedback voltage and internal free−running oscillator. This
randomly chosen switching frequency effectively spreads
the EMI noise nearby switching frequency and allows the
use of a cost− effective inductor instead of an AC input line
filter to satisfy the world−wide EMI requirements.
At the instant the internal SENSEFET is turned on, the
primary−side capacitance and secondary−side rectifier
diode reverse recovery typically cause a high−current spike
through the SENSEFET. Excessive voltage across the
R
SENSE
resistor leads to incorrect feedback operation in the
current−mode PWM control. To counter this effect, the
power switch employs a leading−edge blanking (LEB)
circuit (see the Figure 16). This circuit inhibits the PWM
comparator for a short time (t ) after the SENSEFET is
LEB
turned on.
Protection Circuit
The power switch has several protective functions, such
as overload protection (OLP), over−voltage protection
(OVP), output−short protection (OSP), under−voltage
lockout (UVLO), abnormal over−current protection
(AOCP), and thermal shutdown (TSD). Because these
various protection circuits are fully integrated in the IC
without external components, the reliability is improved
without increasing cost. Once a fault condition occurs,
switching is terminated and the SENSEFET remains off.
This causes V to fall. When V reaches the UVLO stop
CC
CC
voltage, V
(8 V), the protection is reset and the internal
STOP
high−voltage current source charges the V capacitor via
CC
the V
pin. When V reaches the UVLO start voltage,
STR
CC
V
START
(12 V), the power switch resumes normal operation.
In this manner, the auto−restart can alternately enable and
disable the switching of the power SENSEFET until the
fault condition is eliminated.
Figure 15. Frequency Fluctuation Waveform
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8
FSL136MR
Abnormal Over−Current Protection (AOCP)
When the secondary rectifier diodes or the transformer pin
are shorted, a steep current with extremely high di/dt can
flow through the SENSEFET during the LEB time. Even
though the power switch has OLP (Overload Protection), it
is not enough to protect the FPS in that abnormal case, since
severe current stress is imposed on the SENSEFET until
OLP triggers. The power switch includes the internal AOCP
(Abnormal Over−Current Protection) circuit shown in
Figure 19. When the gate turn−on signal is applied to the
power SENSEFET, the AOCP block is enabled and monitors
the current through the sensing resistor. The voltage across
the resistor is compared with a preset AOCP level. If the
sensing resistor voltage is greater than the AOCP level, the
set signal is applied to the latch, resulting in the shutdown of
the SMPS.
Figure 17. P−Widodulation uit
Overload Protection (OLP)
Overload is defined as the load current exceeding a preset
level due to an unexpected event. In this situation, the
protection circuit should be activated to protect the SMPS.
However, even when the SMPS is operating normally, the
overload protection (OLP) circuit can be activated during
the load transition or startup. To avoid this undesired
operation, the OLP circuit is designed to be activated after
a specified time to determine whether it is a transient
situation or a true overload situation.
Figure 19. Abnormal Over−Current Protection
In conjunction with the I current limit pin (if used), the
PK
Thermal Shutdown (TSD)
current−mode feedback path limits the current in the
SENSEFET when the maximum PWM duty cycle is
attained. If the output consumes more than this maximum
The SENSEFET and the control IC are integrated, making
it easier to detect the temperature of the SENSEFET. When
the temperature exceeds approximately 137°C, thermal
shutdown is activated.
power, the output voltage (V ) decreases below its rating
O
voltage. This reduces the current through the opto−coupler
LED, which also reduces the opto−coupler transistor
Over−Voltage Protection (OVP)
current, thus increasing the feedback voltage (V ). If V
FB
FB
In the event of a malfunction in the secondary−side
feedback circuit or an open feedback loop caused by a
soldering defect, the current through the opto−coupler
exceeds 2.4 V, the feedback input diode is blocked and the
5 mA current source (I ) starts to charge C slowly up
DELAY
FB
to V . In this condition, V increases until it reaches 6 V,
CC
FB
transistor becomes almost zero. Then, V climbs up in a
FB
when the switching operation is terminated, as shown in
Figure 18. The shutdown delay is the time required to charge
similar manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is activated. Because excess energy is
provided to the output, the output voltage may exceed the
rated voltage before the overload protection is activated,
resulting in the breakdown of the devices in the secondary
side. To prevent this situation, an over−voltage protection
C
from 2.4 V to 6 V with 5 mA current source.
FB
(OVP) circuit is employed. In general, V is proportional
CC
to the output voltage and the power switch uses V instead
CC
of directly monitoring the output voltage. If V exceeds 24
CC
V, OVP circuit is activated, resulting in termination of the
switching operation. To avoid undesired activation of OVP
during normal operation, V should be designed to be
CC
below 24 V.
Figure 18. Overload Protection (OLP)
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9
FSL136MR
Output−Short Protection (OSP)
Burst Operation
If the output is shorted, steep current with extremely high
di/dt can flow through the SENSEFET during the LEB time.
Such a steep current brings high−voltage stress on the drain
of SENSEFET when turned off. To protect the device from
To minimize power dissipation in standby mode, the FPS
enters burst mode. As the load decreases, the feedback
voltage decreases. As shown in Figure 22, the device
automatically enters burst mode when the feedback voltage
such an abnormal condition, OSP detects V
and
drops below V
. Switching continues, but the current
FB
BURH
SENSEFET turn−on time. When the V is higher than 1.6
V and the SENSEFET turn−on time is lower than 1.0 ms, the
limit is fixed internally to minimize flux density in the
transformer. The fixed current limit is larger than that
FB
FPS recognizes this condition as an abnormal error and shuts
defined by V = V
and, therefore, V is driven down
BURH FB
FB
down PWM switching until V reaches V
abnormal condition output is shown in Figure 20.
again. An
further. Switching continues until the feedback voltage
drops below V . At this point, switching stops and the
CC
START
BURL
output voltages start to drop at a rate dependent on the
standby current load. This causes the feedback voltage to
rise. Once it passes V
, switching resumes. The
BURH
feedback voltage then falls and the process repeats. Burst
mode alternately enables and disables switching of the
SENSEFET and reduces switching loss in standby mode.
Figure 20. Output Short Waveforms (OSP)
Soft−Start
The power switch has an internal soft−start circuit that
slowly increases the feedback voltage, together with the
SENSEFET current, after it starts. The typical soft−start
time is 20 ms, as shown in Figure 21, where progressive
increments of the SENSEFET current are allowed during the
startup phase. The pulse width to the power switching device
is progressively increased to establish the correct working
conditions for transformers, inductors, and capacitors. The
voltage on the output capacitors is progressively increased
with the intention of smoothly establishing the required
output voltage. Soft−start helps to prevent transformer
saturation and reduce the stress on the secondary diode.
Figure 22. Burst−Mode Operation
Adjusting Peak Current Limit
As shown in Figure 23, a combined 6 kW internal
resistance is connected to the non−inverting lead on the
PWM comparator. An external resistance of Rx on the
current limit pin forms a parallel resistance with the 6 kW
when the internal diodes are biased by the main current
source of 400 mA. For example, FSL136MR has a typical
1.25ms
ILIM
16Steps
Current Limit
SENSEFET peak current limit (I ) of 1.2 A. I
can be
LIM
LIM
adjusted to 0.8 A by inserting Rx between the I pin and the
ground. The value of the Rx can be estimated by the
following equations:
PK
0.25ILIM
Drain
Current
2.15A : 1.5A + 6kW : XkW
(eq. 1)
t
Figure 21. Internal Soft−Start
Ŧ
(eq. 2)
X + Rx 6kW
Where X is the resistance of the parallel network.
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10
FSL136MR
Figure 23. Peak Current Limit Adjustment
SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 9.42x6.38, 2.54P
CASE 646CM
ISSUE O
DATE 31 JUL 2016
9.83
9.00
8
1
5
6.670
6.096
4
8.255
TOP VIEW
7.610
1.65
1.27
(0.56)
7.62
3.683
3.200
5.08 MAX
3.60
3.00
0.33 MIN
0.356
0.200
15
°
0.560
0.355
°
0
2.54
9.957
7.62
FRONT VIEW
7.870
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS−001, VARIATION BA
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M−2009
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13468G
PDIP8 9.42X6.38, 2.54P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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