FSA3200UMX-F106_技术文档

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FSA3200 —Two-Port, High-Speed USB2.0 Switch with

Mobile High-Definition Link (MHL™)

Features

Description

.

Low On Capacitance: 2.7 pF / 3.1 pF MHL / USB

(Typical)

The FSA3200 is a bi-directional, low -pow er, tw o-port,

high-speed, USB2.0 and video data sw itch. Configured

as a double-pole, double-throw (DPDT) sw itch for data

and a single-pole, double-throw (SPDT) sw itch for ID; it

is optimized for sw itching betw een high- or full-speed

USB and Mobile Digital Video sources (MDV), including

supporting the MHL™ Rev. 2.0 specification.

.

Low Pow er Consumption: 30μA Maximum

Supports MHL Rev. 2.0

MHL Data Rate: 4.68 Gbps

V_BUSPow ers Device w ith No V_CC

Packaged in 16-Lead UMLP (1.8 x 2.6 mm)

The FSA3200 contains special circuitry on the sw itch

I/O pins, for applications w here the V_CCsupply is

pow ered off (V_CC=0), that allow s the device to w ithstand

an over-voltage condition. This sw itch is designed to

minimize current consumption even w hen the control

voltage applied to the control pins is low er than the

supply voltage (V_CC). This feature is especially valuable

to mobile applications, such as cell phones, allow ing

direct interface w ith the general-purpose I/Os of the

baseband processor. Other applications include

sw itching and connector sharing in portable cell phones,

digital cameras, and notebook computers.

Over-Voltage Tolerance (OVT) on all USB Ports

Up to 5.25 V w ithout External Components

Applications

.

Cell Phones and Digital Cameras

Ordering Information

Part Number Top Mark Operating Temperature Range

Package

16-Lead, Ultrathin Molded Leadless Package

(UMLP), 1.8 x 2.6 mm

FSA3200UMX

GB

-40 to +85°C

Figure 1. Analog Symbol

All trademarks are the property of their respective owners.

November-2017, Rev. 2

Publication Order Number:

FSA3200/D

Switch Power Operation

In normal operation, the FSA3200 is pow ered from the

V_CCpin, w hich typically is derived from a regulated

pow er management device. In special circumstances,

such as production test or system firmw are upgrade, the

device can be pow ered from the V_BUSpin. In this mode

of operation, a valid V_BUSvoltage is present (per USB2.0

specification) and V_CC=0 V, typically due to a no-battery

condition. With the SELn pins strapped LOW (via

external resistor), the FSA3200 closes the USB path,

enabling the initial programming of the system directly

f rom the USB connector. Once the system has normal

operating supply pow er w ith V_CCpresent, the V_BUS

supply is not utilized and normal sw itch operation

commences. Optionally, the Pow er Select Override

(PSO) pin can be set HIGH to force the device to be

pow ered from V_BUS

.

The V_BUS/ V_CCdetection capability is not intended to be

an accurate determination of the voltages present,

rather a state condition detection to determine w hich

supply should be used. These state determinations rely

on the voltage conditions as described in the Electrical

Characterization tables below .

V_BUS

V_CC

PSO

Switch

Power

Selection

Switch

Power

Source

Charge Pump

& Regulator

Switch

Power

Figure 2. Simplified Logic of Switch Power Selection Circuit

Table 1. Switch Power Selection Truth Table

V_CC

0

V_BUS

PSO⁽¹⁾

Switch Power Source

0

1

0

1

0

1

0

1

0

1

No sw itch pow er, sw itch paths high-Z

0

V_BUS

1

V_CC

1

V_CC

0

No sw itch pow er, sw itch paths high-Z

0

V_BUS

(2)

1

V_CC

1

V_BUS

Note s:

1. Control inputs should never be left floating or unconnected. If the PSO function is used, a w eakpull-up resistor

(3 MΩ) should be used to minimize static current draw . If the PSO function is not used, tie directly to GND.

2. PSO control is overridden w ith no V_BUSand the pow er selection is sw itched to V_CC

.

Table 2. Data Switch Select Truth Table

SEL1⁽³⁾

SEL2⁽³⁾

Function

0

1

0

1

0

1

D+/D- connected to USB+/USB-, ID_COconnected to ID_USB

D+/D- connected to USB+/USB-, ID_COMconnected to ID_MDV

D+/D- connected to MDV +/MDV-, ID_COMconnected to ID_USB

D+/D- connected to MDV +/MDV-, ID_COMconnected to ID_MDV

Note:

3. Control inputs should never be left floating or unconnected. To guarantee default sw itch closure to the USB

position, the SEL pins should be tied to GND w ith a w eakpull- dow n resistor (3 MΩ) to minimize static current draw .

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2

Pin Configuration

16

15

14

13

GND

1

2

3

12

11

ID_USB

MDV+

MDV-

SEL2

D+

D-

10

9

4

PSO

5

6

7

8

Figure 3. Pin Assignments (Top-Through View)

Pin Definitions

Pin#

Name

Description

1

2

GND

D+

Ground

Data Sw itch Output (Positive)

Data Sw itch Output (Negative)

Pow er Select Override

Data Sw itch Select

3

D-

4

PSO

SEL1

USB-

USB+

GND

SEL2

MDV -

MDV+

ID_USB

ID_MDV

ID_COM

V_BUS

V_CC

5

6

USB Differential Data (Negative)

USB Differential Data (Positive)

Ground

7

8

9

ID Sw itch Select

10

11

12

13

14

15

16

MDV Differential Data (Negative)

MDV Differential Data (Positive)

ID Sw itch MUX Output for USB

ID Sw itch MUX Output for MDV

ID Sw itch Common

Device Pow er w hen V_CCNot Available

(4)

Device Pow er from System

Note:

4. Device automatically sw itches f rom V _BUSw hen valid V_CCminimum voltage is present.

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3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_CC,V_BUS

V_CNTRL

Parameter

Min.

-0.5

Max.

5.5

Unit

V

Supply Voltage

DC Input Voltage (SELn, PSO)⁽⁵⁾

DC Sw itch I/O Voltage⁽⁵⁾

-0.5

V_CC

5.25

V

(6)

V_SW

-0.50

-50

V

DC Input Diode Current

I

IK

mA

°C

DC Output Current

I_OUT

T_STG

MSL

100

+150

1

Storage Temperature

-65

Moisture Sensitivity Level (JEDEC J-STD-020A)

Human Body Model, JEDEC: JESD22-A114

IEC 61000-4-2, Level 4, for D+/D- and V_CCPins ⁽⁷⁾

Charged Device Model, JESD22-C101

All Pins

Contact

Air

3.5

8.0

ESD

kV

15.0

2.0

Note s:

5. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed.

6. V_SWrefers to analog data sw itch paths (USB, MDV , and ID).

7. Testing performed in a system environment using TVS diodes.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor

does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_BUS

Parameter

Supply Voltage Running f rom V _BUSVoltage

Supply Voltage Running from V_CC

Min.

4.20

2.7

Max.

5.25

4.5

Unit

V

V_CC

V

t_RAMP(VBUS)Pow er Supply Slew Rate from V_BUS

t_RAMP(VCC)Pow er Supply Slew Rate from V_CC

100

1000

336

µs/V

C°/W

V

Θ_JA

Thermal Resistance

V_CNTRL

V_SW(USB)

V_SW(MDV)

T_A

Control Input Voltage (SELn, PSO)⁽⁸⁾

Sw itch I/O Voltage (USB and ID Sw itch Paths)

Sw itch I/O Voltage (MDV Sw itch Path)

Operating Temperature

0

4.5

-0.5

1.65

-40

3.6

V

3.45

+85

V

°C

Note :

8. The control inputs must be held HIGH or LOW; they must not float.

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4

DC Electrical Characteristics

All typical value are at T_A=25°C unless otherw ise specified.

T_A=- 40ºC to +85ºC

Min. Typ. Max.

-1.2

Symbol

Parameter

Condition

V_CC(V)

Unit

V_IK

V_IH

Clamp Diode Voltage

I =-18 mA

2.7

V

IN

Control Input Voltage High

SELn, PSO

2.7 to 4.3 1.25

2.7 to 4.3

V_IL

Control Input Voltage Low

Control Input Leakage

SELn, PSO

0.6

1

V

V_SW=0 V to 3.6 V,

V_CNTRL=0 V to 1.98 V

I

IN

4.3

0

-1

µA

Off-State Leakage for Open

MDV Data Paths

V_SW=1.65 V ≤ MDV

≤ 3.45 V

I_OZ(MDV)

I_OZ(USB)

I_OZ(ID)

1

µA

Off-State Leakage for Open

USB Data Paths

V_SW=0 V ≤ USB ≤ 3.6 V

V_SW=0 V ≤ ID ≤ 3.6 V

-1

Off-State Leakage for Open ID

Data Path

-0.5

-1

0.5

1

On-State Leakage for Closed

MDV Data Paths⁽⁹⁾

V

_SW=1.65 V ≤ MDV

≤ 3.45 V

I_CL(MDV)

I_CL(USB)

I_CL(ID)

On-State Leakage for Closed

USB Data Paths⁽⁹⁾

-1

1

V

_SW=0 V ≤ USB ≤ 3.6 V

_SW=0 V ≤ ID ≤ 3.6 V

On-State Leakage for

Closed⁽⁹⁾ID Data Path

-0.5

-1

0.5

1

Pow er-Off Leakage Current

(All I/O Ports)

I_OFF

V_SW=0 V or 3.6 V, Figure 5

HS Sw itch On Resistance

(USB to D Path)

V_SW=0.4 V, I_ON=-8 mA

Figure 4

R_ON(USB)

R_ON(MDV)

R_ON(ID)

2.7

4.3

3.9

5

6.5

Ω

HS Sw itch On Resistance

(MDV to D Path)

V_SW=V_CC-1050mV,

I_ON=-8mA , Figure 4

LS Sw itch On Resistance

(ID Path)

V_SW=3V, I_ON=-8mA

Figure 4

12

Difference in R_ONBetw een

MDV Positive-Negative

V_SW=V_CC-1050 mV,

I_ON=-8 mA, Figure 4,

∆R_ON(MDV)

∆R_ON(USB)

∆R_ON(ID)

0.03

0.18

0.4

1

Difference in R_ONBetw een

USB Positive-Negative

V_SW=0.4 V, I_ON=-8 mA

Figure 4

Difference in R_ONBetw een ID V_SW=3 V, I_ON=-8 mA

Sw itch Paths

Figure 4

V_SW=1.65 V to 3.45 V,

I_ON=-8 mA , Figure 4

R_ONF(MDV)Flatness for R_ONMDV Path

Ω

V_BUS=5.25 V, V_CNTRL=0 V or

1.98 V, I_OUT=0

I_VBUS

I_CC

Note :

V_BUSQuiescent Current

V_CCQuiescent Current

100

30

µA

V_BUS=0 V, V_CNTRL=0 V or

1.98 V, I_OUT=0

µA

9. For this test, the data sw itch is closed w ith the respective sw itch pin floating.

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5

AC Electrical Characteristics

All typical value are for V_CC=3.3 V and T_A=25°C unless otherw ise specified.

T_A=- 40ºC to +85ºC

Min. Typ. Max.

Symbol

Parameter

Condition

V_CC(V)

Unit

R_L=50 Ω, C_L=5 pF,

V_SW(USB)=0.8 V,

V_SW(MDV)=3.3 V,

Figure 6, Figure 7

Turn-On Time,

SELn to Output

t_ON

2.7 to 3.6

445

600

300

ns

R_L=50 Ω, C_L=5 pF,

V_SW(USB)=0.8 V, V_SW(MDV)=3.3V, 2.7 to 3.6

Figure 6, Figure 7

Turn-Off Time,

SELn to Output

t_OFF

125

ns

C_L=5 pF, R_L=50 Ω,

2.7 to 3.6

t_PD

Propagation Delay⁽¹⁰⁾

Break-Before-Make⁽¹⁰⁾

0.25

Figure 6, Figure 8

R_L=50 Ω, C_L=5 pF,

V_ID=V_MDV=3.3 V, V_USB=0.8 V,

t_BBM

2.7 to 3.6

2.0

13

Figure 10

V_S=1 V_pk-pk, R_L=50 Ω,

f=240 MHz, Figure 12

O_IRR(MDV)

O_IRR(USB)

Xtalk_MDV

2.7 to 3.6

-45

-38

-44

dB

Off Isolation⁽¹⁰⁾

V_S=400m V_pk-pk, R_L=50Ω,

f=240MHz, Figure 12

V_S=1 V_pk-pk, R_L=50 Ω,

f=240 MHz, Figure 13

Non-Adjacent Channel⁽¹⁰⁾

Crosstalk

V_S=400 mV _pk-pk, R_L=50 Ω,

f=240 MHz, Figure 13

Xtalk_USB

2.7 to 3.6

-39

dB

V_IN=1 V_pk-pk, MDV Path,

R_L=50 Ω, C_L=0 pF,

2.34

Figure 11, Figure 16

GHz

MHz

Differential -3 db

Bandw idth⁽¹⁰⁾

V_IN=400 mV_pk-pk, USB Path,

R_L=50 Ω, C_L=0 pF,

Figure 11, Figure 17

BW

2.7 to 3.6

1.59

100

ID Path, R_L=50 Ω, C_L=0 pF,

Figure 11

Note :

10. Guaranteed by characterization.

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6

USB High-Speed AC Electrical Characteristics

Typical values are at T_A= -40ºC to +85ºC.

Symbol

Parameter

Condition

V_CC(V)

3.0 to 3.6

Typ. Unit

Skew of Opposite Transitions of the Same

Output⁽¹¹⁾

t_SK(P)

C_L=5 pF, R_L=50 Ω, Figure 9

3

ps

R_L=50 Ω, C_L=5 pf,

t_R=t_F=500 ps (10-90%) at

480 Mbps, PN7

t_J

Total Jitter⁽¹¹⁾

15

Note:

11. Guaranteed by characterization.

MDV AC Electrical Characteristics

Typical values are at T_A= -40ºC to +85ºC.

Symbol

Parameter

Condition

V_CC(V) Typ. Unit

Skew of Opposite Transitions of the Same

Output⁽¹²⁾

t_SK(P)

R_PU=50 Ω to V_CC, C_L=0 pF

3.0 to 3.6

3

ps

Total Jitter⁽¹²⁾

15

f=2.25 Gbps, PN7,

R_PU=50 Ω to V_CC, C_L=0 pF

t_J

Note:

12. Guaranteed by characterization.

Capacitance

Typical values are at T_A= -40ºC to +85ºC.

Symbol

Parameter

Condition

Typ. Unit

C

Control Pin Input Capacitance⁽¹³⁾

V_CC=0 V, f= 1 MHz

1.5

3.1

IN

C_ON(USB)USB Path On Capacitance⁽¹³⁾

C_OFF(USB)USB Path Off Capacitance⁽¹³⁾

C_ON(MDV)MDV Path On Capacitance⁽¹³⁾

C_OFF(MDV)MDV Path Off Capacitance⁽¹³⁾

V_CC=3.3 V, f=240 MHz, Figure 15

V_CC=3.3 V, f=240 MHz, Figure 14

V_CC=3.3 V, f=240 MHz, Figure 15

V_CC=3.3 V, f=240 MHz, Figure 14

1.6

2.7

1.1

pF

Note:

13. Guaranteed by characterization.

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7

Test Diagrams

Note:

14. HSD refers to the high-speed data USB or MDV paths.

V_ON

I_Dn(OFF)

NC

A

HSD

n

Dn

V

SW

V

SW

Select

GND

ION

GND

V

_Sel= 0 orVcc

Select

**Each switch port is tested separately

V

Sel= 0 orV_C

R

= V_O/ I_ON

O

Figure 4. On Resistance

Figure 5. Off Leakage

t_RISE= 2.5ns

t_{F ALL}= 2.5ns

V

CC

90%

V

GND

Input–V , V

SEL1

SEL

V

CNTRL-HI

10%

90%

GND

V

OH

90%

Output- V

OUT

VO L

t_ON

t_OFF

Figure 6. AC Test Circuit Load

Figure 7. Turn-On / Turn-Off Waveforms

t_RISE

t_FALL

= 500ps

+400mV

-400mV

400mV

90%

0V

90%

50%

Input

0V

10%

t_PLH

t_PHL

V_OH

Output

50%

Output

V_OL

t_PHL

t_PLH

Figure 8. Propagation Delay (t_Rt_F– 500 ps)

Figure 9. Intra-Pair Skew Test t_SK(P)

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8

Test Diagrams (Continued)

t_RISE= 2.5ns

Vcc

HSD

n

90%

Vcc/2

Dn

C

Input -

V

Sel

SW1

10%

0V

V_OUT

GND

L

R

V

L

SW2

V_OUT

GND

0.9*Vout

GND

0.9*Vout

R

S

t_BBM

V

Sel

R_L, R and C_Lare function of application

GND

S

environment (see AC Tables for specific values)

C_Lincludes test fixture and stray capacitance

Figure 10. Break -Before -Make Interval Timing

Network Analyzer

Network

Analyzer

Network Analyzer

FSA3200

R

S

R

S

V

S

V

IN

V

OUT

V

GND

S

R

T

GND

OUT

GND

V

GND

R

Sel

S

V

OUT

GND

R

T

GND

V

IN

R

T

V

S

GND

R_Sand R_Tare functions of the application

environment (see AC Tables for specific values).

Off isolation = 20 Log (V_OUT/ V_IN

GND

V_S, R_Sand R_Tare function of application

environment (see AC/DC Tables for values)

)

Figure 11. Insertion Loss

Figure 12. Channel Off Isolation

Network Analyzer

NC

R

S

V

IN

V

GND

S

GND

V

Sel

GND

R

T

GND

V

OUT

GND

R

T

R_Sand R_Tare functions of the application environment

(see AC Tables for specific values).

GND

Crosstalk = 20 Log (V_OUT/ V_IN)

Figure 13. Non-Adjacent Channel-to-Channel Crosstalk

HSD

n

Capacitance

n

S

Meter

S

V

Capacitance

Meter

V

= 0 or V

cc

Sel

= 0 or V

cc

Sel

HSD

n

Figure 14. Channel Off Capacitance

Figure 15. Channel On Capacitance

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9

Insertion Loss

One of the key factors for using the FSA3200 in mobile

digital video applications is the small amount of insertion

loss experienced by the received signal as it passes

through the sw itch. This results in minimal degradation

of the received eye. One of the w ays to measure the

quality of the high data rate channels is using balanced

ports and 4-port differential S-parameter analysis,

particularly SDD21.

Bandw idth is measured using the S-parameter SDD21

methodology. Figure 16 show s the bandw idth (GHz) for

the MDV path and Figure 17 the bandw idth curve for the

USB path.

Figure 16. MDV Path SDD21 Insertion Loss Curve

Figure 17. USB Path SDD21 Insertion Loss Curve

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10

Typical Applications

Figure 18 show s the FSA3200 utilizing the V_BUS

connection from the micro-USB connector. The 3M

resistor is used to ensure, for manufacturing test via the

micro-USB connector, that the FSA3200 configures for

connectivity through the FSA9280A accessory sw itch.

Figure 19 show s the configuration for the FSA3200 “self

pow ered” by the battery only.

V_BAT

To USB Battery Charging Block

FSA9280A

Baseband or

Application

Processor

D+

D-

100 ohm

VBUS

UART_Tx

UART_Rx

ID

12

16

15

USB_D+

USB_D-

Spkr_R

Spkr_L

7

6

D+

D-

2

3

FSA3200

ID

GND

14

13

CBUS

MHL+

MHL-

11

10

microUSB

Connector

5

9

HDMI to MHL

Bridge

MHL_SEL

3M

GND

Figure 18. Typical FSA3200 Application Using V_BUS

V_BAT

To USB Battery Charging Block

FSA9280A

Baseband or

Application

Processor

D+

D-

GND

UART_Tx

UART_Rx

VBUS

15

ID

12

16

USB_D+

USB_D-

Spkr_R

Spkr_L

7

6

D+

2

D-

3

FSA3200

ID

GND

14

13

CBUS

MHL+

MHL-

11

10

microUSB

Connector

5

9

HDMI to MHL

Bridge

MHL_SEL

3M

GND

Figure 19. Typical FSA3200 “Self-Powered” Application Using V_BAT

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11

Physical Dimensions

2.10

0.563(15X)

0.10 C

1.80

A

B

0.663

0.40

2X

1

2.60

2.90

PIN#1 IDENT

0.10 C

TOP VIEW

0.225

(16X)

2X

RECOMMENDED

LAND PATTERN

0.55 MAX.

0.152

0.10 C

0.08 C

TERMINAL SHAPE VARIANTS

SEATING

PLANE

C

0.05

0.00

0.40

0.60

SIDE VIEW

0.30

0.50

0.15

0.25

0.15

0.25

0.10

15X

0.45

0.10

0.35

PIN 1

NON-PIN 1

5

Supplier 1

9

0.40

0.30

0.50

0.15

0.25

0.15

15X

0.25

0.30

0.50

15X

1

PIN 1

NON-PIN 1

PIN#1 IDENT

Supplier 2

13

16

0.25

0.15

0.55

0.45

0.10 C A B

0.05 C

BOTTOM VIEW

R0.20

PACKAGE

EDGE

NOTES:

A. PACKAGE DOES NOT FULLY CONFORM TO

JEDEC STANDARD.

LEAD

OPTION 2

SCALE : 2X

LEAD

OPTION 1

SCALE : 2X

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

D. LAND PATTERN RECOMMENDATION IS

BASED ON FSC DESIGN ONLY.

E. DRAWING FILENAME: MKT-UMLP16Arev4.

F. TERMINAL SHAPE MAY VARY ACCORDING

TO PACKAGE SUPPLIER, SEE TERMINAL

SHAPE VARIANTS.

Figure 20. 16-Lead, Ultrathin Molded Leadless Package (UMLP)

Package drawings are providedas a service to customers consideringON Semiconductor components.Drawings may change in

any manner without notice. Please notethe revision and/or dateon the drawing andcontact an ON Semiconductor representative to

verify or obtain the most recent revision.Package specifications do notexpand the terms of ON Semiconductor’s worldwideterms

and conditions, specifically the warranty therein,which covers ON Semiconductor products.

www.onsemi.com

12

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13


型号：	FSA3200UMX-F106
厂家：	ONSEMI
描述：	两端口，高速 USB2.0 开关，带 Mobile High-Definition Link 开关
文件：	总14页 (文件大小：688K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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