FS6128-07 [ONSEMI]
PLL Clock Generator IC with VXCO; PLL时钟发生器IC与VXCO
| 型号： | FS6128-07 |
| 厂家： | 
ONSEMI |
| 描述： | PLL Clock Generator IC with VXCO |
| 文件： | 总6页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FS6128-07
PLL Clock Generator IC with VXCO
1.0 Key Features
• Matches MK3727 center frequency characteristics
• Phase-locked loop (PLL) device synthesizes output clock frequency from crystal oscillator or external reference clock
• On-chip tunable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning
• 3.3V supply voltage
• Very low phase noise PLL
• Use with “pullable” 14pF crystals – no external pad-ding capacitors required
• Small circuit board footprint (8-pin 0.150” SOIC)
• Custom frequency selections available - contact your local ON Semiconductor sales representative for more information
2.0 Description
The FS6128 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems.
At the core of the FS6128 is circuitry that implements a voltage-controlled crystal oscillator (VCXO) when an external resonator
(nominally 13.5MHz) is attached. The VCXO allows device frequencies to be precisely adjusted for use in systems that have frequency
matching requirements, such as digital satellite receivers.
A high-resolution phase-locked loop generates an output clock (CLK) through a post-divider. The CLK frequency is ratiometrically
derived from the VCXO frequency. The locking of the CLK frequency to other system reference frequencies can eliminate unpredictable
artifacts in video systems and reduce electromagnetic interference (EMI) due to frequency harmonic stacking.
1
2
3
4
8
7
6
5
XIN
VDD
XOUT
VSS
XTUNE
VSS
VDD
CLK
Figure 1: Pin Configuration – 8-pin (0.150”) SOIC
Table 1: Crystal / Output Frequencies
Device
FS128-07
fXIN (MHz)
13.500
CLK (MHz)
27.000
Note: Contact ON Semiconductor for custom PLL frequencies.
©2008 SCILLC. All rights reserved.
May 2008 – Rev. 2
Publication Order Number:
FS6128-07/D
FS6128-07
XIN
CLK
VCXO
PLL
DIVIDER
XOUT
XTUNE
FS6128-07
Figure 2: Block Diagram
Table 2: Pin Descriptions
Pin
1
Type
AI
Name
XIN
Description
VCXO feedback
2
3
4
P
AI
P
VDD
XTUNE
VSS
Power supply (+3.3V)
VCXO tune
Ground
5
6
7
8
DO
-
DO
AO
CLK
VDD
VSS
Clock output
Power supply (+3.3V)
Ground
XOUT
VCXO drive
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input With Internal Pull-Up; DID = Input With Internal Pull-Down; DIO = Digital
Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low Pin
3.0 Functional Block Diagram
3.1 Voltage-Controlled Crystal Oscillator (VCXO)
The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6128 system components. Loading capacitance for
the crystal is internal to the FS6128. No external components (other than the resonator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The value of this voltage
controls the effective capacitance presented to the crystal. The actual amount that this load capacitance change will alter the oscillator
frequency depends on the characteristics of the crystal as well as the oscillator circuit itself.
It is important that the crystal load capacitance is specified correctly to “center” the tuning range. See Table 5.
A simple formula to obtain the “pulling” capability of a crystal oscillator is:
where:
C0 = the shunt (or holder) capacitance of the crystal
C1 = the motional capacitance of the crystal
CL1 and CL2 = the two extremes (minimum and maximum) of the applied load capacitance presented by the FS6128
Rev. 2 | Page 2 of 6 | www.onsemi.com
FS6128-07
EXAMPLE: A crystal with the following parameters is used: C1 = 0.025pF and C0 = 6pF. Using the minimum and maximum
CL1 = 10pF, and CL2 = 20pF, the tuning range (peak-to-peak) is:
3.2 Phase-Locked Loop (PLL)
The on-chip PLL is a standard frequency- and phase locked loop architecture. The PLL multiplies the reference oscillator frequency to
the desired output frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error (unless otherwise
specified).
4.0 Electrical Specifications
Table 3: Absolute Maximum Ratings
Parameter
Supply voltage (Vss = ground)
Input voltage, DC
Output voltage, DC
Input clamp current, DC (VI < 0 or VI > VDD
Symbol
VDD
VI
VO
IIK
Min.
VSS – 0.5
VSS – 0.5
VSS – 0.5
-50
Max.
7
VDD + 0.5
VDD + 0.5
50
Units
V
V
V
)
mA
Output clamp current, DC (VI < 0 or VI > VDD
)
IOK
-50
50
mA
Storage temperature range (non-condensing)
Ambient temperature range, under bias
Junction temperature
TS
TA
TJ
-65
-55
150
125
125
°C
°C
°C
Lead temperature (soldering, 10s)
Input static discharge voltage protection (MLD-STD 883E, Method 3015.7)
260
2
Per IPC/JEDEC J-STD-020B
kv
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress
rating only and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied.
Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high energy
electrostatic discharge.
Table 4: Operating Conditions
Parameter
Supply voltage
Ambient operating temperature range
Crystal resonator frequency
Symbol
VDD
TA
fXTAL
Conditions/Descriptions
Min.
3.0
0
Typ.
3.3
Max.
3.6
70
Units
V
°C
3.3V ± 10%
Functional mode
12
13.5
18
MHz
Table 5: DC Electrical Specifications
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FS6128-07
Parameter
Symbol
Conditions/Descriptions
Min.
Typ.
Max.
Units
Overall
Supply current, dynamic, with loaded outputs
Supply current, static
IDD
IDD
fXAL = 13.5MHz; CL = 10pF; VDD = 3.6V
XIN = 0V; VDD = 3.6V
30
3
mA
mA
Voltage-Controlled Crystal Oscillator (contact factory for approved crystal sources or other application assistance)
Order crystal for this capacitance
(parallel load) at desired center
frequency
Specified motional capacitance of the
crystal will affect pullability (see text)
Crystal loading capacitance at center tuning
voltage
CL(xtal)
C1
14
25
pF
fF
Crystal resonator motional capacitance
XTUNE effective range
0
3
V
Synthesized load capacitance min.
Synthesized load capacitance max.
CL1
CL2
@V(XTUNE) = minimum value
@V(XTUNE) = maximum value
fXTAL = 13.5MHz; CL(xtal) = 14pF; C1(xtal)
= 25fF (peak-to-peak)
10
20
pF
pF
VCXO tuning range
300
ppm
Note: positive change of XTUNE =
positive change of VCXO frequency
RXTAL = 20Ω; CL = 20pF
VCXO tuning characteristic
150
200
ppm/V
Crystal drive level
μW
Clock Output (CLK)
High-level output source current*
Low-level output sink current*
IOH
IOL
ZOH
ZOL
IOSH
IOSL
VO = 2.0V
VO = 0.4V
VO = 0.1VDD; output driving high
VO = 0.1VDD; output driving low
VO = 0V; shorted for 30s, max.
VO = 3.3V; shorted for 30s, max.
-40
17
25
25
-55
55
mA
mA
Output impedance*
Ω
Short circuit source current*
Short circuit sink current*
mA
mA
Note: Unless otherwise stated VDD = 3.3V ±10% no load on any output and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an
asterisk (*) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization
data are ±3σ from typical. Negative currents indicate current flows out of the device.
Table 6: AC Timing Specifications
Parameter
Symbol
Conditions/Descriptions
Min.
Typ.
Max.
Units
Overall
VCXO stabilization time*
PLL stabilization time*
Synthesis error
Clock Output (CLK)
Duty cycle*
tVCXOSTB
tPLLSTB
From power valid
From VCXO stable
(Unless otherwise noted in frequency table)
10
100
ms
μs
ppm
0
Ratio of high pulse width (as measured from rising edge to next
falling edge at VDD/2) to one clock period
45
55
%
Jitter, period (peak-peak)*
Jitter, long term (σγ(τ))*
Rise time*
From rising edge to next rising edge at VDD/2, CL = 10pF
From 0-500μs at VDD/2, CL = 10pF compared to ideal clock source
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
200
100
1.7
ps
ps
ns
ns
tj(ΔP)
tj(LT)
tr
Fall time*
tf
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
1.7
Note: Unless otherwise stated, VDD = 3.3V ±10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an
asterisk (*) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization
data are ±3σ from typical.
Rev. 2 | Page 4 of 6 | www.onsemi.com
FS6128-07
5.0 Package Information
Table 7: 8-pin SOIC (0.150") Package Dimensions
Dimensions
Inches
Max.
Millimeters
Min.
0.061
0.004
0.055
0.013
0.0075
0.189
0.150
Min.
Max.
1.73
0.249
1.55
0.49
0.249
4.98
3.99
A
A1
A2
B
C
D
E
0.068
0.0098
0.061
0.019
0.0098
0.196
0.157
1.55
0.102
1.40
0.33
0.191
4.80
3.81
e
0.050 BSC
1.27 BSC
H
h
L
0.230
0.010
0.016
0°
0.244
0.016
0.035
8°
5.84
0.25
0.41
0°
6.20
0.41
0.89
8°
Θ
Table 8: 8-pin SOIC (0.150") Package Characteristics
Parameter
Thermal impedance, junction to free-air 8-pin 0.150” SOIC
Lead inductance, self
Symbol Conditions/Descriptions
Typ.
110
2.0
Units
°C/W
Air flow = 0 m/s
ΘJA
L11
Corner lead
nH
Center lead
1.6
Lead inductance, mutual
Lead capacitance, bulk
L12
C11
Any lead to any adjacent lead
Andy lead to VSS
0.4
0.27
nH
pF
Rev. 2 | Page 5 of 6 | www.onsemi.com
FS6128-07
6.0 Ordering Information
Part Number
FS6128-07-XTD
FS6128-07-XTP
Package
8-pin (0.150”) SOIC
8-pin (0.150”) SOIC
Shipping Configuration
Tube/Tray
Tape & Reel
Temperature Range
0°C to 70°C (commercial)
0°C to 70°C (commercial)
7.0 Revision History
Revision Date
Modification
1
2
March 2004
May 2008
Initial release
Update to new ON Semiconductor template
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
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parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
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