FQN1N60CTA [ONSEMI]
功率 MOSFET,N 沟道,QFET®,600 V,0.3 A,11.5 Ω,TO-92;型号: | FQN1N60CTA |
厂家: | ONSEMI |
描述: | 功率 MOSFET,N 沟道,QFET®,600 V,0.3 A,11.5 Ω,TO-92 开关 晶体管 |
文件: | 总8页 (文件大小:424K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MOSFET – N-Channel
QFET)
600 V, 0.3 A, 11.5 W
FQN1N60C
Description
www.onsemi.com
This N−Channel enhancement mode power MOSFET is produced
using ON Semiconductor’s proprietary planar stripe and DMOS
technology. This advanced MOSFET technology has been especially
tailored to reduce on−state resistance, and to provide superior
switching performance and high avalanche energy strength. These
devices are suitable for switched mode power supplies, active power
factor correction (PFC), and electronic lamp ballasts.
S
D
G
Features
TO−92 4.75x4.80
CASE 135AV
• 0.3 A, 600 V, R
= 11.5 ꢀ (Max.) @ V = 10 V,
GS
DS(on)
I = 0.15 A
D
• Low Gate Charge (Typ. 4.8 nC)
• Low Crss (Typ. 3.5 pF)
• 100% Avalanche Tested
D
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
G
Symbol
Parameter
Drain to Source Voltage
Value
600
30
Unit
V
V
DSS
V
GSS
S
Gate to Source Voltage
Drain Current
V
I
D
A
Continuous (T = 25°C)
0.3
0.18
C
MARKING DIAGRAM
Continuous (T = 100°C)
C
I
Drain Current − Pulsed
(Note 1)
1.2
33
A
mJ
A
DM
A/FQN
1N60C
YWW
E
Single Pulsed Avalanche Energy (Note 2)
AS
AR
I
Avalanche Current
(Note 1)
(Note 1)
(Note 3)
0.3
0.3
4.5
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
mJ
V/ns
AR
dv/dt
P
D
(T = 25°C)
1
3
0.02
W
W
W/°C
A
(T = 25°C)
L
Derate above 25°C
A
= Assembly Site
T , T
Operating and Storage Temperature Range −55 to +150
°C
°C
J
STG
FQN1N60C
Y
WW
= Specific Device Code
= Year of Production
= Work Week Number
T
Maximum Lead Temperature for Soldering,
1/8″ from Case for 5 Seconds
300
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
1. Repetitive Rating: Pulse width limited by maximum junction temperature.
Device
FQN1N60CTA
Package
Shipping
2000 / Fan−Fold
2. L = 59 mH, I = 1.1 A, V = 50 V, R = 25
ꢀ
ꢁ
S
t
a
r
t
i
n
g
T
=
2
5
°
C
.
AS
DD
G
DSS
J
TO−92 3LD
3. I ≤ 0.3 A, di/dt ≤ 200 A/ꢂ s, V ≤ BV
, Starting T = 25°C.
J
SD
DD
© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
June, 2021 − Rev. 2
FQN1N60C/D
FQN1N60C
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
50
Unit
R
R
Thermal Resistance, Junction−to−Lead, Max.
Thermal Resistance, Junction−to−Ambient, Max.
(Note 5)
(Note 6)
°C/W
ꢃ
JL
140
ꢃ
JA
ELECTRICAL CHARACTERISTICS (T = 25°C, unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTIC
BV
Drain to Source Breakdown Voltage
I
I
= 250 ꢂ A, V = 0 V
600
−
−
−
V
DSS
D
GS
ꢄ
B
V
Breakdown Voltage Temperature
Coefficient
−
0.6
V/°C
= 250 ꢂ A, Referenced to 25°C
DSS
J
D
/ꢄ T
I
Zero Gate Voltage Drain Current
V
DS
V
DS
V
GS
V
GS
= 600 V, V = 0 V
−
−
−
−
−
−
−
−
50
250
100
−100
ꢂ
A
DSS
GS
= 480 V, T = 125°C
C
I
Gate to Body Leakage Current, Forward
Gate to Body Leakage Current, Reverse
= 30 V, V = 0 V
nA
nA
GSSF
DS
I
= −30 V, V = 0 V
DS
GSSR
ON CHARACTERISTICS
V
R
Gate Threshold Voltage
V
GS
V
GS
V
DS
= V , I = 250 ꢂ A
2.0
−
−
4.0
11.5
−
V
ꢀ
S
GS(th)
DS
D
Static Drain to Source On−Resistance
Forward Transconductance
= 10 V, I = 0.15 A
9.3
DS(on)
D
g
FS
= 40 V, I = 0.3 A
−
0.75
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
V
DD
V
DS
= 25 V, V = 0 V, f = 1.0 MHz
−
−
−
130
19
170
25
6
pF
pF
pF
iss
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
3.5
rss
SWITCHING CHARACTERISTICS
t
Turn−On Delay Time
Turn−On Rise Time
Turn−Off Delay Time
Turn−Off Fall Time
Total Gate Charge
= 300 V, I = 1.1 A, R = 25
ꢀ
−
−
−
−
−
−
−
7
24
52
36
64
6.2
−
ns
ns
d(on)
D
G
(Note 4)
t
21
13
27
4.8
0.7
2.7
r
t
ns
d(off)
t
ns
f
Q
= 480 V, I = 1.1 A, V = 10 V
nC
nC
nC
g
D
GS
(Note 4)
Q
Gate to Source Charge
Gate to Drain Charge
gs
gd
Q
−
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
Maximum Continuous Drain to Source Diode Forward Current
Maximum Pulsed Drain to Source Diode Forward Current
−
−
−
−
−
−
−
0.3
1.2
1.4
−
A
A
S
I
SM
V
SD
Drain to Source Diode Forward Voltage
Reverse Recovery Time
V
GS
V
GS
= 0 V, I = 0.3 A
−
V
S
t
rr
= 0 V, I = 1.1 A, dI /dt = 100 A/ꢂ s
190
0.53
ns
ꢂ C
S
F
Q
Reverse Recovery Charge
−
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of operating temperature.
5. Reference point of the R
is the drain lead.
ꢃ
JL
6. When mounted on 3”x4.5” FR−4 PCB without any pad copper in a still air environment
(R
is the sum of the junction−to−case and case−to−ambient thermal resistance. R
is determined by the user’s board design)
ꢃ
ꢃ
JA
CA
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2
FQN1N60C
TYPICAL CHARACTERISTICS
V
GS
Top:
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
5.0 V
4.5 V
0
10
0
10
150°C
−55°C
Bottom:
25°C
−1
10
10
Notes:
1. 250 μs Pulse Test
Notes:
1. V = 40 V
DS
2. T = 25°C
C
2. 250 μs Pulse Test
−2
−1
10
−1
0
1
10
10
10
2
4
6
8
10
V
DS
, Drain to Source Voltage (V)
V
GS
, Gate to Source Voltage (V)
Figure 2. Transfer Characteristics
Figure 1. On−Region Characteristics
30
25
20
15
V
= 10 V
GS
0
10
V
= 20 V
GS
150°C
10
5
Notes:
1. V = 0 V
2. 250 μs Pulse Test
25°C
GS
Note: T = 25°C
J
−1
0
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.0
0.5
1.0
1.5
2.0
2.5
V
SD
, Source to Drain Voltage (V)
I , Drain Current (A)
D
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
Figure 3. On−Resistance Variation vs.
Drain Current and Gate Voltage
250
200
150
100
50
12
C
C
C
= C + C (C = shorted)
iSS
gs
gd
ds
= C + C
OSS
ds
gd
V
= 120 V
DS
= C
gd
rss
10
8
V
= 300 V
DS
C
C
iSS
V
= 480 V
DS
OSS
6
Notes:
4
1. V = 0 V
GS
Cr
SS
2. f = 1 MHz
2
Note: I = 1.1 A
D
0
0
−1
0
1
10
0
1
2
3
4
5
6
10
10
V
DS
, Drain to Source Voltage (V)
Q , Total Gate Charge (nC)
G
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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3
FQN1N60C
TYPICAL CHARACTERISTICS (Continued)
1.2
1.1
1.0
0.9
0.8
3.0
2.5
2.0
1.5
1.0
Notes:
1. V = 0 V
GS
Notes:
1. V = 10 V
2. I = 0.15 A
D
2. I = 250 ꢂ A
D
0.5
0.0
GS
−100
−50
0
50
100
150
200
−100
−50
0
50
100
150
200
T , Junction Temperature (5C)
J
T , Junction Temperature (5C)
J
Figure 8. On−Resistance Variation
Figure 7. Breakdown Voltage Variation
vs. Temperature
vs. Temperature
0.3
0.2
0.1
0.0
Operation in This Area
is Limited by R
DS(on)
0
10
100 ꢂ s
1 ms
10 ms
100 ms
Notes:
1. T = 25°C
DC
C
2. T = 150°C
3. Single Pulse
J
−1
10
0
1
2
3
10
10
10
10
25
50
75
100
125
150
V
DS
, Drain to Source Voltage (V)
T , Case Temperature (5C)
C
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
2
10
D = 0.5
1
0.2
10
10
0.1
0.05
0.02
0.01
0
Notes:
1. Z
2. Duty Factor, D = t /t
(t) = 50°C/W Max.
ꢃ
JL
single pulse
1
2
3. T − T = P
JM DM
∗ Z
ꢃ
(t)
JL
L
−1
10
−5
−4
−3
−2
−1
0
1
2
3
10
10
10
10
10
10
10
10
10
t , Square Wave Pulse Duration (s)
1
Figure 11. Transient Thermal Response Curve
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4
FQN1N60C
V
GS
Same Type
as DUT
50 kꢀ
Q
g
12 V
200 nF
300 nF
V
DS
Q
Q
gd
gs
V
GS
DUT
I
G
= const.
Charge
Figure 12. Gate Charge Test Circuit & Waveform
R
V
V
L
DS
90%
V
DS
V
DD
V
GS
R
G
10%
GS
DUT
V
GS
t
t
d(off)
d(on)
t
r
t
f
t
off
t
on
Figure 13. Resistive Switching Test Circuit & Waveforms
1
BV
DSS
L
2
E
AS
=
LI
AS
BV
− V
DD
2
V
DS
DSS
BV
DSS
I
D
I
AS
R
G
V
DD
I (t)
D
V
GS
DUT
V
DS
(t)
V
DD
t
p
t
p
Time
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
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5
FQN1N60C
+
DUT
V
DS
_
I
DS
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
• dv/dt controlled by R
G
• I controlled by pulse period
SD
Gate Pulse Width
D =
V
Gate Pulse Period
GS
10 V
(Driver)
I
, Body Diode Forward Current
FM
I
SD
di/dt
(DUT)
I
RM
Body Diode Reverse Current
V
DS
(DUT)
Body Diode Recovery dv/dt
V
DD
V
SD
Body Diode
Forward Voltage Drop
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
QFET is a registered trademark of Semiconductor Components Industries, LLC.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 3LD 4.75x4.80
CASE 135AV
ISSUE O
DATE 07 JAN 2021
1
2
3
GENERIC
MARKING DIAGRAM*
AXXXX
XXXXX
YWW
XXXX = Specific Device Code
A
Y
= Assembly Location
= Year
1
2
3
WW = Work Week
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON29250H
TO−92 3LD 4.75X4.80
PAGE 1 OF 1
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