FPF2487 概述
Dual Channel Over-Voltage Protection Load Switch
FPF2487 数据手册
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February 2015
FPF2487
Dual Channel Over-Voltage Protection Load Switch
Description
Features
The FPF2487 features a 2-channel power switch, which
.
.
Dual Channel Power Switch (VBUS and VIF)
Surge Protection under IEC 61000-4-5
offers surge protection and Over-Voltage Protection
(OVP), to protect downstream components and
enhancing overall system robustness.
•
•
VBUS: 100 V
VIF: 40 V
Channel one (VBUS) is an active-low, 28 V/2.5 A rated,
power MOSFET switch with an internal clamp
supporting 100 V surge protection, highly accurate
fixed OVP at 5.95 V ( 50 mV), and OTG functionality.
Channel two (VIF) is a conditional active-high, 6 V/6 A
rated, power MOSFET switch with an integrated TVS
supporting 40 V surge protection and fixed OVP at
5.25 V ( 250 mV). VIF also provides Reverse Current
Blocking (RCB) during its OFF state to minimize
leakage current.
.
.
.
Input Voltage Range
•
•
VBUS: 2.5 V ~ 23 V
VIF: 3.1 V ~ 5.5 V
Max. Continuous Current Capability
•
•
VBUS: 2.5 A
VIF: 6 A
Ultra Low On-Resistance
VBUS_DET is paired with always ON LDO to power
downstream devices even with VBUS is greater than
2.5 V, even when disabled through the ONB pin. This
provides power sequence control or a host controlled
configuration in system.
-
-
VBUS: Typ. 33 mΩ
VIF: Typ. 11 mΩ
.
Over-Voltage Protection
-
-
VBUS: 5.95 V 50 mV
VIF: 5.25 V 250 mV
The FPF2487 is available in a 15-bump, 1.6 mm x
2.2 mm Wafer-Level Chip-Scale Package (WLCSP) with
0.4 mm pitch.
.
.
.
.
.
LDO Output based VBUS_DET for VBUS Detection
Active Low Control for VBUS Path
Related Resources
OTG Functionality on VBUS Path
.
http://www.fairchildsemi.com/
Conditional Active High Control for VIF Path
Reverse-Current Blocking for VIF Path
Applications
.
.
Mobile Handsets and Tablets
Wearable Devices
Ordering Information
Operating Temperature
Range
Packing
Method
Part Number
Top Mark
Package
FPF2487UCX
-40°C – +85°C
GX
15-Ball, 0.4 mm Pitch WLCSP
Tape & Reel
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPF2487 • Rev. 1.4
Application Diagram
Battery
Charger
Travel
Adapter
System
VOUT
BAT
VBUS
VIF
Test JIG
FPF2487
BATTERY
ONB
ON
PMIC
VBUS_DET
GND
Figure 1.
Typical Application
Block Diagram
FPF2487
VOUT
BAT
VBUS
VIF
TVS
TVS
OVLO
RCB
VBUS
UVLO
OVLO
LDO
VBUS_DET
ON
CONTROL
LOGIC
w/ Charge
pump
ONB
THERMAL
SHUTDOWN
GND
Figure 2.
Functional Block Diagram
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPF2487 • Rev. 1.4
2
Pin Configuration
1
2
3
3
2
1
A
B
C
D
E
VOUT
A
B
C
D
E
VOUT
ON
VOUT
ONB
ONB
VOUT
VBUS
GND
VIF
VBUS
GND
VIF
ON
GND
BAT
BAT
VBUS
VBUS
VBUS_
DET
VBUS_
DET
GND
BAT
BAT
VIF
VIF
VIF
VIF
BAT
BAT
Figure 3.
Pin Configuration (Top View)
Figure 4.
Pin Configuration (Bottom View)
Pin Definitions
Name
Bump
B2, B3
Type
Input/Supply Switch Input and Device Supply
Output Switch Output to Load
Input/Supply Switch Input and Device Supply
Description
VBUS
VOUT
VIF
A1, A2
D2, D3, E3
D1, E1, E2
C3
BAT
Output
Output
Input
Switch Output to Battery
VBUS_DET
ON
Regulated Output according to VBUS
Active HIGH: VIF path only and when BAT is valid prior to VIF
Active LOW: VBUS path only
B1
ONB
GND
A3
Input
C1, C2
GND
Ground
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPF2487 • Rev. 1.4
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max. Unit
VBUS
VIF
VBUS to GND & VBUS to VOUT=GND or Float
VIF to GND
-0.3
-2(1)
-0.3
-0.3
29.0
V
V
6
VIN + 0.3
VIF + 0.3
8
VOUT
VOUT to GND
V
BAT
BAT to GND
V
VBUS_DET
VON(B)
VBUS_DET to GND
V
ONB or ON to GND
Continuous VBUS Current
Peak VBUS Current (5 ms)
Continuous VIF Current
Peak VIF Current (5 ms)
6
V
2.5
A
IIN_VBUS
5
A
6
A
IIN_VIF
12
A
IIN_VBUS_DET Continuous VBUS_DET Current
1
mA
W
°C
C
C
°C/W
tPD
TSTG
TJ
Total Power Dissipation at TA=25°C
1.54
+150
+150
+260
81(2)
Storage Temperature Range
-65
Maximum Junction Temperature
TL
Lead Temperature (Soldering, 10 Seconds)
Thermal Resistance, Junction-to-Ambient(2) (1-in.2 Pad of 2-oz. Copper)
JA
Air Discharge
15
8
IEC 61000-4-2 System
Level ESD
Contact Discharge
Human Body Model,
ANSI/ESDA/JEDEC JS- All Pins
001-2012
ESD
kV
V
2
1
Electrostatic Discharge
Capability
Charged Device Model,
All Pins
JESD22-C101
VBUS
100
40
IEC 61000-4-5,
Surge Protection
VIF
Surge
Notes:
1. Pulsed, 50 ms maximum non-repetitive.
2. Measured using 2S2P JEDEC std. PCB.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VBUS
VIF
Supply Voltage, VBUS
Supply Voltage, VIF
2.5
3.1
23.0
5.5
V
V
CIN / COUT Input and Output Capacitance
CVBUS_DET Output Capacitance
0.1
μF
μF
°C
0.47
-40
TA
Operating Temperature
+85
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPF2487 • Rev. 1.4
4
Electrical Characteristics
Unless otherwise noted, VBUS=2.5 to 23 V, VIF=3.1 to 5.5 V, TA=-40 to 85°C; Typical values are at VBUS=5 V, IIN ≤ 2 A,
VIF=4 V, CIN=0.1 μF and TA=25°C.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Basic Operation
VBUS=5 V, ONB=0 V, VBUS_DET=Floating
VIF=4 V
160
100
150
100
140
250
150
205
180
μA
μA
μA
μA
°C
IQ
Input Quiescent Current
VBUS=12 V, VOUT=0 V, VBUS_DET=Floating
VIF=5.5 V, BAT=0 V
IIN_Q
OVLO Supply Current
Thermal Shutdown(3)
TSDN
Thermal Shutdown
Hysteresis(3)
TSDN_HYS
20
°C
VBUS to VOUT Switch
VBUS_CLAMP Input Clamping Voltage
IIN=10 mA
35
V
V
VBUS Rising, TA=-40 to 85°C
VBUS Falling, TA=-40 to 85°C
VBUS=5 V, IOUT=1 A, TA=25°C
VBUS=9 V, IOUT=1 A, TA=25°C
5.90
5.8
5.95
6.00
VBUS_OVLO Over-Voltage Trip Level
RON_VBUS On-Resistance
V
33
33
39
39
mΩ
mΩ
Time from VBUS_MIN < VBUS < VBUS_OVLO to
VOUT=0.1 × VBUS
tDEB_VBUS Debounce Time
tSTART_VBUS Soft-Start Time
15
30
3
ms
ms
ms
Time from VBUS=VBUS_MIN to 0.1 × VBUS_DET
RL=100 Ω, CL=22 µF, VOUT from 0.1 × VBUS to
0.9 × VBUS
tON_VBUS
Switch Turn-On Time
RL=100 Ω, No CL, VBUS > VBUS_OVLO to
VOUT=0.8 × VBUS
tOFF_VBUS Switch Turn-Off Time
150
ns
VIF to BAT Switch
VIF_CLAMP Input Clamping Voltage
IIN=10 mA
6.4
2.85
2.7
V
V
VIF Rising, TA=-40 to 85°C
VIF Falling, TA=-40 to 85°C
VIF Rising, TA=-40 to 85°C
VIF Falling, TA=-40 to 85°C
VIF=3.1 V, IOUT=1 A, TA=25°C
VIF=0 V, BAT=4.4 V
3.05
5.50
VIF_UVLO
Under-Voltage Trip Level
V
5.00
4.8
5.25
V
VIF_OVLO Over-Voltage Trip Level
V
RON_VIF
IRCB
On-Resistance
10
3
15
7
mΩ
μA
Reverse Current
Time from VIF_UVLO < VIF < VIF_OVLO to
BAT=0.1 × VIF
tDEB_VIF
Debounce Time
Qualification Tim
15
2
ms
ms
BAT > VIH_BAT First, Time from ON >
VIH_ON(B) to BAT Voltage Increase
tQUAL_VIF
RL=100 Ω, CL=22 µF, VOUT from 0.1 × VIF to
0.9 × VIF
tON_VIF
Switch Turn-On Time
Switch Turn-Off Time
2
ms
ns
tOFF_VIF
RL=100 Ω, No CL,VIN > VOVLO to VOUT=0.8 × VIF
150
Note:
3. Guaranteed by characterization and design.
Continued on the following page…
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPF2487 • Rev. 1.4
5
Electrical Characteristics (Continued)
Unless otherwise noted, VBUS=2.5 to 23 V, VIF=3.1 to 5.5 V, TA=-40 to 85°C; Typical values are at VBUS=5 V, IIN ≤ 2 A,
VIF=4 V, CIN=0.1 μF and TA=25°C.
Symbol
VBUS_DET
Parameter
Conditions
Min. Typ. Max. Unit
VBUS=6.5 V, IBUS_DET=0 mA, TA=25°C
VBUS=15 V, IBUS_DET=0 mA, TA=25°C
VBUS=6.5 V, IBUS_DET=1 mA, TA=25°C
VBUS=15 V, IBUS_DET=1 mA, TA=25°C
6.0
6.0
6.0
6.0
6.5
7.9
6.5
7.9
V
V
V
V
7.0
6.3
7.0
VBUS_DET
VBUS_DET Output Voltage
Digital Signals
VIH_ON(B)
Enable HIGH Voltage
VBUS, VIF Operating Range
VBUS, VIF Operating Range
BAT Rising
1.2
2.5
V
V
VIL_ON(B)
Enable LOW Voltage
0.5
VIH_BAT
BAT Presence HIGH Voltage
BAT Presence LOW Voltage
V
VIL_BAT
BAT Falling
1.7
1
V
IVBUS_DET_LEAK VBUS_DET Leakage Current
ON(B)_Leak ON(B) Leakage Current
VVBUS_DET=5 V, VBUS=0 V
VBUS=5 V, VOUT=Float
µA
µA
1
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPF2487 • Rev. 1.4
6
Timing Diagrams
VBUS
tDEB_VBUS
tOFF_VBUS
Measure @
80% ONB to
VOUT = 0.8*VBUS
VOUT
tON_VBUS
Measure
@ 10/90%
ONB
tSTART_VBUS
Measure VBUS > VBUS_MIN
to 0.1*VBUS_DET
VBUS_DET
Figure 5.
Timing for VBUS Power Up/Down and Normal Operation
tSTART_VBUS
tSTART_VBUS
VOVLO
VBUS
tOFF_VBUS
Measure @
OVLO_Rising to
VOUT = 0.8*VIN
VOUT
VBUS_DET
Figure 6.
Timing for VBUS OVLO Operation (ONB=LOW)
VBUS > OVLO
OVLO
VBUS < OVLO
VBUS
VBUS_Min
tSTART_VBUS
Measure VBUS_Min to
0.1*VBUS_DET
VBUS_DET
Figure 7.
Always ON VBUS_DET Operation (ONB=HIGH)
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPF2487 • Rev. 1.4
7
Timing Diagrams (Continued)
VIF
tDEB_VIF
tOFF_VIF
Measure @
UVLO_Falling to
VOUT = 0.8*VIF
BAT
tON_VIF
Measure
@ 10/90%
Figure 8.
Timing for VIF Power Up/Down and Normal Operation (ON=Don’t Care)
VIF (>BAT)
BAT (> VIH_BAT)
tDEB_VIF
ON
Figure 9.
Timing for VIF Power Up/Down and Normal Operation with ON Pin
VOVLO
VIF
tOFF_VIF
Measure @
tDEB_VIF
OVLO_Rising
BAT = 0.8*VIF
BAT
Figure 10. Timing for VIF OVLO Operation (ON=Don’t Care)
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPF2487 • Rev. 1.4
8
VIF Turn-On Qualification State Diagram
Figure 11. VIF Turn-On Qualification State Diagram
Notes:
4. Case #1 is reflecting removable battery system without ON signal.
5. Case #2 is reflecting embedded battery system with ON signal.
Product-Specific Package Dimensions
D
E
X
Y
2200 μm ±30 μm
1600 μm ±30 μm
400 μm ±18 μm
300 μm ±18 μm
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPF2487 • Rev. 1.4
9
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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