FPF2283CUCX [ONSEMI]
28 V / 7 A 额定 OVP，具有超低导通电阻和水分检测;
| 型号： | FPF2283CUCX |
| 厂家： | 
ONSEMI |
| 描述： | 28 V / 7 A 额定 OVP，具有超低导通电阻和水分检测 |
| 文件： | 总19页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FPF2283CUCX
28 V / 7 A Rated OVP with
Ultra Low On-resistance
Switch and Moisture
Detection
www.onsemi.com
Description
FPF2283C is a super OVP with ultra low on−resistance single
2
channel switch controlled by external logic pin or I C interface. The
device contains an N−MOSFET that can operate over an input voltage
range of 2.8 V to 28 V and can support a maximum continuous current
of 10 A.
1
When the input voltage exceeds the over−voltage threshold, the
internal FET is turned off immediately to prevent damage to the
protected downstream components. When in detection mode, the
internal current source and ADC can be used to calculate the resistance
on VIN for moisture detection.
FPF2283CUCX is available in a small 20 bumps WLCSP package
and operate over the free−air temperature range of −40°C to +85°C.
WLCSP20
CU SUFFIX
CASE 567UT
MARKING DIAGRAM
3HKK
XYZ
Features
• Over−voltage Protection Up to +28 V
3H
KK
XY
Z
= Specific Device Code
= 2−digit Lot Run Code
= 2−digit Date Code
= 1−digit Plant Code
• Internal Low R
NMOS Transistors: Typical 7.5 mW
DS(on)
• Programmable Over−voltage Lockout (OVLO)
♦ Externally Adjustable via ADJ Pin
2
♦ Programmable via I C Interface
• Active−low Enable Pin for Device
PIN CONNECTIONS
• Super Fast OVLO Response Time: Typical 50 ns
1
2
3
4
5
2
• I C Communication with System
• 8−bits ADC for Moisture Detection on VIN
• Short Circuit Protection and Auto−restart
EN
INT
ADJ
VOUT VOUT VOUT
A
B
C
D
• Over Temperature Protection (Thermal Shutdown)
• +40 V Surge Capability Base on IEC61000−4−5
GND
GND
SDA
VIN
VIN
VIN
VIN
VIN
VIN
• System Level ESD Base on IEC61000−4−2
VDD
SCL
♦ 8 kV Contact Discharge
♦ 15 kV Air Gap Discharge
VOUT VOUT VOUT
• Robust ESD Performance
♦ 3.5 kV Human Body Model (HBM)
♦ 1 kV Charged Device Model (CDM)
(Top View)
Typical Applications
• Mobile Phones
• PDAs
ORDERING INFORMATION
†
Device
FPF2283CUCX
Package
Shipping
• GPS
WLCSP20
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
January, 2019 − Rev. 1
FPF2283CUCX/D
FPF2283CUCX
VBUS
1uF
Switching
Charger
Travel
Adapter
VIN
VOUT
1uF
Legacy USB /
USB Type C connector
Direct
Charger
FPF2283C
3.3V
VDD
R1
R2
INTB
SCL
SDA
ADJ
#EN
GND
Processor
VIO VIO VIO
Figure 1. Application Schematic – Adjustable Option
Vout
Vin
VDD
Gate Drive
Vref
SCL
SDA
I2C
int
ADJ
Control
GND
Figure 2. Simplified Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin #
Name
Description
B3, B4, B5,
C3, C4, C5
IN
Power Input: Switch Input and Device Supply
A3, A4, A5,
D3, D4, D5
OUT
Power Output: Switch Output to Load
B1
A1
A2
C1
D1
D2
INTB
ENB
ADJ
VDD
SCL
SDA
Interrupt: Open−drain output. Pull down to ground when any FLAG register alarms.
Enable Input: Active LOW.
OVLO Input: Over Voltage Lockout Adjustment Input
2
Power supply: Supply for ADC and I C communication during communication
Serial Clock Input: Be used to synchronize data movement on the I2C serial interface
Serial Data Input/Output: Input / Output pin for the 2−wire serial interface. Open−drain output and
requires an external pull−up resistor.
B2, C2
GND
Ground
www.onsemi.com
2
FPF2283CUCX
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage Range (Note 1)
Output Voltage Range
V
in
−0.3 to 28
V
out
−0.3 to (V + 0.3)
V
in
I/O pin voltage Range
ENB, INTB, SCL, SDA
−0.3 to 6
−0.3 to 6
−0.3 to 28
0 to 10
150
V
VDD Voltage Range
V
DD
V
Adjustable Input Range
ADJ
V
Internal FET continuous current
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charge Device Model (Note 2)
IEC 61000−4−2 SYSTEM Level ESD
I
A
OUT
T
°C
°C
kV
J(max)
TSTG
−65 to 150
3.5
ESDHBM
ESDCDM
Contact
1
8
Air Gap
15
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
T
SLD
260
°C
Moisture Sensitivity
MSL
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latch−up Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, WLCSP−20 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
R
36.5
°C/W
q
JA
4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
5. Values based on 2S2P JEDEC std. PCB.
Table 4. RECOMMENDED OPERATING RANGES
Rating
Symbol
Min
2.8
3.0
1.5
0
Max
23
Unit
V
Supply Voltage on VIN
Supply Voltage on VDD
V
in
V
DD
5.5
5.5
5.5
7
V
2
I C interface
SDA, SCL
V
I/O pins
ADJ, INTB, ENB
V
Output Current
VIN Capacitor
VOUT Capacitor
Ambient Temperature
I
0
A
out
C
0.1
0.1
−40
mF
mF
°C
in
C
out
T
A
85
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
3
FPF2283CUCX
Table 5. ELECTRICAL CHARACTERISTICS V = 2.5 to 23 V, C = 0.1 mF, C = 0.1 mF, T = −40 to 85°C; For typical values
in
in
out
A
V
in
= 5.0 V, I ≤ 3 A, C = 0.1 mF, T = 25°C, for min/max values T = −40°C to 85°C; unless otherwise noted. (Note 6)
in
in
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
LEAKAGE AND QUIESCENT CURRENTS
Input Quiescent Current on VIN
V
V
V
= 5 V, ENB = 0 V, 0x01 = 8’h00
= 20 V, ENB = 0 V, 0x01 = 8’h00
I
Q
100
150
mA
IN
IN
Input Quiescent Current on VDD
= 3.3 V, ENB = 0 V, 0x01 = 8’hC0,
100
DD
0x06 = 8’h00, 0x07 = 8’h00 (detection
mode, 0 A, single pulse)
V
= 3.3 V, ENB = 0 V, VIN = 0V,
30
1
DD
0x01 = 8’h00 (charging mode)
VDD Current consumption of ADC
VDD = 3.3 V, ENB = 0 V, 0x01 = 8’hC0,
0x06 = 8’h00, 0x07 = 8’hF0
I
mA
ADC
Device shutdown current
VIN = 5 V, ENB = 3.3 V, VOUT = 0 V
I
5
10
100
0.5
mA
nA
mA
SHDN
ADJ Input Leakage Current
INTB and SDA Output leakage
V
ADJ
= V
I
ADJ
−100
OVLO_TH
V
= 3 V, Interrupt De−asserted
I
LEAK
PULL_UP
OVER VOLTAGE AND UNDER VOLTAGE LOCKOUT
Under−Voltage Rising Trip Level for VIN
Under−Voltage Falling Trip Level for VIN
Under−Voltage Falling Trip Level for VDD
UVLO Hysteresis for VDD
V
V
V
rising, T = −40 to 85°C
V
IN_UV_R
2.47
2.6
2.6
2.5
2.8
100
6.8
2.8
3.0
V
V
IN
A
falling, T = −40 to 85°C
V
IN_UV_F
IN
A
falling, T = −40 to 85°C
V
V
DD
A
DD_UV_F
HYS_VDD
V
mV
V
Default Over−Voltage Trip Level
V
IN
rising, T = −40 to 85°C, refer to
V
6.6
7.0
A
IN_OVLO
2
register table for other value set by I C
OVLO set threshold
V
= 1.1 V to 1.3 V, the voltage of
V
1.18
1.204
2
1.22
V
ADJ
OVLO_TH
ADJ to trigger OVLO
OVLO threshold hysteresis
Adjustable OVLO range
I/O THRESHOLDS
V
%
V
HYS_OVLO
OV_MODE = 0, V
> 0.5 V
V
4
23
ADJ
OV_RNG
SCL, SDA and ENB Threshold Voltage
Voltage Increasing, Logic High
Voltage Decreasing, Logic Low
V
V
V
High
Low
V
V
1.2
0.3
IH
0.4
IL
ADJ Input Threshold Voltage
Voltage Increasing, Logic High
Voltage Decreasing, Logic Low
High
Low
V
IH_ADJ
V
0.15
0.4
IL_ADJ
INTB and SDA Output Low Voltage (Note 8)
RESISTANCE
I
= 1 mA, logic Low asserted
V
OL
OUT
On−resistance of Power FET
Pull−down resistor on ENB
V
IN
= 5 V, I
= 500 mA, T = 25°C
r
7.5
mW
kW
OUT
A
ON
r
1000
PD
MOISTURE DETECTION
Current Source for Moisture Detection
Set by register: 04h
I
0.001
10
60
mA
ms
SRC
Settle time for I
and ADC (Note 8)
t
SET
SRC
Resolution of ADC
RES
8
0
Bits
V
ADC Full Scale Voltage Range
LSB Voltage of ADC
Powered by V ; V w 2.1 V
V
FSV
V
LSB
2.04
DD
DD
8
mV
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
7. Refer to the APPLICATION INFORMATION section.
8. Values based on design and/or characterization.
9. Depends on the capacitance on ADJ pin.
www.onsemi.com
4
FPF2283CUCX
Table 5. ELECTRICAL CHARACTERISTICS V = 2.5 to 23 V, C = 0.1 mF, C = 0.1 mF, T = −40 to 85°C; For typical values
in
in
out
A
V
in
= 5.0 V, I ≤ 3 A, C = 0.1 mF, T = 25°C, for min/max values T = −40°C to 85°C; unless otherwise noted. (Note 6)
in
in
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
2
I C INTERFACE
SCL clock frequency
Stand Mode
f
100
400
1000
4.7
1.3
0.5
4
kHz
kHz
kHz
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
SCL
Fast Mode
Fast Mode Plus
Bus Free Time Between STOP and START Stand Mode
conditions (Note 8)
t
BUF
Fast Mode
Fast Mode Plus
START or Repeated START Hold Time
(Note 8)
Stand Mode
Fast Mode
t
HD;STA
0.6
0.26
4.7
1.3
0.5
4
Fast Mode Plus
Stand Mode
Fast Mode
LOW Period of SCL Clock (Note 8)
HIGH Period of SCL Clock (Note 8)
Repeated START Setup Time (Note 8)
Stop Condition Setup Time (Note 8)
Data Setup Time (Note 8)
t
LOW
Fast Mode Plus
Stand Mode
Fast Mode
t
HIGH
0.6
0.26
4.7
0.6
0.26
4
Fast Mode Plus
Stand Mode
Fast Mode
t
t
SU;STA
Fast Mode Plus
Stand Mode
Fast Mode
SU;STO
0.6
0.26
250
100
50
Fast Mode Plus
Stand Mode
Fast Mode
t
SU;DAT
Fast Mode Plus
Stand Mode
Fast Mode
Data Hold Time (Note 8)
t
0
3.45
0.9
HD;DAT
0
Fast Mode Plus
Stand Mode
Fast Mode
0
0.45
1000
300
120
1000
300
120
300
300
120
400
SCL Rising Time (Note 8)
t
20+0.1C
20+0.1C
20+0.1C
20+0.1C
20+0.1C
20+0.1C
20+0.1C
20+0.1C
20+0.1C
RCL
b
b
b
b
b
b
b
b
b
Fast Mode Plus
Stand Mode
Fast Mode
SDA Rising Time (Note 8)
t
RDA
Fast Mode Plus
Stand Mode
Fast Mode
SDA Falling Time (Note 8)
t
FDA
Fast Mode Plus
Capacitive Load for SDA and SCL
C
b
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
7. Refer to the APPLICATION INFORMATION section.
8. Values based on design and/or characterization.
9. Depends on the capacitance on ADJ pin.
www.onsemi.com
5
FPF2283CUCX
Table 5. ELECTRICAL CHARACTERISTICS V = 2.5 to 23 V, C = 0.1 mF, C = 0.1 mF, T = −40 to 85°C; For typical values
in
in
out
A
V
in
= 5.0 V, I ≤ 3 A, C = 0.1 mF, T = 25°C, for min/max values T = −40°C to 85°C; unless otherwise noted. (Note 6)
in
in
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
2
I C INTERFACE
Pulse width of spikes which must be sup-
pressed by input filter (Note 8)
t
SP
0
50
ns
Slave Address
Read
Write
1101100
200
TIMING
Hard−short protection auto−restart time
Time from power switch turned off to be-
ing turned on
t
ms
HS_RST
Interrupt maximum duration
t
1000
22
ms
ms
INTB
De−bounce Time of Power FET turned on
Time from 2.5 V < V < V
to
t
SW_DEB
IN
IN_OVLO
V
= 0.1 x V
OUT
IN
Soft−Start Time (Note 8)
Time from de−bounce time finished to
t
15
2
ms
ms
SS
Power Switch fully turn on
Switch Turn−On rising Time (Note 8)
Switch Turn−Off Time (Note 8)
V
V
= 5 V, R = 100 W, C = 22 mF,
t
R
IN
L
L
from 0.1 x V to 0.9 x V
OUT
IN
IN
R = 10 W, C = 0 mF, time from V
>
L
L
IN
V
to V
= 0.9 x V
OVLO
OUT
IN
Internal OVP level
External OVP level (Note 9)
50
ns
ns
100
THERMAL SHUTDOWN
Thermal Shutdown Temperature (Note 8)
Thermal Shutdown Hysteresis (Note 8)
T
T
−
−
130
20
−
−
°C
°C
SD
SH
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
7. Refer to the APPLICATION INFORMATION section.
8. Values based on design and/or characterization.
9. Depends on the capacitance on ADJ pin.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
6
FPF2283CUCX
TYPICAL CHARACTERISTICS
Figure 3. ON−resistance @ VIN = 5 V
Figure 4. ON−resistance @ VIN = 23 V
Figure 5. ON−resistance vs. Input Voltage
Figure 6. Quiescent Current vs. Input Voltage
www.onsemi.com
7
FPF2283CUCX
Function Description
General
hard−short condition keeps, the switch will be turned off and
re−try again after t
FPF2283CUCX is an OVP power switch to protect next
.
HS_RST
stage system which is optimized to lower voltage working
condition. The device includes ultra low on−resistance power
FET (7 mW) and super fast OVP response time (50 ns).
The device integrates moisture detection function to
detect the resistance on VIN side. The communication with
Thermal Shutdown
When the device is in the switch mode, to protect the
device from over temperature, the power switch will be
turned off when the junction temperature exceeds T
INTB will be triggered to ground. At the meantime,
OT_FLG will be set to 1 and latched. The switch will be
.
SD
2
processor can be done via I C interface.
Power MOSFET
turned on again when temperature drop below T − T
.
SD
SH
The FPF2283CUCX integrates an N−type MOSFET with
8 mW resistance. The power FET can work under 2.8 V ~
23 V and up to 7 A DC current capability.
Interrupt
The processor recognizes interrupt signals by observing
the INTB signal of FPF2283CUCX, which is active LOW
and open−drain. Interrupts are masked during VIN or VDD
power up. The INTB pin is default floating in preparation for
an interrupt.
By default, when the following event occurs, INTB
transitions LOW: Over Voltage Lockout, Over Current
Protection, Over Temperature Protection, Over TAG of
VIN, Detection Timeout, Power Switch turned on, Power
applied on VIN.
Power Supply
The FPF2283CUCX is supplied by both VIN and VDD.
When both VDD and VIN drop below threshold, the entire
chip will stop working. When only VDD drops, detection
mode will not be working anymore.
Enable Control
The ENB pin is active low control of FPF2283CUCX with
1 MW pull down resistor. When ENB is tight to ground or
floating, the device is alive and ready to be configured by
internal registers. When ENB is HIGH, the device will be
turned off entirely including the power switch.
When the following event occurs, INTB transitions
HIGH: Read clear, Interrupt time−out, t
down, Hardware disable; ENB pin is pulled.
start, Power
DET
Moisture detection
FPF2283CUCX provide a Moisture Detection, or called
resistance detection, feature to help the system detect any
Under Voltage Lockout
FPF2283CUCX power switch will be turned off when the
voltage on VIN is lower than the UVLO threshold
2
risk on VBUS. The detection can be setup via I C bus.
V
.
IN_UV_F
The Moisture Detection includes two parts:
1. A programmable current source which will be
applied to VIN;
Whenever VIN voltage ramps up to higher than
, the register 0x01 will be reset to default value
V
IN_UV_R
and the power FET will be turned on automatically after
de−bounce time if there is no OV or OT condition.
2. An 8−bits ADC to detect the voltage on VIN.
t
DEB
2
While the voltage value is read via I C, resistance between
VIN and GND can be calculated through the formula:
Over Voltage Lockout
The power FET will be turned off whenever VIN voltage
VVIN
ISRC
RVIN
+
(eq. 2)
higher than V
. The value of V
can be set by
IN_OVLO
IN_OVLO
2
external resistor ladder or by internal registers via I C
communication.
Where V
is a value can be looked up from the value of
VIN
register 0x08.
The Moisture Detection will be implemented during t
When V
≤ 0.15 V or OV_MODE = 1, V
is
ADJ
OVLO
.
decided by internal registers. When V
> 0.3 V and
DET
ADJ
t
is only valid when all the following conditions met:
OV_MODE = 0, the power switch will be turned off once
> V . The external resistor ladder can be
DET
1. The register DET_EN is set to 1’b1;
2. The status is under detecting period according to
V
ADJ
OVLO_TH
decided according to the following equation:
t
and t
set by register 05h.
BLNK
DET
R1
ǒ1 ) R2Ǔ
V
IN_OVLO + VOVLO_TH
(eq. 1)
The moisture detection will only be available when
external supply VDD is applied. The detection result can be
used to decide if there is significant leakage on VBUS or
other power line. The programmable current source is
convenient for different measurement range and for
different input capacitance.
where R1 and R2 are the resistors in Figure 1.
INTB will be triggered to ground when OV event appears.
At the meantime, OV_FLG will be set to 1 and latched.
Hard Short Protection
When the VOUT is short to ground, the power switch will
be turned off to protect the system and power supply. If
The moisture detection function makes it possible for
system to find out the abnormal condition on USB connector
www.onsemi.com
8
FPF2283CUCX
before power source is applied. It provides a safer way than
temperature detection to prevent huge leakage burning
connector.
FPF2283CUCX has 3 modes for different speed. Different
speed has different power consumption level.
The device has its slave address for I C communication
2
with fixed length of 7−bits (7’b1101100).
I2C interface
2
FPF2283CUCX allows I C communication to program
Register Mapping
the registers. Registers will control the OVP, I
for moisture detection. I C communication is only valid
when VDD supply is higher than 1.5 V. The I C of
and ADC
There are registers integrated in FPF2283CUCX. The
registers can be used to control the device or get the status
information. Register table is followed:
SRC
2
2
Defaul
t Value
Address
0x00
Description
ID Register
Bit[7]
0
Bit[6]
0
Bit[5]
0
Bit[4]
0
Bit[3]
1
Bit[2]
0
Bit[1]
0
Bit[0]
1
0x01
Enable Register
00 h
00 h
SW_ENB
PON_STS
DET_EN
TAG_STS
Reserved
TMO_STS
Reserved
SW_STS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x02
Detection status
Register
0x03
0x04
Switch Flag
Register
00 h
00 h
Reserved
Reserved
TAG_MSK
Reserved
Reserved
SW_MSK
Reserved
Reserved
OV_FLG
OV_MSK
HS_FLG
HS_MSK
OT_FLG
OT_MSK
Interrupt mask
register
PON_MSK
TMO_MSK
0x05
0x06
0x07
Working Mode
Isource to VIN
30 h
00 h
00 h
Reserved
Reserved
TDET3
RNG2
Reserved
TDET2
RNG1
Reserved
TDET1
RNG0
Reserved
TDET0
OV_MODE
ISRC3
Reserved
ISRC2
OV1
OV0
ISRC1
TBLK1
ISRC0
TBLK0
Isource
Working Time
TBLK3
TBLK2
0x08
0x09
Voltage on VIN
(0V~2.04V,
8mV LSB)
00 h
FF h
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
Set Tag of VIN
TH_VIN7
TH_VIN6
TH_VIN5
TH_VIN4
TH_VIN3
TH_VIN2
TH_VIN1
TH_VIN0
Identification Register
Address: 00h, Bit [7:0]
Type: Read Only
Description: Vendor ID and Revision ID
Bit Name
VID
Bit #
7:3
Value
5’b00001
3’b001
Description
Vendor ID for customer recognition
Revision ID
RID
2:0
Enable Register
Address: 01h, Bit [7:6]
Default Value: 2’b00
Type: Read / Write
Function: Control the working mode of FPF2283CUCX
Bit Name
Bit #
Value
Description
Written by processor via I C or cleared during POR.
2
SW_ENB
7
0 (Default)
Turned on the power switch if UV, OV, Hard Short, OT condition cleared and detection not
being implemented.
2
1
Written by processor via I C.
Power switch OFF.
2
DET_EN
6
0 (Default)
Written by processor via I C or cleared during POR.
Moisture Detection is not applied until the state of this bit changed. The detection related
registers will not be reset.
2
1
Written by processor via I C.
Moisture Detection turned on. If VIN voltage is lower than V
, I
and ADC will
IN_UVLO_F SRC
be applied on VIN in t
, which is defined by register 04h.
DET
NOTE: The status 2’b01 is invalid. Any writing action 2’b01 to these two bits will be looked as invalid writing and not executed.
www.onsemi.com
9
FPF2283CUCX
The register SW_ENB is an active−low control bit for the
The register DET_EN is an active−high control bit for the
Switch Mode. Writing SW_ENB to 1 will turn off the power
FET in any case, while writing it to 0 will switch the device
into Switch Mode. In Switch Mode, the power FET will be
turned on if no over stress condition is detected for at least
Detection Mode. When DET_EN = 0, the moisture detection
setup (including I
and ADC) will not be implemented.
SRC
When DET_EN = 1, the device will enter the detection
mode. During Detection Mode, current source and ADC will
work according to the setup in register 0x06 and 0x07.
t
.
DEB
Detection Status Register
Address: 02h, Bit [7:0]
Default Value: 3’b000
Type: Read
Bit Name
Bit #
Value
0 (Default)
1
Description
PON_STS
7
Initialed by POR or set by function defined. Indicate the condition that VIN is lower than V
Set by FPF2283CUCX.
.
IN_UVLO_F
The voltage on VIN is higher than V
when ENB is low.
IN_UVLO_R
TAG_STS
TMO_STS
SW_STS
6
5
4
0 (Default)
Initialed by POR or cleared when the value in register 08h is smaller than the value in 09h.
Set by FPF2283CUCX. The value in register 08h is larger than the value in 09h.
1
0 (Default)
Initialed by POR or cleared when t
begins. Refer to diagram.
DET
1
0 (Default)
1
Set by FPF2283CUCX during t
. Refer to diagram.
BLNK
Initialed by POR or cleared when the power switch is turned off when ENB tight low.
Set by FPF2283CUCX. The power switch is turned on when ENB tight low.
PON_STS is a register bit indicates the power on status.
Unless ENB pin is pulled down to ground, a logical ‘0’
means VIN voltage is lower than UVLO threshold, while a
logical ‘1’ means VIN voltage is higher than UVLO level.
An interrupt will be sent out when VIN rises above UVLO
level.
TAG_STS is a “target reached” indicate register for
moisture Detection Mode. When the device is in this mode,
it will monitor VIN voltage. Once VIN is higher than the
threshold level (set by register 0x09) during Detection
Mode, TAG_STS will be set to 1 and interrupt signal will be
triggered via INTB pin.
TMO_STS is a status register for “time−out” situation.
During Detection Mode, it will suggest if the device is in
“detection” period or “blank” period. When it is in
“detection” period, TMO_STS will be 0. When it is in
“blank” period, TMO_STS will be 1. Every time the status
is switched from “detection” period to “blank” period,
interrupt signal will be sent our via INTB pin. Figure x is a
reference timing diagram for that.
Figure 7. TMO_STS and Related Interrupt
www.onsemi.com
10
FPF2283CUCX
SW_STS is a status register for power switch. It indicates if the power FET is on or off. When the FET is in conducting
condition, SW_STS is 1. When the FET is in isolating condition, SW_STS is 0. Every time the power FET is turned on, interrupt
signal will be triggered.
Power Switch FLAG Register
Address: 03h, Bit [2:0]
Default Value: 3’b000
Type: Read / Clear
Bit Name
Bit #
Value
Description
Initialed by POR. Be 0 as long as VIN is lower than V
OV_FLG
2
0 (Default)
.
OVLO
1
Set and latched by FPF2283CUCX when ENB is logical LOW and VIN is higher than V
Initialed by POR. Be 0 as long as VOUT is high enough.
.
OVLO
HS_FLG
OT_FLG
1
0
0 (Default)
1
0 (Default)
1
Set and latched by FPF2283CUCX and kept until this byte been read.
Initialed by POR. Be 0 as long as the junction temperature is lower than T
.
SDN
Set and latched by FPF2283CUCX when the junction temperature is higher than T
.
SDN
OV_FLAG is a flag indicator for over voltage protection.
When the device is in Switch Mode, SW_ENB = 0, power
switch will be turned off and OV_FLG will be latched to 1
when VIN > V
. Interrupt will also be asserted in this
OVLO
case. V
is decided by the register byte 0x03 and
OVLO
external resistor ladder (Figure 1). The action of reading
0x02 will reset OV_FLG and INTB although they might be
triggered again if VIN is still under over voltage stress.
HS_FLG is a flag indicator for hard short circuit
protection. When the device is in Switch Mode, SW_ENB
= 0, power switch will be turned off and HS_FLG will be
latched to 1 and INTB will be asserted, when the VOUT
encounters hard−short to ground. The action of reading 0x02
will reset HS_FLG and de−asserted INTB. However, the
Figure 8. Timing for OVLO Trip Without
power switch will keep OFF for t . After t , the
HS_RST HS_RST
switch will be re−started again. If the short condition still
exists, the device will be turned off again.
OT_FLG is a flag indicator for over temperature
protection. When the device is in Switch Mode, SW_ENB
= 0, power switch will be turned off and OT_FLG will be
latched to 1 when the device junction temperature exceed
T
. The action of reading 0x02 will reset OT_FLG
SDN
although it might be triggered to 1 again if the temperature
is still high.
Figure 9. Timing for Power Switch Thermal
Shutdown
www.onsemi.com
11
FPF2283CUCX
Mask Register
Address: 04h, Bit [7:0]
Default Value: 8’h00
Type: Write / Read
Bit Name
Bit #
Value
Description
PON_MSK
7
6
5
4
0 (Default)
Initialed by POR or set by function defined.
Interrupt responding to PON_STS is normal.
2
1
Set by I C.
The interrupt INTB will not be triggered because of PON_STS.
TAG_MSK
TMO_MSK
SW_MSK
0 (Default)
Initialed by POR or set by function defined.
Interrupt responding to TAG_STS is normal.
2
1
Set by I C.
The interrupt INTB will not be triggered because of TAG_STS.
0 (Default)
Initialed by POR or set by function defined.
Interrupt responding to TMO_STS is normal.
2
1
0 (Default)
1
Set by I C.
The interrupt INTB will not be triggered because of TMO_STS.
Initialed by POR or set by function defined.
Interrupt responding to SW_STS is normal.
2
Set by I C.
The interrupt INTB will not be triggered because of SW_STS.
Reserved
OV_MSK
3
2
0 (Default)
0 (Default)
Do not use
Initialed by POR or set by function defined.
Interrupt responding to OV_FLG is normal.
2
1
Set by I C.
The interrupt INTB will not be triggered because of OV_FLG.
HS_MSK
OT_MSK
1
0
0 (Default)
Initialed by POR or set by function defined.
Interrupt responding to HS_FLG is normal.
2
1
0 (Default)
1
Set by I C.
The interrupt INTB will not be triggered because of HS_FLG.
Initialed by POR or set by function defined.
Interrupt responding to OT_FLG is normal.
2
Set by I C.
The interrupt INTB will not be triggered because of OT_FLG.
The mask registers will control the interrupt assert behavior. By default, the 0x04 is all 0. If one bit of it is written to 1, the
relevant STS bit or FLG bit will not trigger INTB when they flip to 1. For example, when SW_MSK=0, interrupt will be
asserted if SW_STS turns from 0 to 1. However, if SW_MSK=1, interrupt will not be asserted by this process.
www.onsemi.com
12
FPF2283CUCX
Register for OVP Internal Threshold
Address: 05h, Bit [1:0]
Default Value: 2’b00
Register for ISRC Current Value
Address: 06h, Bit [3:0]
Default Value: 4’b0000
Type: Read / Write
Type: Read / Write
Function: Define the center of rising trigger level of OVP,
see the description followed
Function: Define current source amplitude
ISRC [3:0]
Data
I
Value
SRC
OV [1:0]
Data
2’b00
2’b01
2’b10
2’b11
Internal OVP Threshold
4’b0000
4’b0001
4’b0010
4’b0011
4’b0100
4’b0101
4’b0110
4’b0111
4’b1000
4’b1001
4’b1010
4’b1011
4’b1100
4’b1101
4’b1110
4’b1111
0 mA
6.8 V
11.5 V
17.0 V
23.0 V
1 mA
2 mA
Define the
internal Over
Voltage Lockout
center value
3 mA
4 mA
5 mA
Register for OVP Internal Threshold Offset
Address: 05h, Bit [6:4]
10 mA
20 mA
50 mA
100 mA
200 mA
500 mA
1 mA
2 mA
5 mA
10 mA
Define Source
Current value
Default Value: 3’b011
Type: Read / Write
Function: Define the offset of OVP from center value, see
the description followed
RNG [6:4]
Data
Internal OVP offset
−600 mV
−400 mV
−200 mV
0 mV
3’b000
3’b001
3’b010
3’b011
3’b100
3’b101
3’b110
3’b111
Define the OVP
offset
2
The internal current source value can be set via I C. The
register 0x06 can decide it by the above table.
The current source is powered by VDD. It could be used
to set the measurement range. In the case that capacitance on
200 mV
400 mV
600 mV
800 mV
VIN is large, a large I
could be applied firstly. After the
SRC
voltage change becomes smoothly, smaller I
to save the standby consumption.
can be used
SRC
When OV_MODE = 0 or V
< 0.15 V, the OVLO level
ADJ
will be decided by external resistor divider (Equation 1).
When OV_MODE = 1, the OVLO level will be decided by
register 0x05. [OV1:OV0] will decide the OVP level center
value and RNG[6:4] will decide the offset value.
For example, when 0x06 = 8’h19 ([OV1:OV0] =2’b01,
RNG[6:4]=3’b001, OV_MODE=1), the OVP level of VIN
can be calculated as V
= 11.5 V − 0.4 V = 11.1 V.
OVLO
www.onsemi.com
13
FPF2283CUCX
Register for ISRC Pulse
Address: 07h, Bit [7:4]
Default Value: 4’b0000
Type: Read / Write
Register for ISRC Blank Time
Address: 07h, Bit [3:0]
Default Value: 4’b0000
Type: Read / Write
Function: Define t , see the description followed
Function: define t , see the description followed
BLNK
DET
TDET [3:0]
Data
I
Pulse Width
200 ms
400 ms
1 ms
TBLK [3:0]
Data
I
Apply Period
SRC
SRC
4’b0000
4’b0001
4’b0010
4’b0011
4’b0100
4’b0101
4’b0110
4’b0111
4’b1000
4’b1001
4’b1010
4’b1011
4’b1100
4’b1101
4’b1110
4’b1111
4’b0000
4’b0001
4’b0010
4’b0011
4’b0100
4’b0101
4’b0110
4’b0111
4’b1000
4’b1001
4’b1010
4’b1011
4’b1100
4’b1101
4’b1110
4’b1111
Single Pulse
10 ms
20 ms
50 ms
100 ms
200 ms
500 ms
1 s
2 ms
4 ms
10 ms
20 ms
40 ms
100 ms
200 ms
400 ms
1 s
Define pulse
Define Period
width t
of the
DET
t
of Detection
current source
PD
2 s
applied on VIN
3 s
6 s
12 s
2 s
30 s
4 s
60 s
10 s
120 s
300 s
Always ON
NOTE: It should be noticed, when 0x07 is set to 8’hF0 (conflict
as single pulse and always ON), always on mode will be
dominating.
The detection mode period will be decided by above table
and following diagram:
www.onsemi.com
14
FPF2283CUCX
Figure 10. Timing for Detection Period Setup
Register for Detection Target
Address: 09h, Bit [7:0]
Default Value: 8’b00
Type: Read / Write
Function: Define the threshold of moisture detection. This register can be written to a threshold value for 0 V to 2.04 V with
8 mV/step. During detection, once the voltage on VIN exceed the value set by 0x09, the interrupt will be asserted and register
TAG_STS (bit[6] of register 0x02) will be set to 1. By doing that, processor will know when the low resistance condition has
disappeared before proceed to the next action.
Figure 11. Timing for TAG_STS and Register 0x09 (TAG_DIR = 0)
www.onsemi.com
15
FPF2283CUCX
APPLICATIONS INFORMATION
Overview of I2C
transmitter releases the SDA line and the receiver sets the
SDA line to low (= acknowledge) level.
2
The I C bus supports bi−directional communications via
two signal lines: the SDA (data) line and SCL (clock) line.
A combination of these two signals is used to transmit and
receive communication start/stop signals, data signals,
acknowledge signals, and so on. Both the SCL and SDA
signals are held at high level whenever communications are
not being performed.
The starting and stopping of communications will be
controlled at the rising edge or falling edge of SDA while
SCL is at high level. During data transfers, data changes that
occur on the SDA line are performed while the SCL line is
at low level, and on the receiving side the data is captured
while the SCL line is at high level. In either case, the data is
transferred via the SCL line at a rate of one bit per clock
pulse.
After transmitting the ACK signal, if the Master remains
the receiver for transfer of the next byte, the SDA is released
at the falling edge of the clock corresponding to the 9 bit
of data on the SCL line. Data transfer resumes when the
Master becomes the transmitter.
When the Master is the receiver, if the Master does not
send an ACK signal in response to the last byte sent from the
slave, it indicates to the transmitter that data transfer has
ended. At that point, the transmitter continues to release the
SDA and awaits a STOP condition from the Master.
th
Starting and Stopping I2C
START condition: SDA level changes from high to low
while SCL is at high level
Slave Address
2
The I C bus device does not include a chip select pin such
STOP condition: SDA level changes from low to high
while SCL is at high level
as is found in ordinary logic devices. Instead of using a chip
select pin, slave addresses are allocated to each device and
the receiving device responds to communications only when
its slave address matches the slave address in the received
data.
Repeated START condition (RESTART condition)
All communications begin with transmitting the [START
condition] + [slave address (+ R/W specification)]. The
receiving device responds to this communication only when
the specified slave address it has received matches its own
slave address. Slave addresses have a fixed length of 7−bits
(7’b1101100). See table for the details. An R/W bit is added
to each 7−bits slave address during 8−bits transfers.
Data Transfer and Acknowledge Responses during I2C
Communication
Data transfers are performed in 8−bit (1 byte) units once
the START condition has occurred. There is no limit on the
amount (bytes) of data that are transferred between the
START condition and STOP condition. The address auto
increment function operates during both write and read
operations.
Updating of data on the transmitter (transmitting side)’s
SDA line is performed while the SCL line is at low level. The
receiver (receiving side) captures data while the SCL line is
at high level.
Operation Transfer
data
Slave Address
R/W bit
Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Read
Write
D9h
D8h
1
1
0
1
1
0
0
1 (=Read)
0 (=Write)
Input Decoupling (Cin)
A ceramic or tantalum at least 0.1 mF capacitor is
recommended and should be connected close to the
FPF2283CUCX package. Higher capacitance and lower
ESR will improve the overall line and load transient
response.
Output Decoupling (Cout
)
The FPF2283CUCX is a stable component and does not
require a minimum Equivalent Series Resistance (ESR) for
the output capacitor. The minimum output decoupling value
is 0.1 mF and can be augmented to fulfill stringent load
transient requirements.
When transferring data, the receiver generates a
confirmation response (ACK signal, low active) each time
an 8−bit data segment is received. If there is no ACK signal
from the receiver, it indicates that normal communication
has not been established. (This does not include instances
where the master device intentionally does not generate an
ACK signal.)
Enable Operation
The enable pin ENB will turn the device on or off without
I C communication. The threshold limits are covered in the
Immediately after the falling edge of the clock pulse
2
th
corresponding to the 8 bit of data on the SCL line, the
www.onsemi.com
16
FPF2283CUCX
electrical characteristics table in this data sheet. The
maximum dissipation the FPF2283CUCX can handle is
given by:
turn−on/turn−off transient voltage being supplied to the
enable pin should exceed a slew rate of 10 mV/ms to ensure
correct operation. If the enable function is not to be used then
the pin should be connected to Ground.
ƪT
ƫ
J(MAX) * TA
PD(MAX)
+
(eq. 3)
RqJA
Since T is not recommended to exceed 125°C, then the
J
2
Thermal Considerations
FPF2283CUCX soldered on 645 mm , 1 oz copper area, the
As power in the FPF2283CUCX increases, it might
become necessary to provide some thermal relief. The
maximum power dissipation supported by the device is
dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. When the FPF2283CUCX has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power applications. The
power dissipated by the FPF2283CUCX can be calculated
from the following equations:
P
D [ Vin @ IQ@Iout ) Iout 2 @ ron
ǒ Ǔ
(eq. 4)
Hints
V and V printed circuit board traces should be as wide
in
out
as possible. Place external components, especially the input
capacitor and TVS, as close as possible to the
FPF2283CUCX, and make traces as short as possible.
www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP20 2.2x1.8x0.574
CASE 567UT
ISSUE O
DATE 07 JUL 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON66166G
WLCSP20 2.2x1.8x0.574
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
©2020 ICPDF网 联系我们和版权申明