FOD8333R2 [ONSEMI]
输入 LED 驱动、2.5 A 输出电流、带去饱和检测的 IGBT 驱动光电耦合器、隔离故障感测、有源米勒箝位，及自动故障复位;
| 型号： | FOD8333R2 |
| 厂家： | 
ONSEMI |
| 描述： | 输入 LED 驱动、2.5 A 输出电流、带去饱和检测的 IGBT 驱动光电耦合器、隔离故障感测、有源米勒箝位，及自动故障复位 驱动 双极性晶体管 光电 |
| 文件： | 总34页 (文件大小：1273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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May 2014
FOD8333
Input LED Drive, 2.5 A Output Current, IGBT Drive
Optocoupler with Desaturation Detection, Isolated Fault
Sensing, Active Miller Clamp, and Automatic Fault Reset
Features
Description
■ Input LED Drive Facilitates Receiving Digitally
The FOD8333 is an advanced 2.5 A output current IGBT
drive optocoupler capable of driving medium-power
IGBTs with ratings up to 1,200 V and 150 A. It is suited
for fast-switching driving of power IGBTs and
MOSFETs in motor-control inverter applications and
high-performance power systems. The FOD8333 offers
protection features necessary for preventing fault condi-
tions that lead to destructive thermal runaway of IGBTs.
Encoded Signals from PWM Output
■ Optically Isolated Fault-Sensing Feedback
■ Active Miller Clamp to Shut Off IGBT During High
dv/dt without Negative Supply Voltage
■ High Noise Immunity Characterized by
Common Mode Rejection – 35 kV/µs Minimum,
V
= 1500 V
CM
PEAK
®
The device utilizes Fairchild’s proprietary Optoplanar
■ 2.5 A Peak Output Current Driving Capability for
coplanar packaging technology and optimized IC design
to achieve reliable high isolation and high noise immunity,
characterized by high common-mode rejection and power
supply rejection specifications. The device is housed in a
wide-body, 16-pin, small-outline, plastic package.
Medium Power IGBT
– P-Channel MOSFETs at Output Stage Enable
Output Voltage Swing Close to Supply Rail
(Rail-to-Rail Output)
– Wide Supply Voltage Range: 15 V to 30 V
■ Integrated IGBT Protection
– Desaturation Detection
The gate-driver channel consists of an aluminum gallium
arsenide (AlGaAs) light-emitting diode (LED) optically
coupled to an integrated high-speed driver circuit with a
– “Soft” IGBT Turn-Off
low-R
MOSFET output stage. The fault-sense
DS(ON)
channel consists of an AlGaAs LED optically coupled to
an integrated high-speed feedback circuit for fault
sensing.
– Automatic Fault Reset after Fixed Mute Time,
Typically 33 µs
– Under-Voltage Lockout (UVLO) with Hysteresis
■ Fast Switching Speed Over Full Operating
Related Resources
Temperature Range
■ FOD8316—2.5 A Output Current, IGBT Drive
– 250 ns Maximum Propagation Delay
– 100 ns Maximum Pulse Width Distortion
■ Extended Industrial Temperate Range:
Optocoupler with Desaturation, Isolated Fault Sensing
■ FOD8318—2.5 A Output Current, IGBT Drive
Optocoupler with Active Miller Clamp, Desaturation
Detection, and Isolated Fault Sensing
– –40°C to 100°C
■ Safety and Regulatory Approvals
■ FOD8332—Input LED Drive, 2.5 A Output Current,
IGBT Drive Optocoupler with Desaturation Detection,
Isolated Fault Sensing, and Active Miller Clamp
– UL1577, 4,243 V
for 1 Minute
RMS
– DIN-EN/IEC60747-5-5:
1,414 V
Working Insulation Voltage Rating
PEAK
■ AN-3009—Standard Gate-Driver Optocouplers
8,000 V
Transient Isolation Voltage Rating
PEAK
■ 8 mm Creepage and Clearance Distances
Applications
■ AC and Brushless DC Motor Drive
■ Industrial Inverter
■ Uninterruptible Power Supply
■ Induction Heating
■ Isolated IGBT/Power MOSFET Gate Drive
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
Truth Table
(1)
UVLO (V – V )
V
O
LED
DESAT Detected?
FAULT
DD
E
X
Active
Not Active
X
X
Yes
X
HIGH
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
On
Off
On
Not Active
No
Note:
1. FAULT pin is connected to a pull-up resistor.
Pin Configuration
GND
VCC
1
2
3
4
5
6
7
8
16 VE
15 VLED2+
FAULT
GND
14 DESAT
13 VDD
VLED1–
VLED1+
VLED1+
VLED1–
12 VSS
11 VO
10 VCLAMP
9
VSS
Figure 1. Pin Configuration
Pin Definitions
Pin #
Name
Description
1
2
GND
Ground for Fault-Sense Optocoupler
V
Positive Supply Voltage (3 V to 15 V) for Fault Sense Optocoupler
Fault-Sense Output
CC
3
FAULT
GND
4
Ground for Fault-Sense Optocoupler
LED1 Cathode
5
V
V
V
V
V
V
V
V
V
LED1-
LED1+
LED1+
LED1-
SS
6
LED1 Anode
7
LED1 Anode
8
LED1 Cathode
9
Negative Output Supply Voltage
Clamp Supply Voltage
10
11
12
13
14
15
16
CLAMP
O
Gate-Drive Output Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Desaturation Voltage Input
LED2 Anode (Do not connect. Leave floating.)
Output Supply Voltage/IGBT Emitter
SS
DD
DESAT
V
V
LED2+
E
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
2
Block Diagram
16
15
14
13
1
VE
GND
LED2
2
VCC
VLED2+
3
DESAT
DESAT
FAULT
UVLO
SHIELD
4
GND
VDD
FAULT IC
5
6
7
12
11
10
9
VLED1-
VLED1+
VLED1+
VLED1-
VSS
VO
VCLAMP
MILLER
CLAMP
8
SHIELD
VSS
OUTPUT IC
Figure 2. Functional Block Diagram
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
3
Safety and Insulation Ratings
As per DIN EN/IEC 60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings must be ensured by means of protective circuits.
Symbol
Parameter
Min.
Typ.
Max. Unit
Installation Classifications per DIN VDE 0110/1.89 Table 1
Rated Mains Voltage < 150 V
Rated Mains Voltage < 300 V
Rated Mains Voltage < 450 V
Rated Mains Voltage < 600 V
I–IV
I–IV
RMS
RMS
RMS
RMS
I–IV
I–IV
Rated Mains Voltage < 1000 V
Climatic Classification
I–III
RMS
40/100/21
2
Pollution Degree (DIN VDE 0110/1.89)
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
175
V
Input-to-Output Test Voltage, Method b, V
x 1.875 = V
,
2651
V
V
PR
IORM
PR
peak
100% Production Test with t = 1 s, Partial Discharge < 5 pC
m
Input-to-Output Test Voltage, Method a, V
x 1.6 = V
,
2262
IORM
PR
peak
Type and Sample Test with t = 10 s, Partial Discharge < 5 pC
m
V
Maximum Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
1414
8000
8.0
V
V
IORM
peak
V
IOTM
peak
mm
mm
mm
External Clearance
8.0
Insulation Thickness
0.5
Safety Limit Values – Maximum Values in Failure;
Case Temperature
T
150
100
600
°C
Case
Safety Limit Values – Maximum Values in Failure;
Input Power
P
mW
S,INPUT
Safety Limit Values – Maximum Values in Failure;
Output Power
P
mW
S,OUTPUT
9
R
Insulation Resistance at T , V = 500 V
10
Ω
IO
S
IO
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T = 25ºC unless otherwise specified.
A
Symbol
Parameter
Storage Temperature
Value
Units
T
-40 to +125
-40 to +100
-40 to +125
260 for 10 s
ºC
ºC
ºC
ºC
STG
T
Operating Temperature
Junction Temperature
OPR
T
J
T
Lead Solder Temperature
SOL
(not certified for wave immersion)
Refer to reflow temperature profile on page 31
(2)(3)
PD
Input Power Dissipation
45
mW
mW
I
(3)(4)
PD
Output Power Dissipation
600
O
Gate Drive Channel
I
Average Input Current
25
mA
A
F(AVG)
I
Peak Transient Forward Current
(Pulse Width < 1 µs)
1.0
F(PEAK)
(5)
I
Peak Output High Current
3.0
3.0
A
A
OH(PEAK)
(5)
I
Peak Output Low Current
OL(PEAK)
V
Reverse Input Voltage
5.0
V
R
(6)
V – V
Negative Output Supply Voltage
Positive Output Supply Voltage
Gate Drive Output Voltage
Output Supply Voltage
-0.5 to 15
V
E
SS
V
– VE
-0.5 to 35 – (V – V
)
V
DD
O(PEAK)
E
SS
V
– V
-0.5 to 35
-0.5 to 35
V
SS
V
– V
V
DD
SS
V
Desaturation Voltage
V to V + 25
V
DESAT
E
E
I
Desaturation Current
60
mA
V
DESAT
V
– V
Active Miller Clamping Voltage
-0.5 to 35
1.7
CLAMP
SS
I
Peaking Clamping Sinking Current
Input Signal Rise and Fall Time
A
CLAMP
t
, t
500
ns
R(IN) F(IN)
Fault Sense Channel
V
Positive Input Supply Voltage
FAULT Output Voltage
-0.5 to 20
-0.5 to 20
16.0
V
V
CC
V
FAULT
FAULT
I
FAULT Output Current
mA
Notes:
2. No derating required across temperature range.
3. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected
to conditions outside these ratings.
4. Derate linearly above 25°C, free air temperature at a rate of 6.2 mW/°C.
5. Maximum pulse width = 10 µs.
6. This negative output supply voltage is optional. It is only needed when negative gate drive is implemented.
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
5
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
T
Ambient Operating Temperature
Input Current (ON)
-40
7
+100
16
ºC
mA
V
A
I
F(ON)
V
Input Voltage (OFF)
-3.6
3
0.8
15
F(OFF)
V
Supply Voltage
V
CC
V
– V
Total Output Supply Voltage
15
15
0
30
V
DD
SS
(7)
V
– V
Positive Output Supply Voltage
Negative Output Supply Voltage
Input Pulse Width
30 – (V – V
)
V
DD
E
E
SS
V – V
15
V
E
SS
t
500
ns
PW
Note:
7. During power up or down, ensure that both the input and output supply voltages reach the proper recommended
operating voltages to avoid any momentary instability at the output state.
Isolation Characteristics
Apply over all recommended conditions; typical value is measured at T = 25ºC.
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
V
Input-Output Isolation T = 25°C, Relative Humidity < 50%,
4,243
V
RMS
ISO
A
Voltage
t = 1.0 minute, I ≤ 10 µA, 50 Hz
I-O
(8)(9)(10)
(8)
11
R
C
Isolation Resistance
Isolation Capacitance
V
V
= 500 V
10
ISO
I-O
(8)
= 0 V, Frequency = 1.0 MHz
1
pF
ISO
I-O
Notes:
8. Device is considered a two-terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
9. 4,243 V for 1-minute duration is equivalent to 5,091 V for 1-second duration.
RMS
RMS
10. The input-output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an
input-output continuous voltage rating. For the continuous working voltage rating, refer to equipment-level safety
specification or DIN EN/IEC 60747-5-5 Safety and Insulation Ratings Table on page 4.
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
6
Electrical Characteristics
Apply over all recommended conditions; typical value is measured at V = 5 V, V – V = 30 V, V – V = 0 V, and
CC
DD
SS
E
SS
T = 25°C; unless otherwise specified.
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units Figure
Gate Drive Channel
V
Input Forward Voltage
I = 10 mA
1.10
5
1.45
-1.5
1.80
V
5
F
F
Δ(V /T )
Temperature Coefficient
of Forward Voltage
mV/ºC
F
A
BV
Input Reverse
I
= 10 µA
V
R
R
Breakdown Voltage
C
Input Capacitance
f = 1 MHz, V = 0 V
60
pF
IN
F
I
Threshold Input Current,
Low to High
I
= 0 mA, V > 5 V
2.5
7.0
mA
30
31
FLH
O
O
V
Threshold Input Voltage,
High to Low
I
= 0 mA, V < 5 V
0.8
-1.0
-2.5
V
A
A
FHL
O
O
I
High Level Output
Current
V
= V – 3 V,
-2.5
6, 10,
32
OH
O
DD
I = 10 mA
F
V
= V – 6 V,
O
DD
(11)
I = 10 mA
F
I
Low Level Output
Current
V
= V + 3 V, I = 0 mA
1
3
A
A
7, 11,
33
OL
O
SS
F
V
= V + 6 V,
2.5
O
SS
(12)
I = 0 mA
F
I
Low Level Output
Current During Fault
Condition
V
– V = 14 V
70
125
170
mA
34
OLF
O
SS
V
High Level Output
Voltage
I = 10 mA,
V
– 1.0
V – 0.2
DD
V
8, 10,
35
OH
F
DD
(13)(14)(15)
I
= –100 mA
O
V
Low Level Output Voltage I = 0 mA, I = 100 mA
0.1
2.5
0.5
5.0
5.0
V
9, 11,
36
OL
F
O
I
High Level Supply
Current
V
= Open, I = 0 mA
mA
mA
mA
mA
mA
mA
12, 13,
37
DDH
O
O
O
I
Low Level Supply
Current
V
= Open, I = 0 mA
2.5
12, 13,
38
DDL
O
I
V
Low Level Supply
E
-0.8
-0.5
-0.25
-0.25
40
38
EL
Current
I
V
High Level Supply
-0.50
-0.33
10
37
EH
E
Current
(15)(16)
I
Blanking Capacitor
Charge Current
V
V
= 2 V
= 7 V
-0.13
14, 39
39
CHG
DESAT
DESAT
I
Blanking Capacitor
Discharge Current
DSCHG
V
Under-Voltage Lockout
Threshold
I = 10 mA, V > 5 V
10.8
9.8
11.7
10.7
1.0
12.7
11.7
V
V
V
40
UVLO+
F
O
(14)
V
I = 10 mA, V < 5 V
UVLO-
F
O
UVLO
Under-Voltage Lockout
Threshold Hysteresis
HYS
(14)
V
DESAT Threshold
V
– V > V
6.0
6.5
2.0
7.2
V
V
15, 39
41
DESAT
DD
E
ULVO–
V
Clamping Threshold
Voltage
CLAMP_THRES
I
Clamp Low Level Sinking
Current
V
= V + 2.5 V
0.35
1.10
A
16, 42
CLAMPL
O
SS
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
7
Electrical Characteristics (Continued)
Apply over all recommended conditions; typical value is measured at V = 5 V, V – V = 30 V, V – V = 0 V, and
CC
DD
SS
E
SS
T = 25°C; unless otherwise specified.
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units Figure
Fault Feedback Channel
I
FAULT High Level Supply
Current
I
V
V
= 0 mA,
F2
0.0004
150
2
µA
µA
43
44
CCH
= Open,
FAULT
= 15 V
CC
I
FAULT Low Level Supply
Current
I
V
V
= 16 mA,
F2
200
CCL
= Open,
FAULT
= 15V
CC
I
FAULT Logic High Output
Current
V
= V = 5.5 V
0.02
0.50
µA
45
FAULTH
FAULT
CC
I
FAULT Logic Low Output
Current
V
V
= 0.4 V,
= 5.5 V
1.1
mA
17, 46
FAULTL
FAULT
CC
Notes:
11. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%.
12. Minimum pulse width = 4.99 ms, minimum duty cycle = 99.8%.
13. V is measured with the DC load current in this testing (maximum pulse width = 1 ms, maximum duty
OH
cycle = 20%). When driving capacitive loads, V approaches V as I approaches zero units.
OH
DD
OH
14. Positive output supply voltage (V – V ) should be at least 15 V to ensure adequate margin in excess of the
DD
E
maximum under-voltage lockout threshold, V
, of 12.7 V.
UVLO+
15. When V – V > V
and the output state V is allowed to go HIGH, the DESAT-detection feature is active and
O
DD
E
UVLO
provides the primary source of IGBT protection. UVLO is needed to ensure DESAT detection is functional.
16. The blanking time, t
, is adjustable by an external capacitor (C
), where t
= C
× (V
/ I
).
BLANK
BLANK
BLANK
BLANK
DESAT CHG
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
8
Switching Characteristics
Apply over all recommended conditions; typical value is measured at V = 5 V, V – V = 30 V, V – V = 0 V, and
CC
DD
SS
E
SS
T = 25°C; unless otherwise specified.
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units Figure
t
Propagation Delay to Logic
Low Output
Rg = 10 Ω, Cg =10 nF,
f = 10 kHz,
Duty Cycle = 50%,
100
135
150
15
250
ns
ns
ns
18, 19,
20, 21,
47
PHL
(18)
t
Propagation Delay to Logic
100
250
100
PLH
I = 10 mA,
(19)
F
High Output
(17)
V
– V = 30 V
DD
SS
PWD
Pulse Width Distortion,
47
47
(20)
| t
– t
|
PLH
PHL
PDD Skew Propagation Delay Difference
-150
150
ns
Between Any Two Parts or
(21)
Channels, ( t
– t
)
PHL
PLH
t
Output Rise Time
(10% to 90%)
50
50
ns
ns
µs
µs
µs
µs
R
t
Output Fall Time
(90% to 10%)
F
t
DESAT Sense to DESAT Low Rg = 10 Ω, Cg = 10 nF,
0.25
0.45
2.8
DESAT(LOW)
(24)
Propagation Delay
V
– V = 30 V
DD SS
(C
= 100pF,
DESAT
t
DESAT Sense to 90% V
0.70
4.0
1.5
45
22, 48
DESAT(90%)
DESAT(10%)
O
R = 4.7 kΩ, V = 5.5 V)
(22)
F
CC
Delay
t
DESAT Sense to 10% V
23, 24,
25, 48
O
(22)
Delay
t
DESAT Sense to Low Level
0.5
26, 48
DESAT(FAULT)
(23)
FAULT Signal Delay
t
DESAT Input Mute
20
33
4.0
4.0
2
µs
µs
µs
µs
48
49
DESAT(MUTE)
(25)
t
UVLO Turn-On Delay
V
= 20 V in 1.0 ms
UVLO ON
DD
Ramp
(26)
t
UVLO Turn-Off Delay
UVLO OFF
(27)
t
Time-to-Good Power
V
= 0 to 30 V in 10 µs
28, 29,
49
GP
DD
Ramp
| CM
|
Common Mode Transient
Immunity at Output High
T = 25˚C, V = 5 V,
35
35
50
kV/µs
51, 52
H
A
CC
V
= 25 V, V = Ground,
DD
SS
C = 15 pF, R = 4.7 kΩ,
F
F
(28)
V
= 1500 V
CM
PEAK
| CM |
Common Mode Transient
Immunity at Output Low
T = 25˚C, V = 5 V,
A CC
50
kV/µs
50, 53
L
V
= 25 V, V = Ground,
DD
SS
C = 15 pF, R = 4.7 kΩ,
F
F
(29)
V
= 1500 V
CM
PEAK
Notes:
17. This load condition approximates the gate load of a 1200 V / 150 A IGBT.
18. Propagation delay t is measured from the 50% level on the falling edge of the input pulse to the 50% level of the
PHL
falling edge of the V signal.
O
19. Propagation delay t
is measured from the 50% level on the rising edge of the input pulse to the 50% level of the
PLH
rising edge of the V signal.
O
20. PWD is defined as | t
– t
| for any given device.
PHL
PLH
21. The difference between t
and t
between any two parts under same operating conditions with equal loads.
PHL
PLH
22. The length of time the DESAT threshold must be exceeded before V begins to go LOW. This is supply voltage
O
dependent.
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
9
23. The time from DESAT threshold is exceeded until the FAULT output goes LOW.
24. The length of time the DESAT threshold must be exceeded before V begins to go LOW and the FAULT output
O
begins to go LOW.
25. The UVLO turn-on delay, t
, is measured from the V
threshold level of the rising edge of the output
UVLO ON
UVLO+
supply voltage (V ) to the 5 V level of the rising edge of the V signal.
DD
O
26. The UVLO turn-off delay, t
, is measured from the V
threshold level of the falling edge of the output
UVLO OFF
UVLO–
supply voltage (V ) to the 5 V level of the falling edge of the V signal.
DD
O
27. The time to good power, t , is measured from the V
threshold level of the rising edge of the output supply
GP
UVLO+
voltage (V ) to the 5 V level of the rising edge of the V signal.
DD
O
28. Common-mode transient immunity at output HIGH state is the maximum tolerable negative dVCM/dt on the trailing
edge of the common-mode pulse, V , to assure the output remains in HIGH state (i.e., V > 15 V or V > 2 V).
CM
O
FAULT
29. Common-mode transient immunity at output LOW state is the maximum positive tolerable dVCM/dt on the leading
edge of the common-mode pulse, V , to ensure the output remains in LOW state (i.e., V < 1.0 V or
CM
O
V
< 0.8 V).
FAULT
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
10
Timing Diagrams
I
F
t
t
F
R
90%
50%
10%
V
O
t
t
PHL
PLH
Figure 3. t
, t
, t , and t Timing Diagram
PLH PHL
R
F
t
DESAT(LOW)
I
F
6.5V
50%
V
DESAT
t
DESAT(10%)
t
BLANK
90%
V
O
10%
t
DESAT(90%)
Automatic Reset
after Mute Time
50%
50%
FAULT
t
DESAT(FAULT)
t
DESAT(MUTE)
Figure 4. Definitions for DESAT, V and FAULT Timing Waveforms
O
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
11
Typical Performance Characteristics
100.00
7
6
5
4
3
2
10.00
1.00
V
V
= V
= V
– 6 V
OH
DD
100°C
25°C
1.2
-40°C
– 3 V
OH
DD
0.10
I
= 10 mA
LED1+
V
– V = 30 V
SS
DD
1
-40
0.01
0.8
1.0
1.4
1.6
1.8
-20
0
20
40
60
80
100
VF – INPUT FORWARD VOLTAGE (V)
TA – TEMPERATURE (°C)
Figure 5. Input Forward Current (I )
Figure 6. High Level Output Current (I
)
OH
F
vs. Voltage (V )
vs.Temperature
F
7
6
5
4
3
2
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
V
= V + 6 V
SS
OL
V
= V + 3 V
SS
OL
I
V
= 10 mA
LED1+
DD
I
V
= 0 A
– V = 30 V
SS
LED1+
DD
– V = 30 V
SS
I
= -100 mA
OH
1
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C)
Figure 7. Low Level Output Current (I
vs.Temperature
)
Figure 8. High Level Output Voltage (V
V
)
OL
OH – DD
vs.Temperature
30.0
0.20
0.15
0.10
0.05
0
29.5
T
A
= -40°C
29.0
25°C
100°C
28.5
I
V
I
= 0 A
SS
= 100 mA
LED1+
– V = 30 V
OL
I
= 10 mA
LED1+
DD
V
– V = 30 V
SS
DD
28.0
0
0.2
0.4
0.6
0.8
1.0
-40
-20
0
20
40
60
80
100
IOH – HIGH LEVEL OUTPUT CURRENT (A)
TA – TEMPERATURE (°C)
Figure 9. Low Level Output Voltage (V
vs.Temperature
)
OL
Figure 10. High Level Output Voltage (V
)
OH
vs. High Level Output Current (I
)
OH
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
12
Typical Performance Characteristics (Continued)
4
3
2
1
0
3.0
2.8
2.6
2.4
2.2
2.0
I
V
= 0 A
– V = 30 V
SS
LED1+
DD
25°C
I
DDL
T
= 100°C
A
-40°C
I
DDH
I
V
V
= 0 A (I
DDL
) / 10 mA (I
)
LED1+
DD
O
DDH
– V = 30 V
SS
= Open
-40
-20
0
20
40
60
80
100
0
0.5
1.0
1.5
2.0
2.5
TA – TEMPERATURE (°C)
IOL – LOW LEVEL OUTPUT CURRENT (A)
Figure 12. Output Supply Current (I
vs.Temperature
)
DD
Figure 11. Low Level Output Voltage (V ) vs.
OL
Low Level Output Current (I
)
OL
3.0
2.5
2.0
1.5
-0.15
-0.20
-0.25
-0.30
I
DDL
I
DDH
I
V
V
= 0 A (I
) / 10 mA (I )
DDH
LED1+
DDL
I
V
V
= 10 mA
LED1+
DD
– V = 30 V
DD
= Open
SS
– V = 30 V
SS
O
= 2V
-20
DESAT
15
20
25
30
-40
0
20
40
60
80
100
VDD – OUTPUT SUPPLY VOLTAGE (V)
TA – TEMPERATURE (°C)
Figure 13. Output Supply Current (I
)
DD
Figure 14. Blanking Capacitor Charge
vs. Voltage (V
)
DD
Current (I
) vs.Temperature
CHG
7.00
6.75
6.50
6.25
6.00
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
V
V
= 0 mA
LED1+
DD
I
V
= 10 mA
– V = 30 V
SS
– V = 30 V
LED1+
DD
SS
= V + 2.5V
SS
CLAMP
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (C)
TA – TEMPERATURE (°C)
Figure 15. DESAT Threshold (V
vs.Temperature
)
Figure 16. Clamp Low Level Sinking
Current (I ) vs.Temperature
DESAT
CLAMPL
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
13
Typical Performance Characteristics (Continued)
250
10
8
V
= 5.5 V
= 10 mA
CC
I
LED2+
100°C
25°C
200
150
100
50
t
t
PLH
6
PHL
4
-40°C
I
= 10 mA
LED1+
f = 10 kHz 50% Duty Cycle
– V = 30 V
2
V
DD
SS
R
= 10 Ω, C = 10 nF
g
g
0
0
-40
-20
0
20
40
60
80
100
0
1
2
3
4
5
30
50
V
– FAULT LOGIC LOW OUTPUT VOLTAGE (V)
TA – TEMPERATURE (°C)
FAULTL
Figure 18. Propagation Delay (t )
Figure 17. FAULT Logic Low Output
Current (I ) vs. Voltage (V
P
vs.Temperature
)
FAULTL
FAULTL
250
200
150
100
50
250
200
150
100
50
t
t
PLH
PLH
t
t
PHL
PHL
I
= 10 mA
LED1+
f = 10 kHz 50% Duty Cycle
V
C
I
= 10 mA
LED1+
f = 10 kHz 50% Duty Cycle
– V = 30 V
DD
g
SS
= 10 nF
R
= 10 Ω, C = 10 nF
g
g
0
0
15
20
25
0
10
20
30
40
50
VDD – SUPPLY VOLTAGE (V)
Rg – LOAD RESISTANCE (Ω)
Figure 19. Propagation Delay (t )
Figure 20. Propagation Delay (t )
P
P
vs. Supply Voltage (V
)
vs. Load Resistance (R )
DD
g
1.0
0.8
0.6
0.4
0.2
0.0
250
200
150
100
50
t
PLH
t
PHL
V
V
– V = 30 V
SS
DD
– V = 15 V
SS
DD
I
= 10 mA
f = 10 kHz 50% Duty Cycle
LED1+
V
– V = 15 V / 30 V
SS
= 10 mA
DD
V
R
– V = 30 V
DD
g
SS
I
LED1+
= 10 Ω
R
= 10 Ω, C = 10 nF
g
g
0
-40
-20
0
20
40
60
80
100
0
10
20
30
40
TA – TEMPERATURE (°C)
Cg – LOAD CAPACITANCE (nF)
Figure 21. Propagation Delay (t )
Figure 22. DESAT Sense to 90% V
P
O
vs. Load Capacitance (C )
Delay (t ) vs.Temperature
DESAT(90%)
g
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
14
Typical Performance Characteristics (Continued)
5
4
3
2
1
0
5
4
3
2
1
0
V
V
– V = 30 V
SS
DD
V
– V = 30 V
SS
DD
– V = 15 V
SS
DD
V
– V = 15 V
SS
DD
V
– V = 15 V / 30 V
SS
V
– V = 15 V / 30 V
SS
DD
DD
I
= 10 mA
I
= 10 mA
LED1+
LED1+
R
= 10 Ω, C = 10 nF
C = 10 nF
g
g
g
-40
-20
0
20
40
60
80
100
10
20
30
40
50
Rg – LOAD RESISTANCE (Ω)
TA – TEMPERATURE (°C)
Figure 23. DESAT Sense to 10% V
Figure 24. DESAT Sense to 10% V
O
O
Delay (t ) vs.Temperature
DESAT(10%)
Delay (t ) vs. Load Resistance (R )
DESAT(10%) g
15
10
5
0.55
V
– V = 30 V
SS
DD
V
V
= 5.5 V
= 3.3 V
V
– V = 15 V / 30 V
= 10 mA
= 10 Ω
CC
CC
DD
SS
I
LED1+
R
g
0.50
0.45
0.40
0.35
0.30
0.25
100°C
100°C
V
V
– V = 30 V
DD
SS
25°C
-40°C
25°C
– V = 15 V
SS
-40°C
DD
0
4
6
8
10
0
10
20
30
40
50
R F – FAULT LOAD RESISTANCE (kΩ)
Cg – LOAD CAPACITANCE (nF)
Figure 26. DESAT Sense to Low Level Fault Signal
Figure 25. DESAT Sense to 10% V
O
Delay (t
) vs. Fault Load Resistance (R )
Delay (t ) vs. Load Capacitance (C )
DESAT(10%)
DESAT(FAULT)
F
g
50
5
V
– V = 15 V / 30 V
SS
DD
V
– V = 30 V
SS
= 10 mA
DD
I
R
= 10 mA
LED1+
g
I
LED1+
= 10 Ω, C = 10 nF
g
40
30
20
10
0
4
3
2
1
0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C)
Figure 27. DESAT Input Mute (t
vs.Temperature
)
DESAT(MUTE)
Figure 28.Time-to-Good Power (t
)
GP
vs.Temperature
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
15
Typical Performance Characteristics (Continued)
5
I
T
= 10 mA
LED1+
= 25°C
A
4
3
2
1
0
15
20
25
30
VDD – OUTPUT SUPPLY VOLTAGE (V)
Figure 29.Time-to-Good Power (t ) vs. Output Supply Voltage (V
)
DD
GP
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
16
Test Circuits
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VCC
VLED2+
DESAT
VDD
0.1µF
0.1µF
FAULT
GND
0.1µF
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
30V
V
O
+
–
VO
VCLAMP
VSS
10mA
0A
Figure 30.Threshold Input Current Low-to-High (I
) Test Circuit
FLH
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
VCC
0.1µF
FAULT
GND
0.1µF
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
VSS
E
30V
V
O
+
–
0.1µF
VO
VCLAMP
VSS
2V
0V
+
–
Figure 31.Threshold Input Voltage High-to-Low (V
) Test Circuit
FHL
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
VCC
0.1µF
FAULT
GND
0.1µF
+
–
V
O
0.1µF
47µF
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
30V
+
–
VO
0.1µF 47µF
10mA
I
OH
VCLAMP
VSS
Period = 5ms
PW = 10μs
+
–
V
IN
R
M
Figure 32. High Level Output Current (I ) Test Circuit
OH
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
17
Test Circuits (Continued)
FOD8333
1
16
15
14
13
12
11
10
9
GND
VE
2
3
4
5
6
7
8
VCC
VLED2+
DESAT
VDD
0.1µF
FAULT
GND
0.1µF
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
I
OL
30V
+
–
VO
0.1µF 47µF
10mA
V
O
+
–
VCLAMP
VSS
0.1µF
47µF
Period = 5ms
PW = 4.99ms
+
–
V
IN
R
M
Figure 33. Low Level Output Current (I ) Test Circuit
OL
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
100pF
VCC
4.7kΩ
V
CC
0.1µF
0.1µF
+
–
V
DESAT
FAULT
GND
V
FAULT
0.1µF
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
30V
I
OLF
V
O
+
–
VO
0.1µF
10Ω
VCLAMP
VSS
10nF
10mA
V
IN
R
M
Figure 34. Low Level Output Current During Fault Condition (I
) Test Circuit
OLF
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
VCC
0.1µF
FAULT
GND
0.1µF
+
–
100mA
VLED1–
VLED1+
VLED1+
VLED1–
V
VSS
E
30V
V
OH
+
–
0.1µF
VO
VCLAMP
VSS
10mA
Figure 35. High Level Output Voltage (V ) Test Circuit
OH
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
18
Test Circuits (Continued)
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VCC
VLED2+
DESAT
VDD
0.1µF
0.1µF
FAULT
GND
0.1µF
+
–
30V
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
+
–
V
OL
VO
100mA
VCLAMP
VSS
Figure 36. Low Level Output Voltage (V ) Test Circuit
OL
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
I
EH
VCC
0.1µF
0.1µF
FAULT
GND
0.1µF
I
+
–
DDH
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
30V
+
–
VO
VCLAMP
VSS
10mA
Figure 37. High Level Supply Current (I
), V High Level Supply Current (I ) Test Circuit
DDH
E
EH
FOD8333
1
16
15
14
13
12
11
10
9
GND
VE
I
EL
2
VCC
VLED2+
0.1µF
0.1µF
3
4
5
6
7
8
FAULT
GND
DESAT
VDD
0.1µF
I
+
–
DDL
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
30V
+
–
VO
VCLAMP
VSS
Figure 38. Low Level Supply Current (I
), V Low Level Supply Current (I ) Test Circuit
E EL
DDL
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
19
Test Circuits (Continued)
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
–
+
8V
VCC
VLED2+
DESAT
VDD
0V
V
CC
4.7kΩ
0.1µF
0.1µF
+
–
V
DESAT
FAULT
GND
I
I
CHG
0.1µF
DSCHG
0.1µF
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
30V
+
–
VO
VCLAMP
VSS
10mA
Figure 39. DESAT Threshold (V
), Blanking Capacitor Charge Current (I
),
DESAT
CHG
Blanking Capacitor Discharge Current (I
) Test Circuit
DSCHG
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
VCC
0.1µF
0.1µF
FAULT
GND
0.1µF
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
V
O
+
–
15V
VO
0V
0V
10mA
V
UVLO+
V
UVLO–
VCLAMP
VSS
Figure 40. Under-Voltage Lockout Threshold (V
/ V
), Under-Voltage Lockout Threshold
UVLO+
UVLO-
Hysteresis (UVLO
) Test Circuit
HYS
FOD8333
1
2
3
4
5
6
7
8
16
GND
VCC
VE
15
VLED2+
0.1µF
0.1µF
14
FAULT
GND
DESAT
VDD
0.1µF
13
12
11
10
9
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
30V
+
–
VO
50Ω
VCLAMP
VSS
5V
10mA
+
–
V
TCLAMP
0V
0A
Figure 41. Clamping Threshold Voltage (V
) Test Circuit
CLAMP_THRES
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
20
Test Circuits (Continued)
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VCC
VLED2+
DESAT
VDD
0.1µF
0.1µF
FAULT
GND
0.1µF
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
30V
+
–
VO
I
CLAMPL
VCLAMP
VSS
+
–
2.5V
Figure 42. Clamp Low Level Sinking Current (I
) Test Circuit
CLAMPL
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
I
CCH
VCC
15V
V
FAULT
+
–
FAULT
GND
0.1µF
VLED1–
VLED1+
VLED1+
VLED1–
VSS
VO
VCLAMP
VSS
Figure 43. FAULT High Level Supply Current (I
) Test Circuit
CCH
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
16mA
0.1µF
I
CCL
VCC
15V
V
FAULT
+
–
FAULT
GND
0.1µF
VLED1–
VLED1+
VLED1+
VLED1–
VSS
VO
VCLAMP
VSS
Figure 44. FAULT Low Level Supply Current (I
) Test Circuit
CCL
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
21
Test Circuits (Continued)
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VCC
VLED2+
DESAT
VDD
0.1µF
I
FAULTH
+
–
5.5V
FAULT
GND
+
–
5.5V
VLED1–
VLED1+
VLED1+
VLED1–
VSS
VO
VCLAMP
VSS
Figure 45. FAULT High Level Output Current (I
) Test Circuit
FAULTH
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
10mA
0.1µF
VCC
0.1µF
V
FAULTL
+
–
5.5V
FAULT
GND
+
–
1.1mA
VLED1–
VLED1+
VLED1+
VLED1–
VSS
VO
VCLAMP
VSS
Figure 46. FAULT Low Level Output Voltage (V
) Test Circuit
FAULTL
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
VCC
0.1µF
FAULT
GND
0.1µF
+
–
VLED1–
VLED1+
VLED1+
VLED1–
V
E
VSS
30V
V
O
+
–
VO
0.1µF
10Ω
10nF
VCLAMP
VSS
10mA
f = 10kHz
DC = 50%
V
IN
R
M
Figure 47. Propagation Delay (t
, t
), Rise Time(t ), Fall Time (t ),
PLH PHL R F
Pulse Width Distortion (PWD) Test Circuit
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
22
Test Circuits (Continued)
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
V
E
100pF
V
V
CC
LED2+
4.7kΩ
V
CC
0.1µF
0.1µF
+
–
V
DESAT
FAULT
GND
DESAT
V
FAULT
0.1µF
V
DD
+
–
V
V
E
V
LED1–
SS
30V
V
O
+
–
V
V
LED1+
O
0.1µF
10Ω
V
V
LED1+
CLAMP
10nF
10mA
V
IN
V
V
LED1–
SS
R
M
Figure 48. DESAT Sense Delay (t
), t
), t
), DESAT Sense to
DESAT(90%)
DESAT(10%)
DESAT(LOW)
Low Level FAULT Signal Delay (t
), DESAT Input Mute (t
) Test Circuit
DESAT(FAULT)
DESAT(MUTE)
FOD8333
1
16
GND
V
E
2
15
14
13
12
11
10
9
V
V
CC
LED2+
0.1µF
3
FAULT
DESAT
0.1µF
4
GND
V
DD
+
–
5
V
V
E
V
LED1–
SS
20V
V
O
6
0.1µF
V
V
LED1+
O
10mA
t
t = t = 1ms
r f
UVLO
7
V
V
LED1+
CLAMP
TGP t = t = 10μs
r
f
8
V
V
LED1–
SS
Figure 49. Under-Voltage Lockout Delay (t
),Time-to-Good-Power (t ) Test Circuit
UVLO
GP
FOD8333
1
2
3
4
5
6
7
8
16
GND
V
E
15
14
13
12
11
10
9
V
V
CC
LED2+
4.7kΩ
5V
+
–
FAULT
GND
DESAT
15pF
or 1nF
V
DD
V
V
0.1µF
LED1–
SS
Scope
25V
0.1μF
+
–
V
V
LED1+
O
10Ω
360Ω
V
V
LED1+
CLAMP
10nF
V
V
LED1–
SS
V
CM
Figure 50. Common-Mode Low (CML) LED1-Off Test Circuit
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
23
Test Circuits (Continued)
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VCC
VLED2+
DESAT
VDD
4.7kΩ
5V
+
FAULT
GND
–
15pF
or 1nF
VLED1–
VLED1+
VLED1+
VLED1–
VSS
0.1µF
Scope
25V
0.1μF
+
–
VO
10Ω
360Ω
VCLAMP
VSS
10nF
V
CM
Figure 51. Common-Mode High (CMH) LED1-On Test Circuit
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
VCC
4.7kΩ
Scope
5V
+
–
FAULT
GND
15pF
or 1nF
VLED1–
VLED1+
VLED1+
VLED1–
VSS
0.1µF
25V
0.1μF
10Ω
+
–
VO
360Ω
VCLAMP
VSS
10nF
V
CM
Figure 52. Common-Mode High (CMH) LED2-Off Test Circuit
FOD8333
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VE
VLED2+
DESAT
VDD
VCC
4.7kΩ
5V
Scope
+
–
FAULT
GND
15pF
or 1nF
VLED1–
VLED1+
VLED1+
VLED1–
VSS
0.1µF
25V
0.1μF
10Ω
+
–
VO
360Ω
VCLAMP
VSS
10nF
V
CM
Figure 53. Common-Mode High (CML) LED2-On Test Circuit
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
24
Application Information
FOD8333
GND1
VE
VLED2+
DESAT
VDD
1
16
15
14
13
12
11
10
–
0.1µF
+
0.1µF
0.1µF
C
2
3
4
5
6
7
VCC
BLANK
R
D
DESAT
F
FAULT
GND
+HVDC
100Ω
C
F
+
–
V
Q1
Q2
CE
VLED–
VLED+
VLED+
VLED–
VSS
R
LED
R
G
VO
3-Phase
AC
VCLAMP
VSS
+
–
+
–
V
CE
8
9
–HVDC
Figure 54. Recommended Application Circuit
Functional Description
The functional behavioral of FOD8333 is illustrated by
the detailed internal schematic shown in Figure 55.
Figure 55 and the timing diagrams explain the interaction
and sequence of internal and external signals.
250μA
14
+
DESAT
–
V
DESAT
6, 7
V
V
LED1+
16
V
V
E
Delay
5, 8
UVLO Comparator
LED1–
13
–
+
DD
V
UVLO
11
V
O
50x
2
Pulse
Generator
V
CC
9
1x
V
V
SS
3
FAULT
1, 4
10
V
GND
LED2+
+
–
CLAMP
2V
25x
Figure 55. Detailed Internal Behavioral Schematic
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
25
Normal
Operation
Fault Condition
Automatic
Reset
I
F
Blanking
Time
6.5V
V
DESAT
V
O
FAULT
Figure 56. Operating Relationsip Among Desaturation Voltage (DESAT), Fault Output (FAULT),
and Reset Conditions
1. LED Input and Operation Explanation
(LED1) is greater than I
and the forward voltage V is
FLH F
greater than V (MIN). The timing relationship between
F
FOD8333 is an advanced IGBT gate-drive optocoupler
capable of driving most 1200 V / 150 A IGBTs and power
MOSFETs in motor control and inverter applications.
The following section describes driving IGBT, but is also
the LED input and gate driver output is illustrated in
Figure 3. When a fault is detected, the gate driver ouptut
IC immediately enters “soft” turn-off mode, where the
output voltage changes slowly from HIGH to LOW state.
This also disables the gate control input on the gate
applicable to driving MOSFET. Adjust the V
supply
DD
based on the gate threshold voltages. Critical protection
features and controls are incorporated to simplify the
design and improve reliability. The device includes an
IGBT desaturation detection protection and a FAULT
status output.
driver IC side for a minimum mute time, t
20 µs.
, of
DESAT(MUTE)
The FAULT output, which is open-collector configura-
tion, is latched to LOW state to report a fault status to the
microcontroller. It is only reset or pulled back to HIGH
This highly integrated device consists of two high-
performances AlGaAs LEDs and two integrated circuits.
LED1 directly controls the isolated gate driver IC output,
while the returned optical signal path is transmitted by
LED2, which reports the fault status through the open-
collector fault-sense IC output.
automatically after the fixed mute time, t
.
DESAT(MUTE)
The active Miller clamp function avoids the need of
negative gate driving in most applications and allows the
use of a simple bootstrap supply for the high-side driver.
2. Gate Driver Output
The control LED input and the fault-sense IC output
can be connected to a standard 3.3 V / 5 V DSP or
microcontroller. The gate driver output can be connected
to the gate of the power devices on the high-voltage side.
A pair of PMOS and NMOS make up the output driver
stage, which facilitates close to rail-to-rail output swing.
This feature allows tight control of gate voltage during
on-state and short-circuit conditions.
A
typical recommended application is shown in
The output driver can typically sink 2.5 A and source
Figure 54. A typical shunt LED drive can be used to
improve noise immunity. The LED is connected in
parallel with the bipolar transistor switch, creating a
current shunt drive. Common-mode transients from the
load coupling via the package capacitance can be
2.5 A at room temperature. Due to the low R
of the
DS(ON)
MOSFETs, the power dissipation is lower than bipolar-
type driver output stages. The absolute maximum rating
of the output peak current, I
, is 3 A. Careful
O(PEAK)
selection of the gate resistor, R , is required to avoid
coupled into
a
low-impedance path, either the
G
violation of this rating. For charging and discharging, the
conducting LED or the on resistance of the conducting
bipolar transistor, increasing its noise immunity.
R
value is approximated by:
G
R = V – V – V / I
OL OL(PEAK)
(1)
During normal operation, when no fault is detected,
G
CC
EE
LED1 controls the gate driver output. V is set to HIGH
O
when the current flowing from the anode to the cathode
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
26
As shown in Figure 55, the gate driver output is
influenced by signals from the photodetector circuitry,
the UVLO comparator, and the DESAT signals. Under
no-fault condition, normal operation resumes while the
supply voltage is above the UVLO threshold and the
output of the photodetector drives the MOSFETs of the
output stage. The logic circuitry of the output stage
ensures that the push-pull devices are never turned ON
simultaneously. When the output of the photodetector is
capacitance (C
), FAULT threshold voltage
BLANK
(V
), and DESAT charge current (I
):
DESAT
CHG
t
= C
x V / I
DESAT CHG
(2)
BLANK
BLANK
With a recommended 100 pF DESAT capacitor, the
nominal blanking time is:
100 pF x 6.5 V / 250 µA = 2.6 µs
4. Soft Turn-Off
HIGH, output V is pulled to HIGH state by turning on
the PMOS. When the output of the photodetector is
O
The soft turn-off feature ensures the safe shutdown of
the IGBT under fault condition. The gate-driver voltage
LOW, V is pulled to LOW state by turning on the
O
V
turns off the IGBT in a controlled slow manner. This
O
50XNMOS.
reduces the voltage spike on the collector of the IGBT.
Without this, the IGBT would see a heavy spike on the
collector, resulting in a permanent damage to the device
When V
supply goes below V
, which is the
DD
UVLO
designated ULVO threshold at the comparator, V is
O
when it’s turned off immediately. The V is pulled to
pulled to LOW state regardless of photodetector output.
O
LOW slowly in 4 µs.
When V is HIGH and desaturation is detected, V turns
O
O
5. Under-Voltage Lockout (UVLO)
off slowly as it is pulled LOW by the 1XNMOS device.
The input to the fault-sense circuitry is latched to HIGH
state and turns on the LED2. The fault-sense signal
remains in HIGH state until LED1 is switched from LOW
Under-Voltage detection prevents the application of
insufficient gate voltage to the IGBT. This could be
dangerous, as it would drive the IGBT out of saturation
and into the linear operation where losses are very high
and the IGBT quickly overheats. This feature ensures
to HIGH. When V goes below 2 V, the 50XNMOS
O
device turns on, clamping the IGBT gate firmly to V
.
SS
proper operation of the IGBTs. The output voltage, V ,
remains LOW irregardless of the inputs, as long as the
3. Desaturation Protection, FAULT Output and
FAULT RESET
O
supply voltage, V
– V , is less than V
during
DD
E
UVLO+
Desaturation detection protects the IGBT in short circuit
by monitoring the collector-emitter voltage of the IGBT
when it’s turned on. When the DESAT pin voltage goes
above the threshold voltage, a short-circuit condition is
detected and the driver output stage executes a “soft”
IGBT turn-off and is eventually driven LOW. This
sequence is illustrated in Figure 56. The FAULT open-
collector output is triggered active LOW to report a
desaturation error. The gate driver output is muted for
minimum of 20 µs. All input LED signals are ignored
during the mute period to allow the driver to completely
soft shutdown the IGBT. The fault mechanism is reset
power up. When the supply voltage falls below V
,
UVLO-
V
goes LOW, as illustrated in Figure 57.
O
6. Active Miller Clamp Function
An active Miller clamp feature allows the sinking of the
Miller current to ground during a high-dV/dt situation.
Instead of driving the IGBT gate to a negative supply
voltage to increase the safety margin, the device has a
dedicated V
pin to control the Miller current.
CLAMP
During turn-off, the gate voltage of the IGBT is monitored
and the V output is activated when the gate
CLAMP
voltage goes below 2 V (relative to V ).
SS
automatically after the t
(see Figure 56).
DESAT(MUTE)
The Miller clamp NMOS transistor is then turned on and
provides a low resistive path for the Miller current, which
helps prevent a self-turn-on due to the parasitic Miller
capacitor in power switches. The clamp voltage is V
2.5 V, typical for a Miller current up to 1100 mA.
During OFF state of the IGBT, or if V is LOW, the fault
O
sense circuitry is disabled to prevent false fault signals.
The DESAT comparator should be disabled for a short
period (blanking time) before the IGBT turns on to allow
the collector voltage to fall below the DESAT threshold.
+
SS
In this way, the V
function does not affect the turn-
CLAMP
This blanking period protects against false triggering of
the DESAT while the IGBT is turning on. The blanking
time is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
off characteristic. It helps to clamp the gate to the low
level throughout the turn-off time. During turn-on, where
the input of the driver is activated, the V
disabled or opened.
function is
CLAMP
capacitor (capacitor between DESAT and V pin). The
E
nominal blanking time can be calculated using external
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
27
I
FLH
I
F
V
V
UVLO+
UVLO–
V
DD
– V
E
t
GP
V
O
Figure 57. Time to Good Power
9. DESAT Pin Protection
7. Time to Good Power
During fast power up (e.g. bootstrap power supply), the
LED is off and the output of the gate driver should be in
the LOW or OFF state. Sometimes, race conditions exist
During turn off, especially with inductive load, a large
instantaneous forward-voltage transient can appear on
the freewheeling diode of the IGBT. A large negative
voltage spike on the DESAT pin can result and draw
substantial current out of the gate driver IC if there is not
current-limiting resistor. To limit this current, a 100 Ω to
1 kΩ resistor should be inserted in series with the
DESAT diode. The added resistance does not change
the DESAT threshold or the DESAT blanking time.
that cause the output to follow V until all of the circuits
DD
in the output IC stabilize. This condition can result in
output transitions or transients that are coupled to the
driven IGBT. These glitches can cause the high- and
low-side IGBTs to conduct shoot-through current that
can damage the power semiconductor devices.
Fairchild has introduced a initial turn-on delay, called
“time to good power.” This delay, typically 2 µs, is only
present during the initial power-up of the device. If the
LED is ON during the initial turn-on activation, low-to-
high transition at the output of the gate driver only occurs
The DESAT diode protects the gate driver IC from high
voltages when the IGBT is turning off, while allowing a
forward I
current of 250 µA to be conducted to sense
CHG
the IGBT’s saturated collector to emitter voltage when
the IGBT is turned on. A fast-recovery diode, t below
rr
2 µs after the V power is applied.
75 ns, with sufficient reverse-voltage rating, should be
used. Fairchild offers many of these ultra-fast diodes/
DD
8. Dual Supply Operation – Negative Bias at V
SS
rectifiers, such as ES1J-600V, with t at 35 ns.
rr
The IGBT’s off-state noise immunity can be enhanced by
providing a negative gate-to-emitter bias when the IGBT
is in OFF state. This static off-state bias can be supplied
by connecting a separate negative voltage source
If two diodes or more are used, the required maximum
reverse voltage can be reduced by half or accordingly.
This modifies the trigger level for a fault condition. The
sum of the DESAT diode forward-voltage and the IGBT
between the V (pin 16) and V (pin 9 and pin 12). The
E
SS
collector-emitter V
voltage form the voltage at the
CE
primary ground reference is the IGBT’s emitter
DESAT pin. The trigger level for a fault condition given by:
V = V – n x V (3)
CE@FAULT
connection, V (pin 16). The under-voltage lockout
E
threshold and desaturation voltage detection are
DESAT
F
referenced to the IGBT’s emitter (V ) ground.
E
where n is the number of the DESAT diodes.
The negative voltage supply at V appears at the gate
SS
10. Pull-Up Resistor on FAULT Pin
drive output, V , when in LOW state. When the input
O
drives the output HIGH, the output voltage, V , has the
O
The FAULT pin is an open-collector output and can be
connected as wire-OR operation with other types of
protection (e.g., over-temperature, over-voltage, over-
current) to alert the microcontroller. Being an open-
collector output, it requires a pull-up resistor to provide a
normal high output voltage level. This resistor value
must be properly considered based on various IC
interface requirements. The sinking current capability is
potential of the V
and V
.
Proper power supply
DD
SS
bypass capacitors are added to provide paths for the
instantaneous gate charging and discharging currents.
The Schottky diode is recommended connected
between V and V to protect against a reverse voltage
E
SS
greater than 0.5 V. The V
(pin 10) should be
CLAMP
connected to V when not in use.
SS
given by I
.
FAULTL
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
28
11. Increasing the Output Drive Current Using an
External Booster Stage
A possible implementation is by a discrete NPN/PNP
totem-pole configuration. These booster transistors
should be fast switching and have sufficient current gain
to deliver the desired peak output current.
If larger gate drive capability is needed for large IGBT
modules or parallel operation, an output booster stage
may be added to driver for optimum performance.
FOD8333
VE
16
0.1µF
CBLANK
DDESAT
15
14
13
12
11
10
VLED2+
DESAT
VDD
100Ω
0.1µF
+
–
VSS
RG
VO
VCLAMP
VSS
9
–
+
Figure 58. Output Booster Stage for Increased Output Drive Current
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
29
Ordering Information
Part Number
Package
Packing Method
FOD8333
SO 16-Pin
SO 16-Pin
Tube (50 units per tube)
FOD8333R2
FOD8333V
FOD8333R2V
Tape and Reel (750 units per reel)
Tube (50 units per tube)
SO 16-Pin, DIN EN/IEC 60747-5-5 Option
SO 16-Pin, DIN EN/IEC 60747-5-5 Option
Tape and Reel (750 units per reel)
All packages are lead free per JEDEC: J-STD-020B standard.
Marking Information
1
2
3
V
8333
8
J
D X YYKK
6
5
4
7
Definitions
1
2
3
Fairchild logo
Device number, e.g., ‘8333’ for FOD8333
DIN EN/IEC60747-5-5 Option (only appears on component
ordered with this option) (pending approval)
4
5
6
7
8
Plant code, e.g., ‘D’
Alphabetical year code, e.g., ‘E’ for 2014
Two-digit work week ranging from ‘01’ to ‘53’
Lot traceability code
Package assembly code, e.g., ‘J’
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
30
Reflow Profile
Max. Ramp-Up Rate = 3 °C/s
Max. Ramp-Down Rate = 6 °C/s
T
P
260
240
220
200
180
160
140
120
100
80
t
P
T
L
T
smax
t
L
Preheat Area
T
smin
t
s
60
40
20
0
120
Time 25 °C to Peak
240
360
Time (seconds)
Figure 59. Relow Profile
Profile Freature
Pb-Free Assembly Profile
150°C
Temperature Minimum (T
)
smin
Temperature Maximum (T
)
200°C
smax
Time (t ) from (T
to T )
smax
60–120 seconds
3°C/second maximum
217°C
S
smin
Ramp-up Rate (t to t )
L
P
Liquidous Temperature (T )
L
Time (t ) Maintained Above (T )
60–150 seconds
260°C +0°C / –5°C
30 seconds
L
L
Peak Body Package Temperature
Time (t ) within 5°C of 260°C
P
Ramp-Down Rate (T to T )
6°C/second maximum
8 minutes maximum
P
L
Time 25°C to Peak Temperature
©2014 Fairchild Semiconductor Corporation
FOD8333 Rev. 1.0.3
www.fairchildsemi.com
31
0.20 C A-B
1.27 TYP
16
0.64 TYP
9
2X
10.30
A
D
16
9
3.75
10.30
7.50
(2.16)
1
0.10 C D
PIN ONE
8
2X
0.33 C
2X 8 TIPS
1
8
LAND PATTERN
RECOMMENDATION
1.27
INDICATOR
0.51
0.31
(16X)
B
0.51 TYP
0.25
C A-B D
A
0.10 C
3.0 MAX
2.35±0.10
0.10 C
16X
SEATING PLANE
0.30±0.15
C
NOTES: UNLESS OTHERWISE SPECIFIED
(1.42)
A) DRAWING REFERS TO JEDEC MS-013,
VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF
BURRS, MOLD FLASH AND TIE BAR
PROTRUSIONS
(R0.17)
(R0.17)
GAUGE
PLANE
D) DRAWING CONFORMS TO ASME
Y14.5M-1994
E) LAND PATTERN STANDARD:
SOIC127P1030X275-16N
0.25
0.19
8°
0°
F) DRAWING FILE NAME: MKT-M16FREV2
0.25
1.27
0.40
C
SEATING
PLANE
SCALE: 3:1
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