FOD8012AR2 [ONSEMI]
高 CMR，双向，逻辑门极光耦合器;
| 型号： | FOD8012AR2 |
| 厂家： | 
ONSEMI |
| 描述： | 高 CMR，双向，逻辑门极光耦合器 光电 |
| 文件： | 总11页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Logic Gate Optocoupler,
High CMR, Bi-Directional
FOD8012A
Description
SOIC8
CASE 751DZ
The FOD8012A is a half duplex, bi−directional, high−speed logic
gate Optocoupler, which supports isolated communications allowing
digital signals to communicate between systems without conducting
ground loops or hazardous voltages. It utilizes onsemi’s patented
MARKING DIAGRAM
1
®
coplanar packaging technology, OPTOPLANAR , and optimized IC
design to achieve minimum 20 kV/ms Common Mode Noise Rejection
(CMR) rating.
2
5
ON
X
8012A
This high−speed logic gate optocoupler is highly integrated with 2
optically coupled channels arranged in bi−directional configuration,
and housed in a compact 8−pin small outline package. Each
optocoupler channel consists of a high−speed AlGaAs LED driven by
a CMOS buffer IC coupled to a CMOS detector IC. The detector IC
comprises of an integrated photodiode, a high−speed trans−impedance
amplifier and a voltage comparator with an output driver. The CMOS
technology coupled to the high efficiency of the LED achieves low
power consumption as well as very high speed (60 ns propagation
delay, 15 ns pulse width distortion).
YY S1
4
3
1.
2.
3.
4.
ON = onsemi Logo
8012A= Device Number
X
YY
= One−Digit Year Code, e.g. ‘8’
= Two Digit Work Week Ranging
from ‘01’ to ‘53’
Features
5.
S1
= Assembly Package Code
• Half Duplex, Bi−Directional
• 20 kV/ms Minimum Common Mode Rejection
• High Speed:
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
♦ 15 Mbit/s Date Rate (NRZ)
♦ 60 ns Maximum Propagation Delay
♦ 15 ns Maximum Pulse Width Distortion
♦ 30 ns Maximum Propagation Delay Skew
• 3.3 V and 5 V CMOS Compatibility
• Extended Industrial Temperate Range, −40 to +110°C Temperature
Range
• Safety and Regulatory Approvals:
♦ UL1577, 3750 VAC
for 1 min.
RMS
♦ DIN EN/IEC60747−5−5 (approval pending)
Applications
• Industrial Fieldbus Communications
♦ DeviceNet, CAN, RS485
• Microprocessor System Interface
2
♦ SPI, I C
• Programmable Logic Control
• Isolated Data Acquisition System
• Voltage Level Translator
Related Resources
• FOD8001/D, High Noise Immunity, 3.3 V/5 V Logic Gate
Optocoupler Datasheet
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
January, 2022 − Rev. 2
FOD8012A/D
FOD8012A
TRUTH TABLE
V
LED
OFF
ON
V
O
IN
High
Low
High
Low
NOTE: When not communicating, V must be in static high logic condition.
IN
Functional Schematic
1
8
7
VDD1
VDD2
VOA
VINA
2
VINB
VOB
3
4
6
5
GND1
GND2
0.1μF bypass capacitor required from VDD to GND
Figure 1. Functional Schematic
PIN DEFINITIONS
Pin Name
Pin Number
Description
V
1
2
Supply Voltage to Channel−A detector IC and Channel−B buffer IC
Output Voltage from Channel−A detector IC
DD1
V
OA
3
4
5
Input Voltage to Channel−B buffer IC
V
INB
GND
GND
Ground for Channel−A detector IC and Channel−B buffer IC
Ground for Channel−A buffer IC and Channel−B detector IC
1
2
6
7
8
Output Voltage from Channel−B detector IC
V
OB
Input Voltage to Channel−A buffer IC
V
INA
Supply Voltage to Channel−A buffer IC and Channel−B detector IC
V
DD2
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2
FOD8012A
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise specified)
A
Symbol
Parameter
Value
Units
°C
T
STG
Storage Temperature
Operating Temperature
Junction Temperature
−40 to +125
−40 to +110
−40 to +130
260 for 10 s
0 to 6.0
T
OPR
°C
T
J
°C
T
SOL
Lead Solder Temperature (Refer to Reflow Temperature Profile)
Supply Voltage
°C
V
, V
DD2
V
DD1
V , V
Input Voltage
−0.5 to V + 0.5
V
IA
IB
DD
I , I
Input DC Current
−10 to +10
mA
V
IA IB
V
, V
Output Voltage
−0.5 to V + 0.5
OA
OB
DD
I
, I
Average Output Current
10
60
60
mA
mW
mW
OA OB
PD
Input Power Dissipation (Note 1)
Output Power Dissipation (Note 1)
I
PD
O
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. No derating required.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Ambient Operating Temperature
Supply Voltages (3.3 V Operation) (Note 2)
Supply Voltages (5.0 V Operation) (Note 2)
Logic High Input Voltage
Min.
−40
3.0
4.5
2.0
0
Max.
+110
3.6
Unit
°C
T
A
V
, V
DD2
V
DD1
5.5
V
IH
V
DD
V
V
V
IL
Logic Low Input Voltage
0.8
1.0
t , t
Input Signal Rise and Fall Time
ms
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. 0.1 mF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. The capacitors should be kept close to the supply pins.
ISOLATION CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at T = 25°C)
A
Symbol
Characteristics
Test Conditions
Min.
Typ.
Max.
Unit
Input−Output Isolation Voltage
3750
VacRMS
V
ISO
f = 60 Hz, t = 1.0 min., II−O ≤ 10 mA (Notes 3, 4)
VI−O = 500 V (Note 3)
11
W
Isolation Resistance
Isolation Capacitance
10
R
C
ISO
ISO
VI−O = 0 V, f = 1.0 MHz (Note 3)
0.2
pF
3. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
4. 3,750 VAC for 1 minute duration is equivalent to 4,500 VAC for 1 second duration.
RMS
RMS
ELECTRICAL CHARACTERISTICS (T = −40°C to +110°C, 3.0 V ≤ V ≤ 5.5 V, unless otherwise specified.
A
DD
Apply over all recommended conditions, typical value is measured at V
= V = +3.3 V, T = 25°C)
DD2 A
DD1
Symbol
, I
Parameter
Logic Low Supply Current
Logic High Supply Current
Input Current
Conditions
Min.
Typ.
5.8
Max.
8.0
Units
mA
mA
mA
I
V , V = 0 V
IA IB
DD1L DD2L
I
, I
V , V = V
DD
2.5
4.0
DD1H DD2H
IA
IB
I , I
IA IB
−10
3.2
3.0
4.9
4.7
+10
V
OH
Logic High Output Voltage
3.3
3.1
5.0
4.8
0
V
I
O
I
O
I
O
I
O
I
O
I
O
= −20 mA, V = V , V = 3.3 V
I IH DD
= −4 mA, V = V , V = 3.3 V
I
IH
DD
= −20 mA, V = V , V = 5 V
I
IH
DD
= −4 mA, V = V , V = 5 V
I
IH
DD
V
OL
Logic Low Output Voltage
0.1
0.6
V
= 20 mA, V = V , V = 3.3 V or 5 V
I
IL
DD
= 4 mA, V = V , V = 3.3 V or 5 V
0.26
I
IL
DD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
FOD8012A
SWITCHING CHARACTERISTICS (T = −40°C to +110°C, 3.0 V ≤ V ≤ 5.5 V, unless otherwise specified.
A
DD
Apply over all recommended conditions, typical value is measured at V
= V = +3.3 V, T = 25°C)
DD2 A
DD1
Symbol
Parameter
Conditions
Min.
Typ.
Max.
15
Unit
Mbit/s
ns
Data Rate
t
t
Propagation Delay Time to Logic Low Output
Propagation Delay Time to Logic High Output
PW = 66.7 ns, C = 15 pF
37
40
3
60
PHL
L
PW = 66.7 ns, C = 15 pF
60
ns
PLH
L
PWD
Pulse Width Distortion, | t
Channel−Channel Skew
Part−Part Skew
– t
PLH
|
PW = 66.7 ns, C = 15 pF
15
ns
PHL
L
(Note 5)
t
PW = 66.7 ns, C = 15 pF
12
25
30
ns
ns
PSK(CC)
L
(Note 6)
t
PW = 66.7 ns, C = 15 pF
PSK(PP)
L
(Note 7)
t
Output Rise Time (10% to 90%)
Output Fall Time (90% to 10%)
PW = 66.7 ns, C = 15 pF
6.5
6.5
40
ns
ns
R
L
t
PW = 66.7 ns, C = 15 pF
L
F
|CM |
Common Mode Transient Immunity at Output
High
V = V
, V > 0.8 V ,
O DD1
20
20
kV/ms
H
I
DD1
V
CM
= 1000 V (Note 8)
|CM |
Common Mode Transient Immunity at Output
Low
V = 0 V, V < 0.8 V,
40
kV/ms
L
I
O
V
CM
= 1000 V (Note 8)
5. PWD is equal to the magnitude of the worst case difference in t
and/or t
that will be seen for one channel switching, while holding
PHL
PLH
the other channel output at a low or high state, or while both channels are in synchronous data transmission mode.
6. t is equal to the magnitude of the worst case difference in t and/or t that will be seen between the two channels within a single
PSK(CC)
PHL
PLH
device.
7. t
is equal to the magnitude of the worst case difference in t
and/or t
that will be seen between any two units from the same
PSK(PP)
PHL
PLH
manufacturing date code that are operated at same case temperature, at same operating conditions, with equal loads.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of the common mode
impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable
negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to assure that the output will remain low.
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4
FOD8012A
TYPICAL PERFORMANCE CURVES
4.0
3.0
2.0
2.0
1.8
V
= V
= 3.3V
DD1
DD1
1.6
1.4
1.0
0
1.2
1.0
0
1
2
3
4
5
3.0
3.5
4.0
4.5
5.0
5.5
VI – INPUT VOLTAGE (V)
VDD – SUPPLY VOLTAGE (V)
Figure 2. Typical Output Voltage vs. Input Voltage
(Channel A & B)
Figure 3. Typical Input Voltage Switching Threshold
vs. Input Supply Voltage (Channel A & B)
54
2
Frequency = 7.5MHz
Frequency = 7.5MHz
Duty Cycle = 50%
Duty Cycle = 50%
V
= V
= 3.3V
V
= V = 3.3V
1
DD1
DD2
DD1
DD2
50
46
0
−1
−2
−3
42
38
t
PLH
t
PHL
−4
−5
−6
34
30
−40 −20
0
20
40
60
80
100 110
−40 −20
0
20
40
60
80
100 110
TA – AMBIENT TEMPERATURE (°C)
TA – AMBIENT TEMPERATURE (°C)
Figure 4. Typical Propagation Delay vs. Ambient
Temperature (Channel A & B)
Figure 5. Typical tPHL − tPLH vs. Ambient Temperature
(Channel A & B)
7.0
9.0
Frequency = 7.5MHz
Frequency = 7.5MHz
Duty Cycle = 50%
Duty Cycle = 50%
V
= V
= 3.3V
V
= V = 3.3V
8.5
8.0
DD1
DD2
DD1
DD2
6.5
6.0
5.5
7.5
7.0
6.5
t
R
t
F
5.0
4.5
4.0
6.0
5.5
5.0
−40 −20
0
20
40
60
80
100 110
−40 −20
0
20
40
60
80
100 110
TA – AMBIENT TEMPERATURE (°C)
TA – AMBIENT TEMPERATURE (°C)
Figure 6. Typical Rise Time vs. Ambient
Temperature (Channel A & B)
Figure 7. Typical Fall Time vs. Ambient
Temperature (Channel A & B)
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5
FOD8012A
TYPICAL PERFORMANCE CURVES (Continued)
45
43
41
0
Frequency = 7.5MHz
Duty Cycle = 50%
Frequency = 7.5MHz
Duty Cycle = 50%
V
= V = 3.3V
V
= V = 3.3V
DD1
DD2
DD1
DD2
−1
t
PLH
−2
−3
t
PHL
39
37
−4
−5
35
15
20
25
30
35
40
45
50
55
15
20
25
30
35
40
45
50
55
CL – OUTPUT LOAD CAPACITANCE (pF)
CL – OUTPUT LOAD CAPACITANCE (pF)
Figure 8. Typical Propagation Delay vs. Output
Load Capacitance (Channel A & B)
Figure 9. Typical tPHL − tPLH vs. Output
Load Capacitance (Channel A & B)
12
16
14
Frequency = 7.5MHz
Duty Cycle = 50%
Frequency = 7.5MHz
Duty Cycle = 50%
V
= V = 3.3V
V
= V
= 3.3V
DD1
DD2
DD1
DD2
10
8
12
10
t
t
F
R
6
8
6
4
4
2
15
20
25
30
35
40
45
50
55
15
20
25
30
35
40
45
50
55
CL – OUTPUT LOAD CAPACITANCE (pF)
CL – OUTPUT LOAD CAPACITANCE (pF)
Figure 10. Typical Rise Time vs. Output
Load Capacitance (Channel A & B)
Figure 11. Typical Fall Time vs. Output
Load Capacitance (Channel A & B)
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6
FOD8012A
TYPICAL PERFORMANCE CURVES (Continued)
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
7.5
V
V
= V
DD2
= 5.5V, T
Switching
V
V
V
= V = 5.5V, T = 25°C
DD2 A
= 25°C
DD1
A
DD1
INB
INA
T
= 25°C
and V
= 0V @ I
, V
Switching
A
INA
INB
DD1 INA
= 0V @ I
, V
Switching
7.0
6.5
6.0
5.5
5.0
4.5
4.0
Pin 2 and 6 Floating
DD2 INB
Pin 2 and 6 Floating
T
= −40°C
A
T
= 25°C
A
T
= 110°C
A
T
= −40°C
A
T
= 110°C
A
0
2,000
4,000
6,000
8,000
10,000 12,000 14,000
0
2,000
4,000
6,000
8,000
10,000 12,000 14,000
F – FREQUENCY (kHz)
F – FREQUENCY (kHz)
Figure 12. Typical IDD1 DD2
/I
Supply Current vs.
Figure 13. Typical IDD1 DD2
/I
Supply Current vs.
Frequency
Frequency
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
V
V
V
= V = 5.5V, T = 25°C
DD2 A
DD1
INA
INB
= 0V @ I
, V
Switching
DD1 INB
= 0V @ I
, V
Switching
DD2 INA
Pin 2 and 6 Floating
T
A
= 25°C
T
= −40°C
A
T
A
= 110°C
0
2,000
4,000
6,000
8,000
10,000 12,000 14,000
F – FREQUENCY (kHz)
Figure 14. Typical IDD1/IDD2 Supply Current vs.
Frequency
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7
FOD8012A
TEST CIRCUITS
1
2
8
7
V
OA
V
DD2
0.1 mF
0.1 mF
C
L
0V~3.3V
V
OB
3
4
6
5
V
DD1
t
t
PLH
PHL
3.3V
Input
50%
V
IN
V
50%
90%
10%
OH
Output
V
V
OUT
OL
t
t
R
F
Figure 15. Test Circuit for Propagation Delay Time and Rise Time, Fall Time
1
2
8
7
V
A
OA
0.1 mF
V
DD2
B
0.1 mF
C
L
3
4
6
5
V
DD1
–
+
Vcm
Pulse Gen
V
CM
GND
V
OH
CM
H
Switching Pos. (A), V = 3.3V
IN
0.8 x V
DD
0.8V
Switching Pos. (B), V = 0V
V
OL
IN
CM
L
Figure 16. Test Circuit for Instantaneous Common Mode Rejection Voltage
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8
FOD8012A
ORDERING INFORMATION
†
Option
No Suffix
R2
Order Entry Identifier
FOD8012A
Package
Packing Method
Tube (50 Units per Tube)
Tape and Reel (2,500 Units per Reel)
SOIC8 (Pb−Free)*
SOIC8 (Pb−Free)*
FOD8012AR2
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*All packages are lead free per JEDEC: J−STD−020B standard.
REFLOW PROFILE
Max. Ramp−up Rate = 3°C/s
Max. Ramp−down Rate = 6°C/s
260
T
P
245
240
t
P
T
L
220
200
180
160
140
120
100
80
Tsmax
t
L
Tsmin
t
s
60
40
20
0
120
240
360
Time 25°C to Peak
Time (s)
Profile Freature
Pb−Free Assembly Profile
150°C
Temperature Min. (Tsmin)
Temperature Max. (Tsmax)
200°C
Time (t ) from (Tsmin to Tsmax)
60 − 120 s
S
Ramp−up Rate (t to t )
3°C/s max.
217°C
L
P
Liquidous Temperature (T )
L
Time (t ) Maintained Above (T )
60 − 150 s
L
L
Peak Body Package Temperature
245°C + 0°C / −5°C
30 s
Time (t ) within 5°C of 245°C
P
Ramp−down Rate (T to T )
6°C/s max.
8 minutes max.
P
L
Time 25°C to Peak Temperature
OPTOPLANAR is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States
and/or other countries.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751DZ
ISSUE O
DATE 30 SEP 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13733G
SOIC8
PAGE 1 OF 1
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