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April 2007

FMS6501

12 Input / 9 Output Video Switch Matrix with Input Clamp,

Input Bias Circuitry, and Output Drivers

Features

Description

■ 12 x 9 Crosspoint Matrix

The FMS6501 switch matrix provides flexible options for

today’s video applications. The 12 inputs that can be

routed to any of nine outputs. Each input can be routed

to one or more outputs, but only one input may be routed

to any one output. The input to output routing is con-

trolled via an I²C™-compatible digital interface.

■ Supports SD, PS, and HD 1080i/1080p Video

■ Input Clamp / Bias Circuitry

■ AC or DC-Coupled Inputs

■ AC or DC-Coupled Outputs

■ Dual-Load (75Ω) Output Drivers with High-Impedance

Each input supports an integrated clamp option to set the

output sync tip level of video with sync to ~300mV. Alter-

natively, the input may be internally biased to center sig-

nals without sync (Chroma, Pb, Pr) at ~1.25V. These DC

output levels are for the 6dB gain setting. Higher gain

settings increase the DC output levels accordingly. The

input clamp / bias mode is selected via I²C.

Disable

■ One-to-One or One-to-Many Input to Output Switching

■ Programmable Gain: +6, +7, +8, or +9dB

■ I²C^TMCompatible Digital Interface, Standard Mode

■ 3.3V or 5V Single-Supply Operation

■ Lead-Free SSOP-28 Package

Unused outputs may be powered down to reduce power

dissipation.

Applications

■ Cable and Satellite Set-Top Boxes

■ TV and HDTV Sets

■ A/V Switchers

■ Personal Video Recorders (PVR)

■ Security / Surveillance

■ Video Distribution

■ Automotive (In-Cabin Entertainment)

Ordering Information

Part Number

FMS6501MSA28

FMS6501MSA28X

Pb-Free

Yes

Temperature Range

-40°C to 85°C

Package

SSOP-28

Container

Rail

Quantity

47

Yes

-40°C to 85°C

Reel

2000

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

Block Diagram

IN1

IN2

C / B

IN12

C / B

SDA

SCL

ADDR

Programmable Gain

6, 7, 8, or 9dB

VCC (2)

GND (2)

Programmable

Enable/Disable

OUT1

OUT2

OUT9

Figure 1. FMS6501 Block Diagram

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

2

Pin Assignments

Pin Configuration

Pin#

1

Name

IN1

Type

Description

IN1

IN2

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

VCCO

GNDO

OUT7

OUT8

OUT9

SDA

Input Input, channel 1

Input Input, channel 2

Input Input, channel 3

Input Input, channel 4

Input Input, channel 5

Input Input, channel 6

Input Positive power supply

Input Must be tied to ground

Input Input, channel 7

Input Input, channel 8

Input Input, channel 9

Input Input, channel 10

Input Input, channel 11

Input Input, channel 12

2

IN2

IN3

3

IN3

4

IN4

4

5

IN5

FAIRCHILD

FMS6501

IN5

5

6

IN6

6

7

VCC

GND

IN7

28L SSOP

VCC

GND

IN7

7

8

9

10

11

12

13

14

IN8

9

IN9

IN8

10

11

12

13

14

IN10

IN11

IN12

IN9

IN10

IN11

IN12

Selects I²C address. “0” = 0x06

(0000 0110), ‘1” = 0x86 (1000 0110)

SCL

15

ADDR

Input

ADDR

16

17

18

19

20

21

22

23

24

25

26

27

28

SCL

SDA

Input Serial clock for I²C port

Input Serial data for I²C port

Output Output, channel 9

Output Output, channel 8

Output Output, channel 7

Input Must be tied to ground

Input Positive power supply for output drivers

Output Output, channel 6

Output Output, channel 5

Output Output, channel 4

Output Output, channel 3

Output Output, channel 2

Output Output, channel 1

Figure 2. Pin Configuration

OUT9

OUT8

OUT7

GNDO

VCCO

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-

ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-

tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The

absolute maximum ratings are stress ratings only.

Parameter

Min.

-0.3

Max.

6.0

Unit

V

DC Supply Voltage

Analog and Digital I/O

V_cc+ 0.3

40

V

Output Current Any One Channel, Do Not Exceed

mA

Reliability Information

Symbol

T_J

Parameter

Min.

Typ.

Max.

Unit

°C

Junction Temperature

150

300

T_STG

T_L

Storage Temperature Range

-65

°C

Lead Temperature (Soldering, 10 seconds)

Thermal Resistance, JEDEC Standard Multilayer Test Board, Still Air

°C

Θ_JA

50

°C/W

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol

T_A

Parameter

Operating Temperature Range

Supply Voltage Range

Min.

-40

Typ.

Max.

85

Unit

°C

V_CC

3.135

5.000

5.250

V

Electrostatic Discharge Protection

Symbol

HBM

Parameter

Value

Unit

Human Body Model

5

2

kV

CDM

Charged Device Model

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

4

Digital Interface

The I²C-compatible interface is used to program output

enables, input to output routing, input clamp / bias, and

output gain. The I²C address of the FMS6501 is 0x06

(0000 0110) with the ability to offset it to 0x86 (1000

0110) by tying the ADDR pin high.

same input channel for one-to-many routing. When the

outputs are disabled, they are placed in a high-imped-

ance state. This allows multiple FMS6501 devices to be

paralleled to create a larger switch matrix. Typical output

power-up time is less than 500ns.

Both data and address data, of eight bits each, are writ-

ten to the I²C address to access all the control functions.

The clamp / bias control bits are written to their own

internal address, since they should always remain the

same regardless of signal routing. They are set based on

the input signal connected to the FMS6501.

There are separate internal addresses for each output.

Each output’s address includes bits to select an input

channel, adjust the output gain, and enable or disable

the output amplifier. More than one output can select the

All undefined addresses may be written without effect.

Output Control Register Contents and Defaults

Control Name Width

Type

Write

Default Bit(s)

Description

Channel Enable: 1=Enable, 0=Power Down⁽¹⁾

Enable

Gain

Inx

1 bit

2 bits

5 bits

0

7

6:5

4:0

Channel Gain: 00=6dB, 01=7dB, 10=8dB, 11=9dB

Input selected to drive this output: 00000=OFF⁽²⁾

00001=IN1, 00010=IN2... 01100=IN12

,

Notes:

1. Power down places the output in a high-impedance state so multiple FMS6501 devices may be paralleled. Power

down also de-selects any input routed to the specified output.

2. When all inputs are OFF, the amplifier input is tied to approximately 150mV and the output goes to approximately

300mV with the 6dB gain setting.

Output Control Register MAP

Register Register

(1)

Name

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

Address

Bit 7

Bit 6

Gain1

Bit5

Bit4

IN4

Bit3

IN3

Bit2

IN2

Bit1

IN1

Bit0

IN0

0x01

Enable

Gain0

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Notes:

1. IN4 is provided for forward compatibility and should always be written as ‘0’ in the FMS6501.

Clamp Control Register Contents and Defaults

Control Name

Width

Type

Default

Bit(s)

Description

Clamp / Bias selection: 1 = Clamp, 0 = Bias

Clmp

1 bit

Write

0

7:0

Clamp Control Register Map

Register

Register Name Address

Bit 7

Clmp8

Resv’d

Bit 6

Clmp7

Resv’d

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

CLAMP1

CLAMP2

0x1D

0x1E

Clmp6

Resv’d

Clmp5

Clmp4

Clmp3

Clmp2

Clmp1

Clmp9

Resv’d Clmp12 Clmp11 Clmp10

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

5

DC Electrical Characteristics

T = 25°C, V = 5V, V = 1V , input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with

A

cc

IN

pp

0.1µF, unused inputs AC-terminated through 75Ω to GND, all outputs AC coupled with 220µF into 150Ω

loads, referenced to 400kHz, unless otherwise noted.

Symbol

I_CC

Parameter

Supply Current¹

Conditions

Min.

Typ.

80

Max

Units

mA

V_pp

kΩ

V

No load, all outputs enabled

100

V_OUT

R_OFF

V_clamp

V_bias

Video Output Range

2.8

3.0

0.3

1.25

50

Off Channel Output Impedance

DC Output Level¹

Output disabled

Clamp mode

Bias mode

0.2

0.4

1.15

1.35

V

PSRR

Power Supply Rejection Ratio

All channels, DC

dB

Notes:

1. 100% tested at 25°C.

AC Electrical Characteristics

T = 25°C, V = 5V, V = 1V , input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with

A

CC

IN

pp

0.1µF, unused inputs AC-terminated through 75Ω to GND, all outputs AC coupled with 220µF into 150Ω

loads, referenced to 400kHz, unless otherwise noted.

Symbol

Parameter

Channel Gain⁽¹⁾Error

Conditions

All Channels, All Gain Settings, DC

All Channels, DC

V_OUT= 1.4V_pp

Min.

-0.2

0.9

Typ.

0

Max

+0.2

1.1

Units

dB

AV_SD

AV_STEPGain Step⁽¹⁾

1.0

65

dB

f_+1dB

f_-1dB

f_C

1dB Peaking Bandwidth

MHz

%

-1dB Bandwidth

-3dB Bandwidth

Differential Gain

Differential Phase

SD Output Distortion

V_OUT= 1.4V_pp

90

V_OUT= 1.4V_pp

115

0.1

0.2

0.05

0.6

-72

-50

-68

-61

-45

73

dG

3.58MHz

dP

3.58MHz

deg

%

THD_SD

V_OUT= 1.4V_pp, 5MHz

V_OUT= 1.4V_pp, 22MHz

THD_HDHD Output Distortion

%

(2)

X_TALK1

X_TALK2

X_TALK3

X_TALK4

X_TALK5

Input Crosstalk

1MHz, V_OUT= 2V_pp

dB

(2)

Input Crosstalk

15MHz, V_OUT= 2V_pp

dB

(3)

Output Crosstalk

Multi-Channel Crosstalk

1MHz, V_OUT= 2V_pp

dB

(3)

15MHz, V_OUT= 2V_pp

dB

(4)

Standard Video, V_OUT= 2V_pp

dB

SNR_SDSignal-to-Noise Ratio⁽⁵⁾

NTC-7 Weighting, 4.2MHz LP,

100kHz HP

dB

V_NOISE

Channel Noise

400kHz to 100MHz, Input Referred

Post I²C Programming

20

nV/rtHz

ns

AMP_ONAmplifier Recovery Time

300

Notes:

1. 100% tested at 25°C.

2. Adjacent input pair to adjacent output pair. Interfering input is through an open switch.

3. Adjacent input pair to adjacent output pair. Interfering input is through a closed switch.

4. Crosstalk of eight synchronous switching outputs onto single, asynchronous switching output.

5. Signal-to-Noise Ration (SNR) = 20 * log (714mV / rms noise).

www.fairchildsemi.com

FMS6501 Rev. 1.0.4

6

2

I C BUS Characteristics

T = 25°C and V = 5V unless otherwise noted.

A

CC

Symbol

Parameter

Conditions

SDA, SCL, ADDR

SCK

Min.

0

Typ.

Max Units

V_il

V_ih

Digital Input Low⁽¹⁾

Digital Input High⁽¹⁾

Clock Frequency

Input Rise Time

1.5

V_cc

V

3.0

f_scl

100

1000

300

4.7

4.0

300

0

kHz

ns

µs

ns

µs

tr

1.5V to 3V

tf

Input Fall Time

1.5V to 3V

t_low

t_high

t_SU,DAT

Clock Low Period

Clock High Period

Data Set-up Time

t_HD,DATData Hold Time

t_SU,STOSet-up Time from Clock High to Stop

4

t_BUF

Start Set-up Time Following a Stop

Start Hold Time

4.7

4

t_HD,STA

t_SU,STA

Notes:

Start Set-up Time Following Clock Low to High

4.7

1. 100% tested at 25°C.

SDA

SCL

t

BUF

t

f

LOW

t

HD,STA

HD,DAT

HIGH

SU,DAT

r

SDA

t

SU,STA

SU,STO

Figure 3. I²C Bus Timing

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

7

2

I C Interface

Operation

Bit Transfer

The I²C-compatible interface conforms to the I²C spec-

ification for Standard Mode. Individual addresses may

be written. There is no read capability. The interface

consists of two lines. These is a serial data line (SDA)

and a serial clock line (SCL), both of which must be

connected to a positive supply through an external

resistor. Data transfer may be initiated only when the

bus is not busy.

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during

the HIGH period of the clock pulse. Changes in the line

during this time are interpreted as a control signal.

SCL

SDA

Data line

stable;

Change

of data

data valid

allowed

Figure 4. Bit Transfer

Start and Stop Conditions

The data and clock lines remain HIGH when the bus is

not busy. A HIGH-to-LOW transition of the data line,

while the clock is HIGH, is defined as START condition

(S). A LOW-to-HIGH transition of the data line, while

the clock is HIGH, is defined as STOP condition (P).

SCL

S

P

SDA

STOP condition

START condition

Figure 5. Definition of START and STOP conditions

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

8

Acknowledge

The data bytes transferred between the START and

STOP conditions from transmitter to receiver is unlim-

ited. Each byte of eight bits is followed by an acknowl-

edge bit. The acknowledge bit is a high-level signal put

on the bus by the transmitter, during which the master

generates an extra acknowledge-related clock pulse. A

slave receiver must generate an acknowledge after the

reception of each byte. A master receiver must generate

an acknowledge after the reception of each byte that has

been clocked out of the slave transmitter.

The device that acknowledges must pull down the SDA

line during the acknowledge clock pulse so the SDA line

is stable LOW during the HIGH period of the acknowl-

edge-related clock pulse (set-up and hold times must be

taken into consideration). A master receiver must signal

an end of data to the transmitter by not generating an

acknowledge on the last byte clocked out of the slave. In

this event, the transmitter must leave the data line HIGH

to enable the master to generate a STOP condition.

START

condition

clock pulse for

acknowledgement

SCL FROM

MASTER

1

2

8

9

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

Figure 6. Acknowledgement on the I²C Bus

2

I C Bus Protocol

Before any data is transmitted on the I²C bus, the device

that should respond is addressed first. The addressing is

always carried out with the first byte transmitted after the

start procedure. The I²C bus configuration for a data

write to the FMS6501 is shown in Figure 5.

1

9

1

9

SCL

SDA

A6

A5

A4

A3

A2

A1

A0 R/W

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

FMS6501

FRAME1

START BY

MASTER

FRAME 2

SERIAL BUS ADDRESS BYTE

ADDRESS POINTER REGISTER BYTE

9

1

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

FMS6501

STOP BY

MASTER

FRAME 3

DATA BYTE

Figure 7. Write a Register Address to the Pointer Register, Then Write Data to the Selected Register

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

9

Applications Information

Figure 9 shows the bias mode input circuit and internally

controlled voltage at the input pin for AC-coupled inputs.

Input Clamp / Bias Circuitry

The FMS6501 accommodates AC- or DC-coupled inputs.

Lowest voltage

set to 625mV

Internal clamping and bias circuitry are provided to sup-

port AC-coupled inputs. These are selectable through

the CLMP bits via the I²C compatible interface.

FMS6501

Input

Video source must

For DC-coupled inputs, the device should be pro-

grammed to use the 'bias' input configuration. In this con-

figuration, the input is internally biased to 625mV through

a 100kΩ resistor. Distortion is optimized with the output

levels set between 250mV above ground and 500mV

below the power supply. These constraints, along with

the desired channel gain, need to be considered when

configuring the input signal levels for input DC coupling.

Bias

0.1µF

be AC-coupled

75

Figure 9. Bias Mode Input Circuit

Output Configuration

With AC-coupled inputs, the FMS6501 uses a simple

clamp rather than a full DC-restore circuit. For video sig-

nals with and without sync (Y,CV,R,G,B), the lowest volt-

age at the output pins is clamped to approximately

300mV above ground when the 6dB gain setting is

selected.

The FMS6501 outputs may be either AC or DC coupled.

Resistive output loads can be as low as 75Ω, represent-

ing a dual, doubly terminated video load. High imped-

ance, capacitive loads up to 20pF can also be driven

without loss of signal integrity. For standard 75Ω video

loads, a 75Ω matching resistor should be placed in

series to allow for a doubly terminated load. DC-coupled

outputs should be connected as shown in Figure 10.

If symmetric AC-coupled input signals are used

(chroma,Pb,Pr,Cb,Cr), the bias circuit described above

can be used to center them within the input common

range. The average DC value at the output is approxi-

mately 1.27V with a 6dB gain setting. This value

changes depending upon the selected gain setting.

75

FMS6501

Output

Amplifier

75

Gain Setting Clamp Voltage Bias Voltage

6dB

7dB

8dB

9dB

300mV

330mV

370mV

420mV

1.27V

1.43V

1.60V

1.80V

Figure 10. DC-Coupled Load Connection

If multiple low-impedance loads are DC coupled,

increased power and thermal issues need to be

addressed. In this case, the use of a multilayer board

with a large ground plane to help dissipate heat is rec-

ommended. If a two-layer board is used under these

conditions, an extended ground plane directly under the

device is recommended. This plane should extend at

least 0.5 inches beyond the device. PC board layout

issues are covered in the Layout Considerations section.

Figure 8 shows the clamp mode input circuit and the

internally controlled voltage at the input pin for AC-cou-

pled inputs.

Lowest voltage

set to 125mV

FMS6501

Input

Clamp

Video source must

be AC-coupled

0.1µF

75

AC-coupled loads should be configured as in Figure 11:

220µF

75

FMS6501

Output

Figure 8. Clamp Mode Input Circuit

75

Amplifier

Figure 11. AC-Coupled Load Connection

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

10

Thermal issues are significantly reduced with AC-cou-

pled outputs, alleviating special PC layout requirements.

For input crosstalk, the switch is open. All inputs are in

bias mode. Channel 1 input is driven with a 1V_ppsignal,

while all other inputs are AC terminated with 75Ω. All out-

puts are enabled and crosstalk is measured from IN1 to

any output.

Each of the outputs can be independently powered down

and placed in a high-impedance state with the ENABLE

bit. This function can be used to mute video signals, to

parallel multiple FMS6501 outputs, or to save power.

When the output amplifier is disabled, the high-imped-

ance output presents a 3kΩ load to ground. The output

amplifier typically enters and recovers from the power-

down state in less than 300ns after being programmed.

For output crosstalk, the switch is closed. Crosstalk from

OUT1 to any output is measured.

Crosstalk from multiple sources into a given channel was

measured with the setup shown in Figure 6. Input IN1 is

driven with a 1V_pppulse source and is connected to out-

puts Out1 to Out8. Input In9 is driven with a secondary,

asynchronous, gray-field video signal, and is connected

to Out9. All other inputs are AC terminated with 75Ω.

Crosstalk effects on the gray field are measured and cal-

culated with respect to a standard 1V_ppoutput measured

at the load.

When an output channel is not connected to an input, the

input to that channel’s amplifier is forced to approxi-

mately 150mV. The output amplifier is still active unless

specifically disabled by the I²C interface. Voltage output

levels depend on the programmed gain for that channel.

Crosstalk

If not all inputs and outputs are needed, avoid using

adjacent channels, where possible, to reduce crosstalk.

Disable all unused channels to further reduce crosstalk

and power dissipation.

Crosstalk is an important consideration when using the

FMS6501. Input and output crosstalk are defined to rep-

resent the two major coupling modes in a typical applica-

tion. Input crosstalk is crosstalk in the input pins and

switches when the interfering signal drives an open

switch. It is dominated by inductive coupling in the pack-

age lead frame between adjacent leads. It decreases

rapidly as the interfering signal moves farther away from

the pin adjacent to the input signal selected. Output

crosstalk is coupling from one driven output to another

active output. It decreases with increasing load imped-

ance, as it is caused mainly by ground and power cou-

pling between output amplifiers. If a signal is driving an

open switch, its crosstalk is mainly input crosstalk. If it is

driving a load through an active output, its crosstalk is

mainly output crosstalk.

TERMINATION

Bias

IN1

IN1 driven with

SD videio 1Vpp

IN9 driven with

asynchronous

SD video 1Vpp

IN2-8 + IN10-12

driven with

AC term to GND

with 75

IN9

Bias

Input and output crosstalk measurements are performed

with the test configuration shown in Figure 12.

IN12

Bias

TERMINATION

Bias

IN1

Gain = 6dB

OUT1 = 2.0Vpp

Measure crosstalk from

Channels 1-8 into Channel 9

IN2 - IN12 are

OUT1

OUT9

AC-Term to

ground with

Figure 13. Test Configuration for Multi-Channel

Crosstalk

75

IN1 = 1Vpp

Open switch

for input

crosstalk

Close switch

for output

crosstalk

IN12

Bias

Gain = 6dB

OUT1 = 2.0Vpp

Input crosstalk from IN1

to OUTx

Output crosstalk from

OUT1 to OUTx

OUT1

OUT9

Figure 12. Test Configuration for Crosstalk

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

11

Layout Considerations

General layout and supply bypassing play major roles in

high-frequency performance and thermal characteristics.

Fairchild offers a demonstration board, FMS6501DEMO,

to use as a guide for layout and to aid in device testing

and characterization. The FMS6501DEMO is a 4-layer

board with a full power and ground plane. For optimum

results, follow the steps below as a basis for high fre-

quency layout.

FMS6501 Video Switch Matrix Applications

The increased demand for consumer multimedia sys-

tems has created a challenge for system designers to

provide cost-effective solutions to capitalize on the

growth potential in graphics display technologies. These

applications requires cost-effective video switching and

filtering solutions to deploy high-quality display technolo-

gies rapidly and effectively to the target audience. Areas

of specific interest include HDTV, media centers, and

automotive “infotainment” (includes navigation, in-cabin

entertainment, and back-up camera). In all cases, the

advantages an integrated video switch matrix provides

are high quality video switching specific to the applica-

tion, as well as video input clamps and on-chip, low-

impedance output cable drivers with switchable gain.

■ Include 10µF and 0.1µF bypass capacitors.

■ Place the 10µF capacitor within 0.75 inches of the

power pin.

■ Place the 0.1µF capacitor within 0.1 inches of the

power pin.

■ Connect all external ground pins as tightly as possible,

preferably with a large ground plane under the

package.

Generally the largest application for a video switch is for

the front end of an HDTV, where it takes multiple inputs

and routes them to appropriate signal paths (main pic-

ture and picture in picture - PiP). These are normally

routed into ADCs followed by decoders. There are many

different technologies for HDTV; including LCD, Plasma,

and CRT, with similar analog switching circuitry.

■ Layout channel connections to reduce mutual trace

inductance.

■ Minimize all trace lengths to reduce series induc-

tances. If routing across a board, place device such

that longer traces are at the inputs rather than the

outputs.

An example of a HDTV application is shown in Figure 14.

This system combines a video switch matrix and two

three-channel switchable anti-aliasing filters. There are

two three-channel signal paths in the system; one for the

main picture, the other for “Picture in Picture” (PiP).

If using multiple, low-impedance, DC-coupled outputs,

special layout techniques may be employed to help dissi-

pate heat.

If a multilayer board is used, a large ground plane

directly under the device helps reduce package case

temperature.

TM

VIPDEMO Control Software

The FMS6501 is configured via an I²C-compatible digital

interface. To facilitate demonstration, Fairchild Semicon-

ductor had developed the VIPDEMO^TMGUI-based con-

trol software to write to the FMS6501 register map. This

software is included in the FMS6501DEMO kit. Also

included is a parallel port I²C adapter and an interface

cable to connect to the demo board. Besides using the

full FMS6501 interface, the VIPDEMO^TMcan also be

used to control single-register read and writes for I²C.

For dual-layer boards, an extended plane can be used.

Worst-case, additional die power due to DC loading can

be estimated at (V_cc²/4R_load) per output channel. This

assumes a constant DC output voltage of V_cc/2. For 5V

V_ccwith a dual-DC video load, add 25/(4*75) = 83mW,

per channel.

Figure 14. HDTV Application using the FMS6501 Video Switch Matrix

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

12

Physical Dimensions

Dimensions are in millimeters unless otherwise noted.

SSOP-28

Figure 15. FMS6501 28-Lead Small Scale Outline Package (SSOP)

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

13

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

14

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型号：	FMS6501MSA28X
厂家：	ONSEMI
描述：	12 Input, 9 Output Video Switch Matrix 光电二极管
文件：	总16页 (文件大小：428K)
中文：	中文翻译
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