FMS6146MTC14X [ONSEMI]
视频滤波器驱动器,六沟道,4 阶标清;型号: | FMS6146MTC14X |
厂家: | ONSEMI |
描述: | 视频滤波器驱动器,六沟道,4 阶标清 PC 驱动 光电二极管 商用集成电路 驱动器 |
文件: | 总13页 (文件大小:885K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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October 2009
FMS6146
Low-Cost Six-Channel 4th-Order
Standard Definition Video Filter Driver
Features
Description
■ Six 4th-Order 8MHz (SD) Filters
■ Drives Single,AC- or DC-Coupled, Video Loads (2Vpp, 150Ω)
■ Drives Dual,AC- or DC-Coupled, Video Loads (2Vpp, 75Ω)
■ Transparent Input Clamping
The FMS6146 Low-Cost Video Filter (LCVF) is intended
to replace passive LC filters and drivers with a low-cost
integrated device. Six 4th-order filters provide improved
image quality compared to typical 2nd or 3rd-order
passive solutions.
■ AC- or DC-Coupled Inputs
The FMS6146 may be directly driven by a DC-coupled
DAC output or an AC-coupled signal. Internal diode
clamps and bias circuitry may be used if AC-coupled
inputs are required (see theApplications section for details).
■ AC- or DC-Coupled Outputs
■ DC-Coupled Outputs EliminateAC-Coupling Capacitors
■ 5V Only
■ Robust 8kV ESD Protection
The outputs can driveAC- or DC-coupled single (150Ω) or
dual (75Ω) loads. DC coupling the outputs removes the
need for output coupling capacitors. The input DC levels
are offset approximately +280mV at the output (see the
Applications section for details).
■ Lead-free TSSOP-14 Package
Applications
■ Cable Set-Top Boxes
■ Satellite Set-Top Boxes
■ DVD Players
■ HDTV
■ Personal Video Recorders (PVR)
■ Video On Demand (VOD)
Functional Block Diagram
IN1
IN2
IN3
Transparent Clamp
Transparent Clamp
Transparent Clamp
6dB
6dB
6dB
OUT1
OUT2
OUT3
Transparent Clamp
Transparent Clamp
Transparent Clamp
6dB
6dB
6dB
IN4
IN5
IN6
OUT4
OUT5
OUT6
th
8MHz, 4 order
Ordering Information
Operating
Temperature Range
Part Number
Eco Status
Package
Packaging Method
FMS6146MTC14X
-40°C to +85°C
RoHS
TSSOP-14
Tape and Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
Pin Configuration
OUT1
OUT2
1
2
3
4
5
6
7
14
13
12
11
10
9
IN1
IN2
IN3
FMS6146
14-pin
TSSOP
OUT3
GND
V
CC
IN4
OUT4
OUT5
OUT6
IN5
IN6
8
Pin Assignments
Pin# Pin Name Type
Description
1
2
IN1
IN2
Input
Input
Video input, Channel 1
Video input, Channel 2
Video input, Channel 3
+5V supply, do not float
Video input, Channel 4
Video input, Channel 5
Video input, Channel 6
3
IN3
Input
4
VCC
Input
5
IN4
Input
6
IN5
Input
7
IN6
Input
8
OUT6
OUT5
OUT4
GND
OUT3
OUT2
OUT1
Output
Output
Output
Output
Output
Output
Output
Filtered video output, Channel 6
Filtered video output, Channel 5
Filtered video output, Channel 4
Must be tied to ground, do not float
Filtered video output, Channel 3
Filtered video output, Channel 2
Filtered video output, Channel 1
9
10
11
12
13
14
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Parameter
Min.
-0.3
-0.3
Max.
6
Unit
V
DC Supply Voltage
Analog and Digital I/O
V
CC + 0.3
V
Output Channel - Any One Channel (Do Not Exceed)
50
mA
Reliability Information
Symbol
Parameter
Min.
Typ.
Max.
Unit
TJ
Junction Temperature
+150
°C
TSTG
TL
Storage Temperature Range
-65
+150
°C
Lead Temperature (Soldering, 10 seconds)
+300
°C
Thermal Resistance, JEDEC Standard
Multi-layer Test Boards, Still Air
ΘJA
90
°C/W
Electrostatic Discharge Information
Symbols
Parameter
Max.
Unit
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
4
2
ESD
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended ope-
rating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recom-
mend exceeding them or designing to absolute maximum ratings.
Parameter
Min.
-40
Typ.
Max.
+85
Unit
°C
Operating Temperature Range
CC Range
V
+4.75
+5.0
+5.25
V
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
3
DC Electrical Characteristics
TA = 25°C, VCC = 5V, RSOURCE = 37.5Ω; all inputs are AC coupled with 0.1μF; all outputs are AC coupled with 220μF into
150Ω loads; unless otherwise noted.
Symbol Parameter
Conditions
Min. Typ. Max. Units
ICC
VIN
Supply Current(1)
FMS6146 (No Load)
Referenced to GND if DC coupled
DC (All Channels)
35
1.4
-50
55
mA
Video Input Voltage Range
Power Supply Rejection
V
pp
dB
PSRR
Note:
1. 100% tested at 25°C.
AC Electrical Characteristics
TA = 25°C, VIN = 1V , VCC = 5V, RSOURCE = 37.5Ω; all inputs are AC coupled with 0.1μF; all outputs are AC coupled with
pp
220μF into 150Ω loads; unless otherwise noted.
Symbol Parameter
Conditions
All Channels
All Channels
All Channels
Min. Typ. Max. Units
AV
f1dB
fc
Channel Gain(1)
-1dB Bandwidth(1)
-3dB Bandwidth
6.0
4.5
6.2
6.8
7.8
48
6.4
dB
MHz
MHz
dB
fSB
Attenuation (Stopband Reject) All Channels at f = 27MHz
dG
dφ
Differential Gain
All Channels
All Channels
0.3
0.6
0.4
%
°
Differential Phase
THD
Output Distortion (All Channels) VOUT = 1.8V , 1MHz
pp
%
XTALK Crosstalk (Channel-to-Channel) at 1MHz
-60
dB
All Channels
NTC-7 Weighting: 100kHz to 4.2MHz
SNR
Signal-to-Noise Ratio
Propagation Delay
75
59
dB
ns
t
Delay from Input-to-Output, 4.5MHz
pd
Note:
1. 100% tested at 25°C.
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
4
Typical Performance Characteristics
TA = 25°C, VCC = 5V, RSOURCE = 37.5Ω; all inputs AC coupled with 0.1μF; all outputs are AC coupled with 220μF into 150Ω
loads; unless otherwise noted.
5
0
40
30
20
10
0
2
-5
1
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
1
-10
Mkr Frequency
Gain
-20
-30
Ref 400kHz
6dB
1
2
3
6.83MHz
7.84MHz
27MHz
-1dB BW
-3dB BW
-47.57dB
-40
-50
1 = 8.2MHz (16.02ns)
3
400kHz
5
10
15
20
25
30
400kHz
5
10
15
20
25
30
Frequency (MHz)
Frequency (MHz)
Figure 1. Frequency Response
Figure 2. Group Delay vs. Frequency
-60
0.2
NTSC
0.1
0
-70
-80
-0.1
-0.2
-0.3
-0.4
-0.5
-90
-100
-110
-120
-130
Min = -0.24
Max = 0.02
ppMax = 0.26
400kHz
1
2
3
4
5
6
1st
2nd
3rd
4th
5th
6th
Frequency (MHz)
Figure 3. Noise vs. Frequency
Figure 4. Differential Gain
1.0
0.8
NTSC
0.6
0.4
0.2
0
Min = 0.00
Max = 0.64
ppMax = 0.64
-0.2
-0.4
1st
2nd
3rd
4th
5th
6th
Figure 5. Differential Phase
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
5
Typical Application Diagrams
The following circuit may be used for direct DC-coupled drive by DACs with an output voltage range of 0V to 1.4V.
AC-coupled or DC-coupled outputs may be used with AC-coupled outputs, offering slightly lower power dissipation.
+5V
DVD Player or STB
0.1
μF
1.0
μF
220μF
220μF
220μF
75Ω Video Cables
R
G
B
75Ω
75Ω
75Ω
1
2
14
13
12
11
10
9
R
IN1
IN2
IN3
VCC
IN4
IN5
IN6
OUT1
OUT2
OUT3
GND
OUT
75Ω
75Ω
75Ω
G
OUT
OUT
FMS6146
14L TSSOP
3
4
5
6
7
B
Video
SoC
220μF
220μF
220μF
75Ω Video Cables
Y
75Ω
75Ω
75Ω
Y
OUT4
OUT5
OUT6
OUT
OUT
OUT
75Ω
75Ω
75Ω
C
C
CV
8
CV
DAC Load Resistors
per SoC specs.
AC-Coupling Caps
are Optional.
Figure 6. Typical Application Diagram
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
6
Application Information
Video Cables
Application Circuits
75Ω
75Ω
LOAD2
(optional)
The FMS6146 Low Cost Video Filter (LCVF) provides
6dB gain from input to output. In addition, the input is
slightly offset to optimize the output driver performance.
The offset is held to the minimum required value to
decrease the standing DC current into the load. Typical
voltage levels are shown in the diagram below:
75Ω
75Ω
0.65V
Y
LOAD1
Driver
IN
Y
OUT
Video Cables
1.0 -> 1.02V
0.65 -> 0.67V
0.3 -> 0.32V
Figure 8. Input Clamp Circuit
I/O Configurations
For a DC-coupled DAC drive with DC-coupled outputs,
0.0 -> 0.02V
V
IN
use the configuration shown in Figure 9.
2.28V
1.58V
Driven by:
0V - 1.4V
DC-Coupled DAC Outputs
AC-Coupled and Clamped
Y, CV, R, G, B
DVD or
STB
LCVF
Clamp
Inactive
75Ω
0.88V
0.28V
SoC
V
OUT
DAC
Output
There is a 280mV offset from the DC input level to the
DC output level. V
= 2 * V + 280mV.
IN
OUT
0.85V
0.5V
Figure 9. DC-Coupled Inputs and Outputs
Alternatively, if the DAC’s average DC output level causes
the signal to exceed the range of 0V to 1.4V, it can be AC
coupled as shown in Figure 10.
0.15V
V
IN
0V - 1.4V
0.1μ
1.98V
1.28V
0.58V
Driven by:
AC-Coupled and Biased
U, V, Pb, Pr, C
DVD or
STB
LCVF
Clamp
Active
75Ω
SoC
DAC
Output
V
OUT
Figure 7. Typical Voltage Levels
The FMS6146 provides an internal diode clamp to sup-
port AC-coupled input signals. If the input signal does not
go below ground, the input clamp does not operate. This
allows DAC outputs to directly drive the FMS6146 without
an AC coupling capacitor. When the input is AC coupled,
the diode clamp sets the sync tip (or lowest voltage) just
below ground. The worst-case sync tip compression due
to the clamp cannot exceed 7mV. The input level set by
the clamp, combined with the internal DC offset, keeps
the output within its acceptable range.
Figure 10. AC-Coupled Inputs,
DC-Coupled Outputs
When the FMS6146 is driven by an unknown external
source or a SCART switch with its own clamping circuitry,
the inputs should be AC coupled as shown in Figure 11.
0V - 1.4V
0.1μ
LCVF
Clamp
Active
75Ω
External video
source must
be AC-coupled
For symmetric signals like Chroma, U, V, Pb, and Pr, the
average DC bias is fairly constant and the inputs can be
AC coupled with the addition of a pull-up resistor to set
the DC input voltage. DAC outputs can also drive these
same signals without theAC coupling capacitor. Aconceptual
illustration of the input clamp circuit is shown in Figure 8.
75Ω
Figure 11. SCART with DC-Coupled Outputs
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
7
The same method can be used for biased signals, with the External video
0V - 1.4V
source must
addition of a pull-up resistor to make sure the clamp never
operates. The internal pull-down resistance is 800kΩ
±20%, so the external resistance should be 7.5MΩ to set
the DC level to 500mV as shown in Figure 12.
0.1μ
220μ
be AC-Coupled
LCVF
Clamp
Active
75Ω
75Ω
External video
source must
7.5MΩ
0.1μ
be AC-coupled
LCVF
Bias
Input
75Ω
Figure 15. Biased SCART with
AC-Coupled Outputs
75Ω
500mV +/-350mV
NOTE: The video tilt or line time distortion is dominated by
theAC-coupling capacitor. The value may need to be incre-
ased beyond 220μF to obtain satisfactory operation in
some applications.
Figure 12. Biased SCART with
DC-Coupled Outputs
Power Dissipation
The FMS6146 output drive configuration must be considered
when calculating overall power dissipation. Care must be
taken not to exceed the maximum die junction temperature.
The following example can be used to calculate the
FMS6146’s power dissipation and internal temperature rise.
The same circuits can be used with AC-coupled outputs if
desired.
0V - 1.4V
0.1μ
220μ
DVD or
STB
LCVF
Clamp
Active
75Ω
Tj = TA + Pd • θJA
EQ. 1
EQ. 2
EQ. 3
EQ. 4
EQ. 5
SoC
DAC
Output
where: Pd = PCH1 + PCH2 + PCH3 and
PCHx = VCC • ICH - (VO2/RL)
where: VO = 2VIN + 0.280V
ICH = (ICC/3) + (VO/RL)
VIN = RMS value of input signal
ICC = 35mA
Figure 13. DC-Coupled Inputs,
AC-Coupled Outputs
VCC = 5V
0V - 1.4V
RL = channel load resistance
0.1μ
220μ
DVD or
STB
LCVF
Clamp
Active
75Ω
Board layout can also affect thermal characteristics. Refer
to Layout Considerations for more information.
SoC
DAC
Output
The FMS6146 is specified to operate with output currents
typically less than 50mA, more than sufficient for a dual
(75Ω) video load. Internal amplifiers are current limited to a
maximum of 100mA and should withstand brief-duration
short-circuit conditions; this capability is not guaranteed.
Figure 14. AC-Coupled Inputs and Outputs
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
8
Layout Considerations
Output Considerations
The FMS6146 outputs are DC offset from the input by
150mV. Therefore, VOUT = 2•VIN DC+150mV. This offset is
required to obtain optimal performance from the output dri-
ver and is held at the minimum value to decrease the stan-
ding DC current into the load. Since the FMS6146 has a 2x
(6dB) gain, the output is typically connected via a 75ꢀ-
series back-matching resistor, followed by the 75ꢀ video
cable. Due to the inherent divide by two of this configurati-
on, the blanking level at the load of the video signal is
always less than 1V. When AC-coupling the output, ensure
that the coupling capacitor of choice passes the lowest
frequency content in the video signal and that line time dis-
tortion (video tilt) is kept as low as possible.
General layout and supply bypassing play major roles in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6146DEMO,
to guide layout and aid device testing and characterizati-
on. The FMS6146DEMO is a four-layer board with full
power and ground planes. Following this layout configu-
ration provides the optimum performance and thermal
characteristics. For optimum results, follow the guidelines
below as a basis for high-frequency layout:
■ Include 1μF and 0.1μF ceramic bypass capacitors.
■ Place the 1μF capacitor within 0.75 inches of the
The selection of the coupling capacitor is a function of the
subsequent circuit input impedance and the leakage cur-
rent of the input being driven. To obtain the highest quality
output video signal, the series termination resistor must be
placed as close to the output pin as possible. This reduces
the parasitic capacitance and inductance effect on the out-
put driver. The distance from the device pin to the series
termination resistor should be no greater than 0.1 inches.
power pin.
■ Place the 0.1μF capacitor within 0.1 inches of the
power pin.
■ For multi-layer boards, use a large ground plane to help
dissipate heat.
■ For two-layer boards, use a ground plane that extends
beyond the device by at least 0.5 inches.
■ Minimize all trace lengths to reduce series inductances.
Figure 16. Distance from Device Pin to Series
Termination Resistor
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
9
Physical Dimensions
0.43 TYP
0.65
1.65
6.10
0.45
12.00°TO P & BOTTOM
R0.09 m in
A. CO NFO RM S TO JEDEC REG ISTRATIO N M O -153,
VARIATION AB, REF NOTE 6
B. DIM ENSIO NS ARE IN M ILLIM ETERS
R0.09m in
1.00
C. DIM ENSIO NS ARE EXCLUSIVE O F BURRS, M O LD FLASH,
AND TIE BAR EXTRUSIO NS
D. DIM ENSIO NING AND TOLERANCES PER ANSI
Y14.5M , 1982
E. LANDPATTERN STANDARD: SO P65P640X110-14M
F. DRAW ING FILE NAM E: M TC14REV6
Figure 17. TSSOP-14 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in
any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s
worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
10
© 2006 Fairchild Semiconductor Corporation
FMS6146 • Rev. 1.1.0
www.fairchildsemi.com
11
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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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