FL3100T [ONSEMI]
Low-Side Gate Driver with LED PWM Dimming Control;
| 型号： | FL3100T |
| 厂家： | 
ONSEMI |
| 描述： | Low-Side Gate Driver with LED PWM Dimming Control 栅 |
| 文件： | 总18页 (文件大小：1007K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 2015
FL3100T
Low-Side Gate Driver with LED PWM Dimming Control
for Smart LED Lighting
Features
Description
The FL3100T 2 A gate driver is designed to drive an N-
channel enhancement-mode MOSFET in low-side
switching applications by providing high peak current
pulses during the short switching intervals. The
FL3100T has two inputs that can be configured to
operate in non-inverting (IN) mode with a DIM pin for
PWM dimming control of the LED Driver. High accuracy
PWM dimming control required in smart LED drivers is
possible by adjusting the duty ratio of the DIM input. If
one or both inputs are left unconnected, internal
resistors bias the inputs such that the output is pulled
LOW to hold the power MOSFET off.
.
Non-inverting Input Logic with DIM Control Input for
PWM Dimming Down to 0.1% for Hybrid Dimming
.
.
.
.
.
4.5 to 18 V Operating Range
TTL Inputs Independent of Supply Voltage
2.5 A Sink / 1.8 A Source at VOUT = 6 V
Internal Resistors Turn Driver Off If No Inputs
13 ns Typical Rise Time and 9 ns Typical Fall-Time
with 1 nF Load
.
.
MillerDrive™ Technology
The driver is available with fixed TTL input thresholds.
Internal circuitry provides an under-voltage lockout
function by holding the output LOW until the supply
voltage is within operating range. The FL3100T delivers
fast MOSFET switching performance, which helps
maximize efficiency in high-frequency LED driver
designs.
Typical Propagation Delay Time Under 20 ns with
Input Falling or Rising
.
.
6-Lead, 2 x 2 mm MLP or 5-Pin, SOT23 Packages
Rated from -40°C to 125°C Ambient
Applications
The FL3100T is available in a 5-pin, SOT23 or a
2 x 2 mm, 6-lead, Molded Leadless Package (MLP) for
the smallest size with excellent thermal performance.
.
.
Smart LED Drivers with Accurate PWM Dimming
General LED Lighting
Typical Application Circuit
ILED
VDD
FL3100T
IN
OUT
MCU
DIM
Figure 1. LED PWM Dimming Application Circuit for Smart LED Lighting
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
Ordering Information
Part Number
FL3100TMPX
FL3100TSX
Package
6-Lead, 2 x 2 mm MLP
5-Pin, SOT23
Packing Method
Tape & Reel
Quantity / Reel
3000
Tape & Reel
3000
Block Diagrams
1
VDD
UVLO
VDD_OK
100k
IN
3
5
OUT
100k
100k
4
DIM
2
GND
Figure 2. Simplified Block Diagram (SOT23 Pin-out)
3
VDD
UVLO
100k
VDD_OK
IN
1
4
OUT
100k
100k
6
2
DIM
AGND
5
PGND
0.4
Figure 3.
Simplified Block Diagram (MLP Pin-out)
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
2
Functional Pin Configurations
VDD
GND
IN
5
4
1
2
3
OUT
DIM
IN
6
5
4
1
2
3
DIM
AGND
VDD
PGND
OUT
Figure 4. 6-Lead MLP (Top View)
Figure 5.
SOT23-5 (Top View)
Pin Definitions
SOT23 MLP
Pin # Pin #
Name
Pin Description
1
3
2
VDD
Supply Voltage. Provides power to the IC.
AGND Analog ground for input signals (MLP only). Connect to PGND underneath the IC.
GND Ground (SOT-23 only). Common ground reference for input and output circuits.
2
3
Input. Non-inverting logic. If IN is not used, connect to VDD to enable regular operation
of the output.
1
6
IN
Dimming Input. Used for PWM dimming. Inverting logic. If dimming is not used, connect
to AGND or PGND to enable regular operation of the output.
4
5
DIM
Gate Drive Output: Held low unless required inputs are present and VDD is above UVLO
threshold.
4
OUT
Thermal Pad (MLP only). Exposed metal on the bottom of the package, which is
electrically connected to pin 5.
Pad
5
P1
Power Ground (MLP only). For output drive circuit; separates switching noise from
PGND
inputs.
Output Logic
IN
DIM
0
OUT
0(1)
0(1)
1
0
0
1
0
1(1)
0
1
1(1)
Note:
1. Default input signal if no external connection is made.
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
3
Thermal Characteristics(2)
(3)
(4)
JT
(5)
JA
Package
Unit
JL
6-Lead, 2 x 2 mm Molded Leadless Package (MLP)
2.7
56
133.0
99
58.0
157
°C/W
°C/W
SOT23-5
Notes:
2. Estimates derived from thermal simulation; actual values depend on the application.
3. Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
4. Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
5. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
and airflow. The value given is for natural convection with no heatsink using a 2SP2 board, as specified in
JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDD
Parameter
Min.
Max.
Unit
V
VDD to PGND
-0.3
20.0
VIN
Voltage on IN and DIM to GND, AGND, or PGND
Voltage on OUT to GND, AGND, or PGND
Lead Soldering Temperature (10 Seconds)
Junction Temperature
GND - 0.3 VDD + 0.3
GND - 0.3 VDD + 0.3
+260
V
VOUT
TL
V
ºC
ºC
ºC
TJ
-55
-65
+150
+150
TSTG
Storage Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VDD
Parameter
Min.
4.5
0
Max.
18.0
VDD
Unit
V
Supply Voltage Range
Input Voltage IN, DIM
VIN
V
TA
Operating Ambient Temperature
-40
+125
ºC
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
4
Electrical Characteristics
Unless otherwise noted, VDD = 12 V, TJ = -40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Supply
VDD
Parameter
Conditions
Min. Typ. Max. Unit
Operating Range
4.5
18.0
0.80
V
Supply Current Inputs/
EN Not Connected
IDD
0.50
mA
VON
VOFF
Turn-On Voltage
Turn-Off Voltage
3.5
3.3
3.9
3.7
4.3
4.1
V
V
Inputs
VINL_T
VINH_T
IIN
IN, DIM Logic LOW Voltage, Maximum
IN, DIM Logic HIGH Voltage, Minimum
Non-inverting Input
0.8
V
V
2.0
175
1
IN from 0 to VDD
-1
µA
µA
V
IDIMim
VHYS
DIM Input
IN from 0 to VDD
-175
0.2
IN, DIM Logic Hysteresis Voltage
0.4
0.8
Output
OUT at VDD/2,
CLOAD = 0.1 µF, f = 1 kHz
ISINK
OUT Current, Mid-Voltage, Sinking(6)
2.5
A
A
OUT at VDD/2,
CLOAD = 0.1 µF, f = 1 kHz
ISOURCE
IPK_SINK
OUT Current, Mid-Voltage, Sourcing(6)
OUT Current, Peak, Sinking(6)
-1.8
CLOAD = 0.1 µF, f = 1 kHz
CLOAD = 0.1 µF, f = 1 kHz
CLOAD = 1000 pF
3
-3
A
A
IPK_SOURCE OUT Current, Peak, Sourcing(6)
tRISE
tFALL
tD1, tD2
IRVS
Notes:
Output Rise Time(7)
13
9
20
14
30
ns
ns
ns
mA
Output Fall Time(7)
CLOAD = 1000 pF
Output Prop. Delay, TTL Inputs(7)
Output Reverse Current Withstand(6)
0 – 5 VIN; 1 V/ns Slew Rate
9
16
500
6. Not tested in production.
7. See Timing Diagrams of Figure 6 and Figure 7.
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
5
Timing Diagrams
90%
90%
Output
Output
10%
10%
VINH
Input
VINL
VINH
VINL
PWM
tD1
tD2
tD1
tD2
tRISE
tFALL
tFALL
tRISE
Figure 6.
IN Pin
Figure 7. DIM Pin
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
6
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 8. IDD (Static) vs. Supply Voltage
Figure 9. IDD (No-Load) vs. Frequency
1 nF Load
Figure 10. IDD (1 nF Load) vs. Frequency
Figure 11. IDD (Static) vs. Temperature
Figure 12. Input Thresholds vs. Supply Voltage
Figure 13. TTL Input Thresholds vs. Temperature
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
7
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 14. UVLO Thresholds vs. Temperature
Figure 15. UVLO Hysteresis vs. Temperature
Non-Inverting Input
Figure 16. Propagation Delay vs. Supply Voltage
Inverting Input
Figure 17. Propagation Delay vs. Temperature
Figure 18. Propagation Delay vs. Temperature
Figure 19. Fall Time vs. Supply Voltage
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
8
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 20. Rise Time vs. Supply Voltage
Figure 21. Rise and Fall Time vs. Temperature
Figure 22. Rise / Fall Waveforms with 1 nF Load
Figure 23. Rise / Fall Waveforms with 10 nF Load
Figure 24. Quasi-Static Source Current with VDD=12 V
Figure 25. Quasi-Static Sink Current with VDD=12 V
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
9
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 26. Quasi-Static Source Current with VDD=8 V
Figure 27. Quasi-Static Sink Current with VDD=8 V
VDD
470µF
Al. El.
4.7µF
ceramic
Current Probe
LECROY AP015
IOUT
IN
1kHz
1µF
ceramic
CLOAD
0.1µF
VOUT
Figure 28. Quasi-Static IOUT / VOUT Test Circuit
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
10
Applications Information
PWM Dimming
0%
50%
90%
DIM
Duty
(%)
FL3100T is used for pulse-width modulation of the LED
current to control the amount of light produced by the
LED in MCU-driven hybrid dimming applications.
t
There are two factors to consider, PWMamplitude controls
the LED light output by reducing the forward current in
the LED and PWMlight controls the on time of forward
current in the LED.
IN
t
t
OUT
In the typical application circuit, Figure 1 and repeated
here Figure 29, IN is connected to the PWMamplitude
signal coming out of the MCU to control the amplitude of
the overall LED current. This PWMamplitude signal from
the MCU is the same PWM signal based on the
switching frequency of the power stage and error signal
in a closed loop LED driver stage.
100%
ILED
10%
50%
t
Figure 30.
LED Current with PWM Dimming
DIM is connected to a different PWM signal, also from
the MCU, but is usually a lower frequency signal to
command the PWMlight dimming on the LED current, i.e.
~1 kHz and can be commanded from a wired or wireless
interface such as DALI or ZigBee. Therefore, mixed
mode dimming using both amplitude and PWM dimming
on the LED current is possible.
Input Thresholds
In the FL3100T, the input thresholds meet industry-
standard TTL logic thresholds, independent of the VDD
voltage, and there is
a
hysteresis voltage of
approximately 0.4 V. These levels permit the inputs to
be driven from a range of input logic signal levels for
which a voltage over 2 V is considered logic HIGH. The
driving signal for the TTL inputs should have fast rising
and falling edges with a slew rate of 6 V/µs or faster, so
the rise time from 0 to 3.3 V should be 550 ns or less.
With reduced slew rate, circuit noise could cause the
driver input voltage to exceed the hysteresis voltage and
retrigger the driver input, causing erratic operation.
ILED
VDD
Static Supply Current
FL3100T
IN
In the IDD (static) typical performance graphs (Figure 8,
and Figure 11), the curve is produced with all inputs
floating (OUT is LOW) and indicates the lowest static IDD
current for the tested configuration. For other states,
additional current flows through the 100 k resistors on
the inputs and outputs shown in the block diagrams (see
Figure 2 - Figure 3). In these cases, the actual static IDD
current is the value obtained from the curves plus this
additional current.
OUT
MCU
DIM
Figure 29. LED PWM Dimming Application
Under-Voltage Lockout (UVLO)
During amplitude dimming (PWMamplitude), DIM stays low
and there is no PWMlight dimming. When PWMlight
dimming becomes active, e.g. below 20% of amplitude
(PWMamplitude) dimming, then amplitude dimming is held
constant and PWMlight dimming is used to reduce the
light output down to ~0.1% accurately. Figure 30 shows
a possible implementation for mixed mode dimming.
The FL3100T startup logic is optimized to drive ground
referenced N-channel MOSFETs with an Under-Voltage
Lockout (UVLO) function to ensure that the IC starts up
in an orderly fashion. When VDD is rising, yet below the
3.9 V operational level, this circuit holds the output
LOW, regardless of the status of the input pins. After the
part is active, the supply voltage must drop 0.2 V before
the part shuts down. This hysteresis helps prevent
chatter when low VDD supply voltages have noise from
the power switching. This configuration is not suitable
for driving high-side P-channel MOSFETs because the
low output voltage of the driver would turn the P-channel
MOSFET on with VDD below 3.9 V.
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
11
VDD Bypass Capacitor Guidelines
Layout and Connection Guidelines
To enable this IC to turn a power device on quickly, a
local, high-frequency, bypass capacitor CBYP with low
ESR and ESL should be connected between the VDD
and GND pins with minimal trace length. This capacitor
is in addition to bulk electrolytic capacitance of 10 µF to
47 µF often found on driver and controller bias circuits.
The FL3100T incorporates fast-reacting input circuits,
short propagation delays, and powerful output stages
capable of delivering current peaks over 2 A to facilitate
voltage transition times from under 10 ns to over 100 ns.
The following layout and connection guidelines are
strongly recommended:
.
Keep high-current output and power ground paths
separate from logic input signals and signal ground
paths. This is especially critical when dealing with
TTL-level logic thresholds.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply ≤5%. Often
this is achieved with a value ≥ 20 times the equivalent
load capacitance CEQV, defined here as Qgate/VDD
.
Ceramic capacitors of 0.1 µF to 1 µF or larger are
common choices, as are dielectrics, such as X5R and
X7R, which have good temperature characteristics and
high pulse current capability.
.
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and other
surrounding circuitry.
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV, or
CBYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10 nF, mounted
closest to the VDD and GND pins to carry the higher-
frequency components of the current pulses.
.
The FL3100T is available in two packages with
slightly different pinouts, offering similar
performance. In the 6-pin MLP package, Pin 2 is
internally connected to the input analog ground and
should be connected to power ground, Pin 5,
through a short direct path underneath the IC. In
the 5-pin SOT23, the internal analog and power
ground connections are made through separate,
individual bond wires to Pin 2, which should be
used as the common ground point for power and
control signals.
MillerDrive™ Gate Drive Technology
FL3100T drivers incorporate the MillerDrive™
architecture shown in Figure 31 for the output stage, a
combination of bipolar and MOS devices capable of
providing large currents over a wide range of supply
voltage and temperature variations. The bipolar devices
carry the bulk of the current as OUT swings between 1/3
to 2/3 VDD and the MOS devices pull the output to the
high or low rail.
.
.
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
triggering. These effects can be especially obvious
if the circuit is tested in breadboard or non-optimal
circuit layouts with long input, enable, or output
leads. For best results, make connections to all pins
as short and direct as possible.
The purpose of the MillerDrive™ architecture is to
speed up switching by providing the highest current
during the Miller plateau region when the gate-drain
capacitance of the MOSFET is being charged or
discharged as part of the turn-on / turn-off process.
The turn-on and turn-off current paths should be
minimized as discussed in the following sections.
The output pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
if a slower rise or fall time at the MOSFET gate is
needed, a series resistor can be added.
Figure 32 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local
bypass capacitor, CBYP, and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized CBYP acts
to contain the high peak current pulses within this driver-
MOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
VDD
Input
stage
VOUT
VDD
VDS
CBYP
FL3100T
PWM
Figure 31. MillerDrive™ Output Architecture
Figure 32.
Current Path for MOSFET Turn-On
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
12
Figure 33 shows the current path when the gate driver
turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
VDD
Turn-on
Threshold
DIM
IN
VDD
VDS
CBYP
FL3100T
OUT
PWM
Figure 34.
IN Startup Waveforms
Thermal Guidelines
Figure 33.
Current Path for MOSFET Turn-Off
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure that the part is operating within
acceptable temperature limits.
Table 1.
Truth Table of Logic Operation
The truth table indicates the operational states using the
IN and DIM pins.
IN
DIM
OUT
The total power dissipation in a gate driver is the sum of
two components; PGATE and PDYNAMIC:
0
0
1
1
0
1
0
1
0
0
1
0
PTOTAL = PGATE + PDYNAMIC
(1)
If the DIM pin is connected to logic HIGH, a disable
function is realized, and the driver output remains LOW
regardless of the state of the IN pin. Likewise, If the IN
pin is connected to logic LOW, a disable function is
realized, and the driver output remains LOW regardless
of the state of the DIM pin.
Operational Waveforms
At power up, the driver output remains LOW until the
VDD voltage reaches the turn-on threshold. The
magnitude of the OUT pulses rises with VDD until
steady-state VDD is reached. The non-inverting
operation illustrated in Figure 34 shows that the output
remains LOW until the UVLO threshold is reached, and
then the output is in-phase with the input.
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
13
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the
switching frequency. The power dissipation that results
from driving a MOSFET at a specified gate-source
voltage, VGS, with gate charge, QG, at switching
frequency, fSW, is determined by:
In a typical MOSFET gate drive application, the
FDS2672 would be a potential MOSFET selection. The
typical gate charge would be 32 nC with VGS = VDD =
10 V. Using a TTL input driver at a switching frequency
of 500 kHz, the total power dissipation can be calculated
as:
PGATE = 32 nC • 10 V • 500 kHz = 0.160 W
PDYNAMIC = 8 mA • 10 V = 0.080 W
PTOTAL = 0.24 W
(5)
(6)
(7)
PGATE = QG • VGS • fSW
(2)
Dynamic Pre-drive / Shoot-through Current: A power loss
resulting from internal current consumption under
dynamic operating conditions, including pin pull-up /
pull-down resistors, can be obtained using the IDD (no-
Load) vs. Frequency graphs in Typical Performance
Characteristics to determine the current IDYNAMIC drawn
from VDD under actual operating conditions:
The 5-pin SOT23 has
a junction-to-lead thermal
characterization parameter JB = 51°C/W.
In a system application, the localized temperature
around the device is a function of the layout and
construction of the PCB along with airflow across the
surfaces. To ensure reliable operation, the maximum
junction temperature of the device must be prevented
from exceeding the maximum rating of 150°C; with 80%
derating, TJ would be limited to 120°C. Rearranging
Equation (4) determines the board temperature required
to maintain the junction temperature below 120°C:
PDYNAMIC = IDYNAMIC • VDD
(3)
Once the power dissipated in the driver is determined,
the driver junction rise with respect to circuit board can
be evaluated using the following thermal equation,
JB
design (heat sinking and air flow):
assuming
was determined for a similar thermal
•
(8)
(9)
TB,MAX = TJ - PTOTAL
JB
(4)
TJ
= PTOTAL
•
JB + TB
where:
TJ
TB,MAX = 120°C – 0.24W • 51°C/W = 108°C
= driver junction temperature
For comparison purposes, replace the 5-pin SOT23
used in the previous example with the 6-pin MLP
JB
= (psi) thermal characterization parameter
relating temperature rise to total power
dissipation
JB
package with
= 2.8°C/W. The 6-pin MLP package
can operate at a PCB temperature of 119°C, while
maintaining the junction temperature below 120°C. This
illustrates that the physically smaller MLP package with
thermal pad offers a more conductive path to remove
the heat from the driver. Consider the tradeoffs between
reducing overall circuit size with junction temperature
reduction for increased reliability.
TB = board temperature in location defined in the
Thermal Characteristics table.
Typical Application Diagram
Boost
Isolated DC to DC
ILED
VDD
FL3100T
PWM
Controllers
IN
AC Input
OUT
DIM
MCU
(DC-DC
Control)
Communication
Chipset
Figure 35.
Smart LED Driver using the MCU and FL3100T in the Buck DC-DC Stage
© 2015 Fairchild Semiconductor Corporation
FL3100T • Rev.1.0
www.fairchildsemi.com
14
0.05 C
2.0
A
1.72
1.68
2X
B
4
6
0.15
1.21
2.0
0.90
2.25
0.52(6X)
0.05 C
1
3
PIN#1 IDENT
TOP VIEW
2X
0.42(6X)
0.65
RECOMMENDED
LAND PATTERN
ꢂꢁꢈꢃꢂꢁꢂꢃ
0.10 C
ꢂꢁꢀꢂꢂꢁꢂꢃ
NOTES:
0.08 C
SIDE VIEW
C
ꢂꢁꢂꢀꢃꢂꢁꢂꢀꢃ
SEATING
PLANE
A. PACKAGE DOES NOT FULLY CONFORM
TO JEDEC MO-229 REGISTRATION
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
ꢀꢁꢂꢂꢂꢁꢂꢃ
ꢄꢁꢅꢂꢂꢁꢂꢃ
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
(0.70)
PIN #1 IDENT
(0.20)4X
E. DRAWING FILENAME: MKT-MLP06Krev5.
1
3
(0.40)
ꢂꢁꢇꢀꢂꢁꢂꢃ
(6X)
ꢂꢁꢆꢂꢂꢁꢂꢃ
(0.60)
6
4
(6X)
ꢂꢁꢇꢂꢂꢁꢂꢃ
0.10
0.65
C A B
1.30
0.05
C
BOTTOM VIEW
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