FIN1022MTCX [ONSEMI]
2 X 2 LVDS 高速交点开关;
| 型号： | FIN1022MTCX |
| 厂家： | 
ONSEMI |
| 描述： | 2 X 2 LVDS 高速交点开关 开关 光电二极管 |
| 文件： | 总12页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
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September 2001
Revised December 2001
FIN1022
2 X 2 LVDS High Speed Crosspoint Switch
General Description
Features
This non-blocking 2x2 crosspoint switch has a fully differ-
ential input to output data path for low noise generation and
low pulse width distortion. The device can be used as a
high speed crosspoint switch, 2:1 multiplexer, 1:2 demulti-
plexer or 1:2 signal splitter. The inputs can directly interface
with LVDS and LVPECL levels.
■ Low jitter, 800 Mbps full differential data path
■ Worst case jitter of 190ps
with PRBS = 223 − 1 data pattern at 800 Mbps
■ Rail-to-rail common mode range is 0.5V to 3.25V
■ Worst case power dissipation is less than 126 mW
■ Open-circuit fail safe protection
■ Fast switch time of 1.1 ns typical
■ 35 ps typical pin channel to channel skew
■ 3.3V power supply operation
■ Non-blocking switch
■ LVDS receiver inputs accept LVPECL signals directly
■ 7.5 kV HBM ESD protection
■ 16-lead SOIC package and TSSOP package
■ Inter-operates with TIA/EIA 644-1995 specification
■ See the Fairchild Interface Solutions web page for cross
reference information:
www.fairchildsemi.com/products/interface/lvds.html
Ordering Code:
Order Number Package Number
Package Description
FIN1022M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
FIN1022MTC
MTC16
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS500653
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Name
Description
RIN0+, RIN1+
RIN0−, RIN1−
LVDS non-inverting data inputs
LVDS inverting data inputs
DOUT0+, DOUT1+ LVDS non-inverting data outputs
DOUT0−, DOUT1− LVDS inverting data outputs
EN0
EN1
SEL0
LVTTL input for enabling DOUT0+/DOUT0−
LVTTL input for enabling DOUT1+/DOUT1−
LVTTL input for selecting RIN0+/RIN0− or
RIN1+/RIN1− for output DOUT0+/DOUT0−
SEL1
LVTTL input for selecting RIN0+/RIN0− or
RIN1+/RIN1− for output DOUT1+/DOUT1−
VCC
Power Supply
Ground
GND
Function Table
Inputs
Outputs
Mode
SEL0
SEL1
EN0
EN1
DOUT0+ DOUT0− DOUT1+ DOUT1−
L / O
L / O
H
L / O
H
H
H
H
H
RIN0+
RIN0+
RIN1+
RIN1+
Z
RIN0−
RIN0−
RIN1−
RIN1−
Z
RIN0+
RIN1+
RIN0+
RIN1+
RIN0+
RIN1+
Z
RIN0− 1:2 Splitter
RIN1− Repeater
L / O
H
H
H
RIN0− Switch
H
H
H
RIN1− 1:2 Splitter
RIN0− DOUT0 Disabled
RIN1− DOUT0 Disabled
X
L / O
H
L / O
L / O
H
H
X
H
Z
Z
L / O
H
X
L / O
L / O
L / O
RIN0+
RIN1+
Z
RIN0−
RIN1−
Z
Z
Z
Z
DOUT1 Disabled
DOUT1 Disabled
X
H
Z
X
X
L / O
Z
DOUT0 and DOUT1 Disabled
O = OPEN
L / O = LOW or OPEN
H = HIGH Logic Level
L = LOW Logic Level
X = Don’t Care
Z = High Impedance
Function Diagrams
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Driver Short Circuit Current (IOSD
)
−0.3V to +4.6V
−0.3V to +4.6V
−0.3V to +4.6V
Continuous
)
Supply Voltage (VCC
Input Voltage (VIN
)
3.0V to 3.6V
0 to VCC
)
)
)
Operating Temperature (TA)
Electrostatic Discharge
(HBM 1.5 kΩ, 100 pF)
Electrostatic Discharge
(MM 0Ω, 100 pF)
−40°C to +85°C
Storage Temperature Range (TSTG
Max Junction Temperature (TJ)
Lead Temperature (TL)
)
−65°C to +150°C
150°C
>7500V
(Soldering, 10 seconds)
260°C
>300V
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified (Note 2)
Min
Typ
Max
Symbol
Parameter
Test Conditions
Units
(Note 3)
LVDS Differential Driver Characteristics
VOD
Output Differential Voltage
R
L = 75 Ω, See Figure 3
L = 75 Ω, See Figure 3
270
285
365
365
475
440
R
mV
TA = 25°C and VCC = 3.3V
∆VOD
VOD Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
R
L = 75 Ω, See Figure 3
35
1.45
35
mV
V
VOS
See Figure 3
See Figure 3
1.0
1.2
∆VOS
Offset Magnitude Change from
Differential LOW-to-HIGH
Disabled Output Leakage Current
Power-Off Current
mV
IOZD
IOFF
IOS
VOUT = 3.6V or GND, Driver Disabled
VCC = 0V, VIN or VOUT = 3.6V or 0V
VOUT = 0V, Driver Enabled
±10
±20
−10
−10
µA
µA
Short Circuit Output Current
mA
VOUTx+ = 0V, VOUTx− = 0V, Driver Enabled
LVDS Differential Receiver Characteristics
VTH
VTL
VIC
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Common Mode Voltage
Input Current (Differential Inputs)
V
IC = 0.05V or 1.2V or 3.25V
CC = 3.3V
100
mV
V
V
−100
0.05
3.25
±20
±20
IIND
V
IN = GND
IN = VCC
µA
V
LVTTL Control Characteristics
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
Input Current
2
V
V
0.8
VIN = 3.6V or GND
±20
µA
Device Characteristics
VIK
Input Clamp Voltage
I
IK = −18 mA
CC = 0V to 1.5V
−1.5
V
IPU/PD
Output Power-Up/Power-Down
High Z Leakage Current
Input Capacitance
V
±10
µA
CIN
4.5
4.5
pF
pF
COUT
ICC
Output Capacitance
Power Supply Current
No Load, All Drivers Enabled
35
35
35
mA
mA
mA
R
L = 75 Ω, All Drivers Enabled
L = 75 Ω, All Drivers Enabled
R
Note 2: This part will only function with datasheet specification when a resistive load is applied to the driver outputs.
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
3
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AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Min
Typ
Max
Symbol
Parameter
Test Conditions
Units
ns
(Note 4)
tPLHD
Differential Output Propagation Delay
LOW-to-HIGH
0.7
1.0
0.7
1.0
290
290
0.6
0.9
0.6
0.9
1.6
1.3
1.6
1.3
580
580
1.5
1.2
1.5
1.2
R
L = 75 Ω, CL = 5 pF,
CC = 3.3V, TA = 25°C
See Figure 4 and Figure 5
1.2
1.2
tPHLD
Differential Output Propagation Delay
HIGH-to-LOW
V
ns
tTLHD
tTHLD
tPLH
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
Selection Propagation Delay
LOW-to-HIGH (SELn to OUTn)
Selection Propagation Delay
HIGH-to-LOW (SELn to OUTn)
Differential Output Enable Time
from Z-to-HIGH
ps
ps
ns
ns
ns
ns
ns
ns
R
L = 75 Ω, CL = 5 pF,
CC = 3.3V, TA = 25°C
See Figure 6 and Figure 7
1.1
1.1
tPHL
tZHD
tZLD
tHZD
tLZD
V
3.5
3.5
3.5
3.5
Differential Output Enable Time
from Z-to-LOW
R
L = 75Ω, CL = 5 pF
Differential Output Disable Time
from HIGH-to-Z
See Figure 8 and Figure 9
Differential Output Disable Time
from LOW-to-Z
tSET
tHOLD
tJIT
Input (INn+/INn−) Setup Time to SELn
Input (INn+/INn−) Hold Time to SELn
Output Peak-to-Peak Jitter
See Figure 10
0.5
0.5
0.3
0.3
ns
ns
See Figure 10
223 −1 PRBS Sequence at 800 Mbps
190
35
ps
50% Duty Cycle at 800 Mbps
20
900
35
ps
fTOG
Maximum Toggle Frequency
RL = 75 Ω, CL = 5 pF, See Figure 4
800
Mbps
ps
tSKEW
Within Device Channel-to-Channel Skew
80
Pulse Skew |tPLHD -tPHLD
Part-to-Part Skew (Note 5)
Note 4: All typical values are at TA = 25°C and with VCC = 3.3V.
|
0
225
500
ps
100
ps
Note 5: Part-to-part skew is the maximum delay time difference on like edges (LOW-to-HIGH or HIGH-to-LOW) for the same VCC and temperature condi-
tions.
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4
Required Specifications
1. When the true and complement LVDS outputs (having
a 75Ω connected between outputs) are connected to
3.75 kΩ resistors and the common point of those 3.75
kΩ resistors are connected to a voltage source that
sweeps from 0 to 2.4V, the DC VOD and ∆VOD are still
3. Pull-down resistors are required on Enable (EN0 and
EN1) and select (SEL0 and SEL1) inputs.
4. Fail safe protection on the outputs that draw less than
20 µA of current (worst case) on the LVDS inputs. In
this condition, if the input is in fail safe selected to
OUT0+/OUT0− (say) and the outputs are Enabled then
maintained (see Figure 1).
2. When the true and complement LVDS outputs (having
a 5 pF capacitor attached between outputs) are con-
nected with 37.5Ω resistors each to common point,
then the common point does not vary by more than 150
mV under all process, temperature and voltage condi-
tions when the outputs switch either from LOW-to-
HIGH or from HIGH-to-LOW (see Figure 2).
OUT0+ = HIGH and OUT0− = LOW. This prevents noise
from being amplified when the connection is broken.
5. In the disabled state the outputs can go beyond VCC
but there should be no appreciable leakage (see IOZD
and IOFF specifications)
FIGURE 1. Common Mode Supply Test Circuit
FIGURE 2. Dynamic VOS Test Circuit and Waveforms
5
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Required Specifications (Continued)
Note A: All input pulses have frequency = 50 MHz, tR or tF = 500 ps
Note B: CL includes all probe and jig capacitances
FIGURE 4. LVDS Input to LVDS Driver Propagation
Delay and Transition Time Circuit
FIGURE 3. LVDS Driver DC Test Circuit
FIGURE 5. LVDS Input to LVDS Output AC Waveforms
FIGURE 6. LVTTL Input to LVDS Driver Propagation
Delay and Transition Time Test Circuit
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6
Required Specifications (Continued)
Note A: All input pulses have frequency = 10MHz, tR or tF < = 1 ns.
Note B: CL includes all probe and jig capacitances.
FIGURE 7. LVTTL Input to LVDS Output AC Waveforms
FIGURE 8. Differential Driver Enable
and Disable Test Circuits
FIGURE 9. Enable and Disable AC Waveforms
7
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Required Specifications (Continued)
FIGURE 10. Set-up and Hold Time Specification
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8
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
9
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
10
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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