FDSS2407 [ONSEMI]
N 沟道逻辑电平门极双 MOSFET 60V，3.3A，132mΩ;
| 型号： | FDSS2407 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道逻辑电平门极双 MOSFET 60V，3.3A，132mΩ |
| 文件： | 总14页 (文件大小：777K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FDSS2407
N-Channel Dual MOSFET
General Description
62V, 3.3A, 132mΩ
This dual N-Channel MOSFET provides added functions as
compared to a conventional Power MOSFET. These are: 1.
A drain to source voltage feedback signal and 2. A gate
drive disable control function that previously required
external discrete circuitry. Including these functions within
the MOSFET saves printed circuit board space. The drain to
source voltage feedback function provides a 5V level output
whenever the drain to source voltage is above 62V. This can
monitor the time an inductive load takes to dissipate its
stored energy. Multiple feedback signals can be wired
“OR’d” together to a single input of the monitoring circuit.
The gate disable function allows the device to be turned off
independent of the drive signal on the gate. This function
permits a second control circuit the ability to deactivate the
load if necessary. It can also be wired “OR’d” allowing
multiple devices to be controlled by a single open collector /
drain control transistor.
Features
62V, 132mΩ, 5V Logic Level Gate Dual MOSFET in SO-8
5V Logic Level feedback signal of the drain to source
voltage. Multiple devices can be wired “OR’d” to a single
monitoring circuit input.
Gate Drive Disable Input. Multiple devices controllable by
a single disable transistor.
Qualified to AEC Q101
Applications
Automotive Injector Driver
Solenoid Driver
Internal Diagram
1
2
3
Source 1
8
7
Drain 1
Branding Dash
5
Gate Disable
Gate 1
1
2
3
4
SO-8
6
5
Source 2
Drain 2
Pin 5 - Drain Feedback Output
Pin 7 - Gate Drive Disable Input
4
Drain FBK
Gate 2
Publication Order Number:
FDSS2407/D
©2004 Semiconductor Components Industries, LLC.
October-2017,Rev 1
MOSFET Maximum Ratings T =25°C unless otherwise noted
A
Symbol
Parameter
Ratings
62
Units
V
V
V
V
Drain to Source Voltage
Gate to Source Voltage
DSS
GS
20
Drain Current
o
o
3.3
3.0
A
A
Continuous (T = 25 C, V = 10V, R
= 55 C/W)
A
GS
θJA
I
D
o
o
Continuous (T = 25 C, V = 5V, R
= 55 C/W)
A
GS
θJA
Pulsed
Figure 4
140
A
E
P
Single Pulse Avalanche Energy ( Note 1)
Power dissipation
mJ
W
AS
2.27
D
o
o
Derate above 25 C
18
mW/ C
o
T , T
Operating and Storage Temperature
-55 to 150
C
J
STG
Thermal Characteristics
2
2
o
R
R
R
Pad Area = 0.50 in (323 mm ) (Note 2)
55
C/W
C/W
C/W
θJA
θJA
θJA
2
2
o
o
Pad Area = 0.027 in (17.4 mm ) (Note 3)
180
200
2
2
Pad Area = 0.006 in (3.87 mm ) (Note 4)
Package Marking and Ordering Information
Device Marking
Device
FDSS2407
Package
SO-8
Reel Size
330 mm
Tape Width
12 mm
Quantity
2500
2407
Electrical Characteristics T = 25°C unless otherwise noted
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 5mA, V = 0V
62
-
-
-
-
V
VDSS
D
GS
V
V
= 15V, V =0V
1
DS
GS
I
µA
nA
= 15V, V =0V,
DSS
GSS
DS
GS
-
-
-
-
250
100
o
T =150 C
A
I
V
= 20V
GS
On Characteristics
V
Gate to Source Threshold Voltage
V
= V , I = 250µA
1
-
-
3
V
GS(TH)
GS
DS
D
I
I
= 3.3A, V = 10V
0.099
0.115
0.110
0.132
D
D
GS
r
Drain to Source On Resistance
Ω
DS(ON)
= 3.0A, V = 5V
-
GS
Dynamic Characteristics
C
C
C
R
Input Capacitance
-
-
-
-
-
-
-
-
-
300
140
16
-
pF
pF
pF
Ω
nC
nC
nC
nC
nC
ISS
OSS
RSS
G
V
= 15V, V = 0V,
GS
DS
Output Capacitance
-
f = 75kHz
Reverse Transfer Capacitance
Gate Resistance
-
8500
3.3
-
4.3
0.5
-
Q
Q
Q
Q
Q
Total Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V
V
= 0V to 5V
= 0V to 1V
g(TOT)
g(TH)
gs
GS
GS
0.4
V
= 30V
= 3.3A
DD
I
1.2
D
I = 1.0mA
g
0.8
-
gs2
2.0
-
gd
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2
Switching Characteristics (V = 10V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
2700
ns
ns
ns
ns
ns
ns
ON
630
1200
8700
3500
-
-
d(ON)
-
V
V
= 30V, I = 3.3A
r
DD
GS
D
= 10V, R = 47Ω
Turn-Off Delay Time
Fall Time
-
-
GS
d(OFF)
f
Turn-Off Time
18500
OFF
Drain-Source Diode Characteristics
I
I
I
I
= 3.3A
= 1.7A
-
-
-
-
-
-
-
-
1.25
1.0
45
V
V
SD
SD
SD
SD
V
Source to Drain Diode Voltage
SD
t
Reverse Recovery Time
= 3.3A, dI /dt = 100A/µs
= 3.3A, dISD/dt = 100A/µs
ns
nC
rr
SD
Q
Reverse Recovered Charge
60
RR
Drain Feedback Characteristics
V
V
Feedback to Source Voltage
Feedback to Source Voltage
V
V
= 35V, R
= 62V, R
=51KΩ
=51KΩ
-
1
1.5
-
V
V
FBK(Low)
FBK(High)
DS
DS
FBK-SOURCE
FBK-SOURCE
3.5
4.4
Gate Drive Disable Characteristics
Gate Drive Disable Input Voltage, Gate
o
V
V
V
= 5V, I = 3.0A, T =25 C
3
-
-
-
-
V
V
DIS(High)
Enabled
GS
D
J
Gate Drive Disable Input Voltage, Gate
= V = 10V, I ≤ 250µA,
DS D
GS
V
0.4
o
DIS(Low)
Disabled
T =150 C
J
Notes:
1. Starting T = 25°C, L = 42mH, I = 2.6A, V = 62V, V = 10V.
J
AS
DD
GS
o
2
2
2. 55 C/W measured using FR-4 board with 0.50 in (323 mm ) copper pad at 1 second.
3. 180 C/W measured using FR-4 board with 0.027 in (17.4 mm ) copper pad at 1000 seconds.
4. 200 C/W measured using FR-4 board with 0.006 in (3.87 mm ) copper pad at 1000 seconds.
o
2
2
o
2
2
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
All ON Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
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3
Typical Characteristics T = 25°C unless otherwise noted
A
1.2
1.0
0.8
0.6
0.4
0.2
0
4
3
2
1
0
V
= 10V
= 5V
GS
V
GS
o
R
= 55 C/W
θJA
0
25
50
75
100
125
150
25
50
75
100
125
150
o
T
, AMBIENT TEMPERATURE ( C)
o
A
T
, AMBIENT TEMPERATURE ( C)
A
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
o
R
= 55 C/W
θJA
P
DM
0.1
t
1
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R
+ T
θJA A
J
DM
θJA
0.01
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
200
o
T
= 25 C
A
o
R
= 55 C/W
θJA
FOR TEMPERATURES
o
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
150 - T
A
I = I
25
125
V
= 5V
GS
10
3
V
= 10V
GS
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
10
Figure 4. Peak Current Capability
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4
Typical Characteristics (Continued) T = 25°C unless otherwise noted
A
100
10
1
10
o
STARTING T = 25 C
J
100µs
1ms
o
STARTING T = 150 C
J
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
If R = 0
SINGLE PULSE
t
= (L)(I )/(1.3*RATED BV
- V
)
AV
AS
DSS
DD
T
= MAX RATED
J
T
If R ≠ 0
o
o
= 25 C
A
R
= 55 C/W
t
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DSS DD
θJA
AV
AS
1
0.01
0.1
0.1
1
10
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
t
, TIME IN AVALANCHE (ms)
V
AV
DS
NOTE: Refer to ON Semiconductor Application Notes AN7514
Figure 5. Forward Bias Safe Operating Area
and AN7515
Figure 6. Unclamped Inductive Switching
Capability
15
15
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
DUTY CYCLE = 0.5% MAX
= 15V
J
V
= 5V
V
GS
o
DD
T
= 25 C
A
10
5
10
5
V
= 3.5V
GS
V
= 10V
GS
V
= 3V
GS
o
T
= 150 C
J
o
T
= -55 C
J
0
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.5
1.0
1.5
2.0
2.5
V
, GATE TO SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
GS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
240
210
180
150
120
90
2.0
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
I
= 3.3A
D
1.5
1.0
0.5
I
= 1A
D
V
= 10V, I = 3.3A
D
GS
2
4
6
8
10
-80
-40
0
40
80
120
o
160
V
, GATE TO SOURCE VOLTAGE (V)
GS
T , JUNCTION TEMPERATURE ( C)
J
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
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5
Typical Characteristics (Continued) T = 25°C unless otherwise noted
A
1.2
1.0
0.8
0.6
1.2
1.1
1.0
0.9
V
= V , I = 250µA
I = 5mA
D
GS
DS
D
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
6
1000
FBK voltage measured across
a 51KΩ load resistor.
5
C
= C + C
GS GD
ISS
4
o
C
≅ C + C
DS GD
OSS
T
= 150 C
J
3
2
1
0
100
o
T
= 25 C
J
o
C
= C
GD
T
= -55 C
RSS
J
V
= 0V, f = 75kHz
GS
10
0.1
1
10
20
20
30
40
50
60
70
V
, DRAIN TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
DS
Figure 13. Feedback Voltage vs Drain to Source
Voltage
Figure 14. Capacitance vs Drain to Source
Voltage
500
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= V
GS DS
o
T
= 150 C
J
I
= 250µA
D
V
= 5V, I = 3A
D
GS
400
300
200
100
0
8
6
4
2
0
o
T
= 25 C
J
o
T
= 150 C
J
o
T
= -55 C
J
o
T
= 25 C
J
o
T
= -55 C
J
1
2
3
4
5
0
1
2
3
4
5
V
, GATE DISABLE VOLTAGE (V)
V
DIS
, GATE DISABLE VOLTAGE (V)
DIS
Figure 15. Drain to Source On Resistance vs
Figure 16. Gate to Source Voltage vs Gate
Disable Voltage
Gate Disable Voltage
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6
Typical Characteristics (Continued) T = 25°C unless otherwise noted
A
10
V
= 30V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 3.3A
= 1A
D
D
0
2
4
6
8
Q , GATE CHARGE (nC)
g
Figure 17. Gate Charge Waveforms for Constant Gate Currents
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 18. Unclamped Energy Test Circuit
Figure 19. Unclamped Energy Waveforms
V
DS
R
L
V
Q
DD
g(TOT)
V
DS
V
GS
V
= 5V
GS
V
GS
+
-
Q
gs2
V
DD
DUT
V
= 1V
GS
I
g(REF)
0
Q
g(TH)
Q
Q
gs
gd
I
g(REF)
0
Figure 20. Gate Charge Test Circuit
Figure 21. Gate Charge Waveforms
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7
Test Circuits and Waveforms (Continued)
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
DS
90%
90%
+
-
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 22. Switching Time Test Circuit
Figure 23. Switching Time Waveforms
V
DS
+
LM324
-
NC
V
DISABLE
DUT
Figure 24. Gate to Source Voltage vs Gate Disable Voltage
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8
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T , and the
maximum transient thermal impedance curve.
JM
thermal resistance of the heat dissipating path determines
Thermal resistances corresponding to other copper areas
can be obtained from Figure 25 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
the maximum allowable device power dissipation, P , in an
DM
application.
Therefore the application’s ambient
o
o
temperature, T ( C), and thermal resistance R
must be reviewed to ensure that T
( C/W)
A
θJA
is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
15
R
= 79.9 + -------------------------------
0.14 + Area
(EQ. 2)
θJA
(T
– T )
JM
A
(EQ. 1)
P
= ------------------------------
DM
RθJA
The transient thermal impedance (Z ) is also effected by
θJA
varied top copper board area. Figure 26 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:
is complex
DM
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
200
5. Air flow and board orientation.
R
= 79.9 + 15/(0.14+Area)
θJA
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
150
ON Semiconductor provides thermal information to
assist
evaluation. Figure 25
defines the R for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
the
designer’s
preliminary
application
100
50
θJA
0.001
0.01
0.1
1
10
2
AREA, TOP COPPER AREA (in )
Figure 25. Thermal Resistance vs Mounting
applications
can
be
evaluated
using
the
ON
Pad Area
Semiconductor device Spice thermal model or manually
utilizing the normalized
160
COPPER BOARD AREA - DESCENDING ORDER
2
0.020 in
2
0.140 in
2
0.257 in
0.380 in
0.493 in
120
80
40
0
2
2
-1
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
Figure 26. Thermal Impedance vs Mounting Pad Area
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9
PSPICE Electrical Model
.SUBCKT FDSS2407 2 1 3 101 102
Ca 12 8 1e-10
;
rev July 2004
Cb 15 14 4e-10
Cin 6 8 2.8e-10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
CGATE 9 20 5e-9
DDISABLE 20 101 DDISABLEMOD
DFBK1 104 103 DFBK1MOD
DFBK2 7 104 DFBK2MOD
DFBK3 104 102 DFBK3MOD
RFBK1 5 103 RFBK1MOD 13e3
RFBK2 104 7 RFBK2MOD 2.15e3
Ebreak 11 7 17 18 67.4
Eds 14 8 5 8 1
LDRAIN
DPLCAP
5
DRAIN
2
10
RLDRAIN
RFBK1
RSLC1
51
DBREAK
11
+
RSLC2
103
5
51
ESLC
DFBK1
-
+
17
18
50
DBODY
104
-
EBREAK
INJ FBK
102
RDRAIN
6
8
ESG
DFBK3
DFBK2
-
Egs 13 8 6 8 1
Esg 6 10 6 8 1
EVTHRES
+
16
CGATE
21
+
-
19
8
MWEAK
LGATE
EVTEMP
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 1.8e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 0.6e-9
RLgate 1 9 18
RLdrain 2 5 10
RLsource 3 7 6
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 3.5e-2
Rgate 9 20 RgateMOD 8.63e3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RGATE
9
GATE
1
6
+
-
18
22
RFBK2
7
MMED
20
MSTRO
8
RLGATE
LSOURCE
CIN
GATE
SOURCE
3
DISABLE
101
RSOURCE
RLSOURCE
DDISABLE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
Rsource 8 7 RsourceMOD 5.3e-2
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
RVTHRES
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*20),3.5))}
.MODEL DbodyMOD D (IS=1.1E-12 N=1.05 IKF=4e-1 RS=4.2e-2 TRS1=3e-4 TRS2=1.3e-6
+ CJO=3.3e-10 TT=3e-8 M=0.38, XTI=3.5)
.MODEL DbreakMOD D (RS=1 TRS1=1e-3 TRS2=-9e-6)
.MODEL DplcapMOD D (CJO=1.97e-10 IS=1e-30 N=10 M=0.84)
.MODEL DDISABLEMOD D (RS=30 IS=1e-15 BV=4.7 TBV1=-3e-4 TBV2=-3e-6 XTI=0)
.MODEL DFBK1MOD D (IS=1e-15 BV=23.8 IKF=2 TBV1=-6e-4 TBV2=6e-6)
.MODEL DFBK2MOD D (RS=1 IS=1e-30 BV=5.6 N=3.3 NBV=1)
.MODEL DFBK3MOD D (RS=1 IS=1e-15 BV=4.2 NBV=2.5)
.MODEL MmedMOD NMOS (VTO=1.7 KP=1.08 IS=1e-30 N=10 TOX=1 L=1u W=1u RG= 8.56e3)
.MODEL MstroMOD NMOS (VTO=2 KP=14 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.5 kp=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG= 8.56e4 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.05e-3 TC2=-9e-7)
.MODEL RdrainMOD RES (TC1=9e-3 TC2=2.7e-5)
.MODEL RSLCMOD RES (TC1=2e-3 TC2=6e-6)
.MODEL RsourceMOD RES (TC1=3e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1.1e-3 TC2=-3.3e-6)
.MODEL RvtempMOD RES (TC1=-1.6e-3 TC2=1e-7)
.MODEL RFBK1MOD RES (TC1=-1.4e-3 TC2=1e-6)
.MODEL RFBK2MOD RES (TC1=-1.4e-3 TC2=1e-6)
.MODEL RgateMOD RES (TC1=-1.4e-3 TC2=1e-5)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-3.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.0 VOFF=-4.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-1.0)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
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10
SABER Electrical Model
REV July 2004
template FDSS2407 n2,n1,n3,n101,n102
electrical n2,n1,n3,n101,n102
{
var i iscl
dp..model dbodymod = (isl=1.1e-12,nl=1.05,ikf=4e-1,rs=4.2e-2,trs1=3e-4,trs2=1.3e-6,cjo=3.3e-10,tt=3e-8,m=0.38,xti=3.5)
dp..model dbreakmod = (rs=1,trs1=1e-3,trs2=-9e-6)
dp..model ddisablemod = (rs=30, isl=1e-15,bv=4.7,tbv1=-3e-4,tbv2=-3e-6,xti=0)
dp..model dfbk1mod = (isl=1e-15,bv=23.8,ikf=2,tbv1=-6e-4,tbv2=6e-6)
dp..model dfbk2mod = (rs=1,isl=1e-30,bv=5.6,nl=3.3,nbv=1)
dp..model dfbk3mod = (rs=1,isl=1e-15,bv=4.2,nbv=2.5)
dp..model dplcapmod = (cjo=1.97e-10,isl=10e-30,nl=10,m=0.84)
m..model mmedmod = (type=_n,vto=1.7,kp=1.08,is=1e-30,tox=1)
m..model mstrongmod = (type=_n,vto=2,kp=14,is=1e-30,tox=1)
m..model mweakmod = (type=_n,vto=1.5,kp=0.04,is=1e-30, tox=1,rs=0.1)
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-3.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.0,voff=-4.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.0,voff=-0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-1.0)
c.ca n12 n8 = 1e-10
c.cb n15 n14 = 4e-10
c.cin n6 n8 = 2.8e-10
c.cgate n9 n20 = 5e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RFBK1
DBODY
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
dp.ddisable n20 n101 = model=ddisablemod
dp.dfbk1 n104 n103 = model=dfbk1mod
dp.dfbk2 n7 n104 = model=dfbk2mod
dp.dfbk3 n104 n102 = model=dfbk3mod
spe.ebreak n11 n7 n17 n18 = 67.4
spe.eds n14 n8 n5 n8 = 1
RSLC1
51
RSLC2
103
104
ISCL
DFBK1
DBREAK
11
50
-
INJ FBK
102
RDRAIN
6
8
ESG
DFBK3
DFBK2
EVTHRES
+
16
21
CGATE
RGATE
+
-
19
8
MWEAK
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
LGATE
EVTEMP
GATE
1
+
6
-
RFBK2
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
-
spe.evtemp n20 n6 n18 n22 = 1
RLGATE
LSOURCE
CIN
SOURCE
3
GATE
i.it n8 n17 = 1
7
DISABLE
l.lgate n1 n9 = 1.8e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 0.6e-9
res.rlgate n1 n9 = 18
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 6
res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=-9e-7
res.rdrain n50 n16 = 3.5e-2,tc1=9e-3,tc2=2.7e-5
res.rgate n9 n20 = 8.63e3,tc1=-1.4e-3,tc2=1e-5
res.rfbk1 n5 n103 = 13e3,tc1=-1.4e-3,tc2=1e-6
res.rfbk2 n104 n7 = 2.15e3,tc1=-1.4e-3,tc2=1e-6
res.rslc1 n5 n51 = 1e-6,tc1=2e-3,tc2=6e-6
res.rslc2 n5 n50 = 1e3
101
RSOURCE
RLSOURCE
DDISABLE
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
res.rsource n8 n7 = 5.3e-2,tc1=3e-3,tc2=1e-6
res.rvthres n22 n8 = 1,tc1=-1.1e-3,tc2=-3.3e-6
res.rvtemp n18 n19 = 1,tc1=-1.6e-3,tc2=1e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/20))** 3.5))
}
}
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11
SPICE Thermal Model
JUNCTION
th
REV July 2004
FDSS2407T
Copper Area =0.5 in2
CTHERM1 Junction c2 1.2e-4
CTHERM2 c2 c3 2e-3
CTHERM3 c3 c4 2e-2
CTHERM4 c4 c5 3.0e-2
CTHERM5 c5 c6 4e-2
CTHERM6 c6 c7 7e-2
CTHERM7 c7 c8 2e-1
CTHERM8 c8 Ambient 2.8
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
8
7
RTHERM1 Junction c2 1.4
RTHERM2 c2 c3 2.0
RTHERM3 c3 c4 2.8
RTHERM4 c4 c5 9.0
RTHERM5 c5 c6 18.0
RTHERM6 c6 c7 26.0
RTHERM7 c7 c8 28.0
RTHERM8 c8 Ambient 29.0
6
5
SABER Thermal Model
Copper Area = 0.5 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th c2 =1.2e-4
ctherm.ctherm2 c2 c3 =2e-3
ctherm.ctherm3 c3 c4 =2e-2
ctherm.ctherm4 c4 c5 =3.0e-2
ctherm.ctherm5 c5 c6 =4e-2
ctherm.ctherm6 c6 c7 =7e-2
ctherm.ctherm7 c7 c8 =2e-1
ctherm.ctherm8 c8 tl =2.8
4
3
2
rtherm.rtherm1 th c2 =1.4
rtherm.rtherm2 c2 c3 =2.0
rtherm.rtherm3 c3 c4 =2.8
rtherm.rtherm4 c4 c5 =9.0
rtherm.rtherm5 c5 c6 =18.0
rtherm.rtherm6 c6 c7 =26.0
rtherm.rtherm7 c7 c8 =28.0
rtherm.rtherm8 c8 tl =29.0
}
tl
AMBIENT
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12
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