FDS5672_技术文档

Is Now Part of

To learn more about ON Semiconductor, please visit our website at

www.onsemi.com

Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers

will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor

product management systems do not have the ability to manage part nomenclature that utilizes an underscore

(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain

device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated

device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please

email any questions regarding the system integration to Fairchild_questions@onsemi.com.

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number

of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right

to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and speciﬁcally disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON

Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON

Semiconductor data sheets and/or speciﬁcations can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s

technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA

Class 3 medical devices or medical devices with a same or similar classiﬁcation in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its ofﬁcers, employees, subsidiaries, afﬁliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out

of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor

is an Equal Opportunity/Afﬁrmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

July 2005

FDS5672

N-Channel PowerTrench^®MOSFET

60V, 12A, 10mΩ

General Description

Features

r_DS(ON)= 10mΩ, V_GS= 10V, I_D= 12A

This N-Channel MOSFET has been designed specifically to

improve the overall efficiency of DC/DC converters using

either synchronous or conventional switching PWM

controllers. It has been optimized for low gate charge, low

r_DS(ON)= 14mΩ, V_GS= 6V, I_D= 10A

High performance trench technology for extremely low

r_DS(ON)and fast switching speed.

r_DS(ON)

Low gate charge

High power and current handling capability

Applications

DC/DC converters

Branding Dash

5

6

7

8

4

3

2

1

5

1

2

3

4

SO-8

FDS5672 Rev. A

www.fairchildsemi.com

1

MOSFET Maximum Ratings T_C= 25°C unless otherwise noted

Symbol

V_DSS

V_GS

Parameter

Ratings

60

Units

Drain to Source Voltage

Gate to Source Voltage

Drain Current

V

20

Continuous (T_C= 25 ^oC, V_GS= 10V, R_θJA= 50^oC/W)

Continuous (T_C= 25 ^oC, V_GS= 6V, R_θJA= 50^oC/W)

Pulsed

12

10

A

I_D

Figure 4

245

A

mJ

E_AS

Single Pulse Avalanche Energy (Note 1)

Power dissipation

Derate above 25^oC

2.5

W

P_D

20

mW/^oC

^oC

T_J, T_STG

Operating and Storage Temperature

-55 to 150

Thermal Characteristics

R_θJC

R_θJA

Thermal Resistance Junction to Case (Note 2)

25

50

85

^oC/W

Thermal Resistance Junction to Ambient at 10 seconds (Note 3)

Thermal Resistance Junction to Ambient at 1000 seconds (Note 3)

Package Marking and Ordering Information

Device Marking

Device

Package

Reel Size

Tape Width

12mm

Quantity

2500 units

FDS5672

SO-8

330mm

Electrical Characteristics T_C= 25°C unless otherwise noted

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

B_VDSS

Drain to Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate to Source Leakage Current

I_D= 250µA, V_GS= 0V

60

-

V

V_DS= 50V

1

I_DSS

µA

V_GS= 0V

T_C= 150^oC

-

250

100

I_GSS

V_GS= 20V

-

nA

On Characteristics

V_GS(TH)

Gate to Source Threshold Voltage

V_GS= V_DS, I_D= 250µA

I_D= 12A, V_GS= 10V

I_D= 10A, V_GS= 6V,

I_D= 12A, V_GS= 10V,

2

-

4

V

0.0088 0.010

0.012 0.014

-

r_DS(ON)

Drain to Source On Resistance

Ω

-

0.016 0.023

T

_C= 150^oC

Dynamic Characteristics

C_ISS

C_OSS

C_RSS

R_G

Input Capacitance

-

2200

410

130

1.4

34

-

pF

Ω

nC

V_DS= 25V, V_GS= 0V,

f = 1MHz

Output Capacitance

-

Reverse Transfer Capacitance

Gate Resistance

V_GS= 0.5V, f = 1MHz

V_GS= 0V to 10V

-

Q_g(TOT)

Q_g(TH)

Q_gs

Total Gate Charge at 10V

Threshold Gate Charge

Gate to Source Gate Charge

Gate Charge Threshold to Plateau

Gate to Drain “Miller” Charge

45

5.5

-

V_GS= 0V to 2V

4.2

9.4

5.2

9.3

V_DD= 30V

I_D= 12A

I_g= 1.0mA

Q_gs2

Q_gd

-

www.fairchildsemi.com

FDS5672 Rev. A

2

Resistive Switching Characteristics (V_GS= 10V)

t_ON

t_d(ON)

t_r

Turn-On Time

Turn-On Delay Time

Rise Time

-

50

-

ns

13

20

35

14

-

V_DD= 30V, I_D= 12A

V_GS= 10V, R_GS= 9.1Ω

t_d(OFF)

t_f

Turn-Off Delay Time

Fall Time

-

t_OFF

Turn-Off Time

64

Drain-Source Diode Characteristics

I_SD= 12A

-

1.25

1.0

39

V

V_SD

Source to Drain Diode Voltage

I_SD= 6A

t_rr

Reverse Recovery Time

I_SD=12A, dI_SD/dt = 100A/µs

ns

nC

Q_RR

Reverse Recovered Charge

40

Notes:

1: Starting T = 25°C, L = 1mH, I = 22A, V = 60V, V = 10V.

J

AS

DD

GS

2: R

drain pins. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the

θJA

is guaranteed by design while R

is determined by the user’s board design.

θJC

θJA

2

3: R

is measured with 1.0 in copper on FR-4 board.

θJA

www.fairchildsemi.com

FDS5672 Rev. A

3

Typical Characteristics T_C= 25°C unless otherwise noted

1.2

1.0

0.8

0.6

0.4

0.2

0

15

12

9

V

= 10V

GS

6

3

0

25

50

75

100

125

150

25

50

75

100

125

150

o

T

, AMBIENT TEMPERATURE ( C)

T , AMBIENT TEMPERATURE ( C)

A

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

Figure 2. Maximum Continuous Drain Current vs

Ambient Temperature

2

1

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.02

0.01

0.1

P

DM

SINGLE PULSE

0.01

t

1

t

2

NOTES:

DUTY FACTOR: D = t /t

1

2

PEAK T = P

x Z

x R

+ T

θJA A

J

DM

θJA

0.001

-5

-4

-3

-2

-1

0

1

2

3

10

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

1100

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

o

T

= 25 C

A

FOR TEMPERATURES

ABOVE 25 C DERATE PEAK

o

CURRENT AS FOLLOWS:

V

= 10V

GS

150 - T

A

I = I

25

125

100

10

3

-5

-4

-3

-2

-1

0

1

2

10

t, PULSE WIDTH (s)

10

Figure 4. Peak Current Capability

www.fairchildsemi.com

FDS5672 Rev. A

4

Typical Characteristics T_C= 25°C unless otherwise noted

400

100

50

100µs

If R = 0

= (L)(I )/(1.3*RATED BV

t

- V

DD

)

AV

AS

DSS

If R ≠ 0

t

= (L/R)ln[(I *R)/(1.3*RATED BV

- V ) +1]

DD

AV

AS

DSS

1ms

10

1

o

STARTING T = 25 C

J

OPERATION IN THIS

AREA MAY BE

10ms

LIMITED BY r

DS(ON)

SINGLE PULSE

o

STARTING T = 150 C

J

T

= MAX RATED

J

o

T

= 25 C

A

1

0.1

1

10

70

0.1

1

10

100

V

, DRAIN TO SOURCE VOLTAGE (V)

t , TIME IN AVALANCHE (ms)

AV

DS

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

Figure 5. Forward Bias Safe Operating Area

25

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

V

= 6V

GS

V

= 5V

GS

20

15

V

= 15V

20

DD

15

10

5

o

T

= 150 C

V

= 10V

J

GS

V

= 4.5V

GS

10

5

o

T

= -55 C

J

T

= 25 C

J

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

o

T

= 25 C

A

0

3.0

3.5

4.0

4.5

5.0

5.5

0

0.2

0.4

0.6

0.8

1.0

V

, GATE TO SOURCE VOLTAGE (V)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

GS

Figure 7. Transfer Characteristics

Figure 8. Saturation Characteristics

15.0

12.5

10.0

2.0

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

V

= 6V

GS

1.5

1.0

0.5

V

= 10V

GS

7.5

5.0

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

V

= 10V, I = 12A

D

GS

-80

-40

0

40

80

120

o

160

0

3

6

9

12

I , DRAIN CURRENT (A)

T , JUNCTION TEMPERATURE ( C)

J

D

Figure 9. Drain to Source On Resistance vs Drain

Current

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

www.fairchildsemi.com

FDS5672 Rev. A

5

Typical Characteristics T_C= 25°C unless otherwise noted

1.2

1.1

1.0

0.9

0.8

0.7

0.6

1.10

1.05

1.00

V

= V , I = 250µA

DS D

GS

I

= 250µA

D

0.95

0.90

-80

-40

0

40

80

120

160

-80

-40

0

40

80

120

160

o

T , JUNCTION TEMPERATURE ( C)

J

Figure 11. Normalized Gate Threshold Voltage vs

Junction Temperature

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

6000

10

C

= C + C

GS GD

ISS

V

= 50V

DD

8

6

4

1000

C

≅ C + C

GD

OSS

C

DS

= C

RSS

GD

100

40

2

0

WAVEFORMS IN

DESCENDING ORDER:

V

= 0V, f = 1MHz

1

I

= 12A

= 1A

GS

D

0.1

10

60

0

5

10

15

20

25

30

35

V

, DRAIN TO SOURCE VOLTAGE (V)

Q , GATE CHARGE (nC)

DS

g

Figure 13. Capacitance vs Drain to Source

Voltage

Figure 14. Gate Charge Waveforms for Constant

Gate Currents

www.fairchildsemi.com

FDS5672 Rev. A

6

Test Circuits and Waveforms

V

BV

DSS

DS

t

P

V

DS

L

I

AS

V

DD

VARY t TO OBTAIN

P

+

-

R

REQUIRED PEAK I

G

AS

V

DD

V

GS

DUT

t

P

I

0V

AS

0

0.01Ω

t

AV

Figure 15. Unclamped Energy Test Circuit

Figure 16. Unclamped Energy Waveforms

V

DS

V

Q

DD

g(TOT)

V

DS

L

V

= 10V

GS

V

GS

+

-

V

DD

V

GS

V

= 2V

DUT

GS

Q

gs2

0

I

g(REF)

Q

g(TH)

Q

gd

gs

I

g(REF)

0

Figure 17. Gate Charge Test Circuit

Figure 18. Gate Charge Waveforms

V

DS

t

ON

OFF

t

d(OFF)

t

d(ON)

R

t

f

L

r

V

0

DS

90%

+

-

V

GS

V

DD

10%

DUT

90%

50%

R

GS

V

0

GS

50%

PULSE WIDTH

10%

V

GS

Figure 19. Switching Time Test Circuit

Figure 20. Switching Time Waveforms

www.fairchildsemi.com

FDS5672 Rev. A

7

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, T_JM, and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, P_DM, in an

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using

Equation 2. The area, in square inches is the top copper

area including the gate and source pads.

application.

Therefore the application’s ambient

temperature, T_A(^oC), and thermal resistance R_θJA(^oC/W)

must be reviewed to ensure that T_JMis never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

26

R

= 64 + -------------------------------

(EQ. 2)

θJA

0.23 + Area

(T

– T )

A

JM

(EQ. 1)

P

= ------------------------------

DM

R_θJA

The transient thermal impedance (Z_θJA) is also effected by

varied top copper board area. Figure 22 shows the effect of

copper pad area on single pulse transient thermal

impedance. Each trace represents a copper pad area in

square inches corresponding to the descending list in the

graph. Spice and SABER thermal models are provided for

each of the listed pad areas.

In using surface mount devices such as the SO8 package,

the environment in which it is applied will have a significant

influence on the part’s current and maximum power

dissipation ratings. Precise determination of P_DMis complex

and influenced by many factors:

Copper pad area has no perceivable effect on transient

thermal impedance for pulse widths less than 100ms. For

pulse widths less than 100ms the transient thermal

impedance is determined by the die and package.

Therefore, CTHERM1 through CTHERM5 and RTHERM1

through RTHERM5 remain constant for each of the thermal

models. A listing of the model component values is available

in Table 1.

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

200

5. Air flow and board orientation.

R

= 64 + 26/(0.23+Area)

θJA

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

150

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21

defines the R_θJAfor the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

100

50

0.001

0.01

0.1

1

10

2

AREA, TOP COPPER AREA (in )

Figure 21. Thermal Resistance vs Mounting

Pad Area

150

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

0.52 in

0.76 in

1.00 in

120

90

60

30

0

2

-1

0

1

2

3

10

t, RECTANGULAR PULSE DURATION (s)

10

Figure 22. Thermal Impedance vs Mounting Pad Area

www.fairchildsemi.com

FDS5672 Rev. A

8

PSPICE Electrical Model

.SUBCKT FDS5672 2 1 3 ;

Ca 12 8 7e-10

rev June 2005

Cb 15 14 7e-10

Cin 6 8 2.2e-10

LDRAIN

DPLCAP

DRAIN

2

5

10

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Dplcap 10 5 DplcapMOD

RLDRAIN

RSLC1

51

DBREAK

+

RSLC2

5

ESLC

11

51

Ebreak 11 7 17 18 67

Eds 14 8 5 8 1

Egs 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtemp 20 6 18 22 1

-

+

50

-

17

DBODY

RDRAIN

6

8

EBREAK 18

-

ESG

EVTHRES

+

16

21

+

-

19

8

MWEAK

LGATE

EVTEMP

RGATE

GATE

1

6

+

-

18

22

It 8 17 1

MMED

9

20

MSTRO

8

RLGATE

Lgate 1 9 1.23e-9

Ldrain 2 5 1.0e-9

Lsource 3 7 0.18e-9

LSOURCE

CIN

SOURCE

3

7

RSOURCE

RLSOURCE

RLgate 1 9 12.3

RLdrain 2 5 10

RLsource 3 7 1.8

S1A

S2A

RBREAK

12

15

13

8

14

13

17

18

RVTEMP

19

S1B

S2B

Mmed 16 6 8 8 MmedMOD

Mstro 16 6 8 8 MstroMOD

Mweak 16 21 8 8 MweakMOD

13

CB

CA

IT

14

-

+

VBAT

6

8

5

8

EGS

EDS

+

Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 1e-3

Rgate 9 20 1.4

-

8

22

RVTHRES

RSLC1 5 51 RSLCMOD 1.0e-6

RSLC2 5 50 1.0e3

Rsource 8 7 RsourceMOD 3.2e-3

Rvthres 22 8 RvthresMOD 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),2.5))}

.MODEL DbodyMOD D (IS=4.5E-12 RS=4.7e-3 TRS1=1.5e-3 TRS2=2e-5

+ CJO=1.6e-9 M=0.55 TT=1.8e-8 XTI=3.0)

.MODEL DbreakMOD D (RS=2.5 TRS1=1.0e-3 TRS2=1e-6)

.MODEL DplcapMOD D (CJO=6.0e-10 IS=1.0e-30 N=10 M=0.45)

.MODEL MmedMOD NMOS (VTO=3.35 KP=4 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.4)

.MODEL MstroMOD NMOS (VTO=3.93 KP=50 IS=1e-30 N=10 TOX=1 L=1u W=1u)

.MODEL MweakMOD NMOS (VTO=2.82 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14 RS=0.1)

.MODEL RbreakMOD RES (TC1=7e-4 TC2=-1.3e-7)

.MODEL RdrainMOD RES (TC1=1.0e-4 TC2=1e-5)

.MODEL RSLCMOD RES (TC1=1.0e-2 TC2=1e-7)

.MODEL RsourceMOD RES (TC1=1.0e-2 TC2=1.0e-6)

.MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.4e-5)

.MODEL RvtempMOD RES (TC1=-4e-3 TC2=2e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-2.0)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-4.0)

.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0)

.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=-0.5)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

www.fairchildsemi.com

FDS5672 Rev. A

9

SABER Electrical Model

REV June 2005

ttemplate FDS5672 n2,n1,n3

electrical n2,n1,n3

{

var i iscl

dp..model dbodymod = (isl=4.5e-12,rs=4.7e-3,trs1=1.5e-3,trs2=2e-5,cjo=1.6e-9,m=0.55,tt=1.8e-8,xti=3.0)

dp..model dbreakmod = (rs=2.5,trs1=1e-4,trs2=1e-6)

dp..model dplcapmod = (cjo=6.0e-10,isl=10.0e-30,nl=10,m=0.45)

m..model mmedmod = (type=_n,vto=3.35,kp=4,is=1e-30, tox=1)

m..model mstrongmod = (type=_n,vto=3.93,kp=50,is=1e-30, tox=1)

m..model mweakmod = (type=_n,vto=2.82,kp=0.04,is=1e-30, tox=1,rs=0.1)

sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-2.0)

sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-4.0)

LDRAIN

DPLCAP

5

DRAIN

2

sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0)

sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0,voff=-0.5)

10

RLDRAIN

c.ca n12 n8 = 7e-10

c.cb n15 n14 = 7e-10

c.cin n6 n8 = 2.2e-9

RSLC1

51

RSLC2

ISCL

dp.dbody n7 n5 = model=dbodymod

dp.dbreak n5 n11 = model=dbreakmod

dp.dplcap n10 n5 = model=dplcapmod

DBREAK

11

50

-

RDRAIN

6

8

ESG

DBODY

EVTHRES

+

16

21

+

spe.ebreak n11 n7 n17 n18 = 67

-

19

8

MWEAK

LGATE

EVTEMP

spe.eds n14 n8 n5 n8 = 1

spe.egs n13 n8 n6 n8 = 1

RGATE

GATE

1

6

+

-

18

22

EBREAK

+

MMED

9

20

spe.esg n6 n10 n6 n8 = 1

spe.evthres n6 n21 n19 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

MSTRO

8

17

18

-

RLGATE

LSOURCE

CIN

SOURCE

3

7

i.it n8 n17 = 1

RSOURCE

RLSOURCE

S1A

S2A

l.lgate n1 n9 = 1.23e-9

l.ldrain n2 n5 = 1.0e-9

l.lsource n3 n7 = 0.18e-9

RBREAK

12

15

13

8

14

13

17

18

RVTEMP

19

S1B

S2B

13

CB

res.rlgate n1 n9 = 12.3

res.rldrain n2 n5 = 10

res.rlsource n3 n7 = 1.8

CA

IT

14

-

+

VBAT

6

8

5

8

EGS

EDS

+

-

8

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

22

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

RVTHRES

res.rbreak n17 n18 = 1, tc1=7e-4,tc2=-1.3e-7

res.rdrain n50 n16 = 1e-3, tc1=1e-4,tc2=1e-5

res.rgate n9 n20 = 1.4

res.rslc1 n5 n51 = 1e-6, tc1=1e-2,tc2=1e-7

res.rslc2 n5 n50 = 1e3

res.rsource n8 n7 = 3.2e-3, tc1=1e-2,tc2=1e-6

res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.4e-5

res.rvtemp n18 n19 = 1, tc1=-4e-3,tc2=2e-7

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51->n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5))

}

www.fairchildsemi.com

FDS5672 Rev. A

10

SPICE Thermal Model

REV June 2005

JUNCTION

th

FDS5672_JA Junction Ambient

Copper Area = 1sq.in

CTHERM1 TH 8 2e-3

CTHERM2 8 7 5e-3

CTHERM3 7 6 1e-2

CTHERM4 6 5 4e-2

CTHERM5 5 4 9e-2

CTHERM6 4 3 2e-1

CTHERM7 3 2 1

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

CTHERM1

8

7

CTHERM2

CTHERM3

CTHERM4

CTHERM5

CTHERM6

CTHERM7

CTHERM8

CTHERM8 2 TL 3

RTHERM1 TH 8 1e-1

RTHERM2 8 7 5e-1

RTHERM3 7 6 1

RTHERM4 6 5 5

RTHERM5 5 4 8

RTHERM6 4 3 12

RTHERM7 3 2 18

RTHERM8 2 TL 25

6

5

SABER Thermal Model

SABER thermal model FDS5672

Copper Area = 1sq.in

template thermal_model th tl

thermal_c th, tl

{

ctherm.ctherm1 th 8 =2e-3

ctherm.ctherm2 8 7 =5e-3

ctherm.ctherm3 7 6 =1e-2

ctherm.ctherm4 6 5 =4e-2

ctherm.ctherm5 5 4 =9e-2

ctherm.ctherm6 4 3 =2e-1

ctherm.ctherm7 3 2 =1

ctherm.ctherm8 2 tl =3

4

3

2

rrtherm.rtherm1 th 8 =1e-1

rtherm.rtherm2 8 7 =5e-1

rtherm.rtherm3 7 6 =1

rtherm.rtherm4 6 5 =5

rtherm.rtherm5 5 4 =8

rtherm.rtherm6 4 3 =12

rtherm.rtherm7 3 2 =18

rtherm.rtherm8 2 tl =25

}

tl

AMBIENT

T ABLE 1. THERMAL MODELS

COMPONANT

CTHERM6

CTHERM7

CTHERM8

RTHERM6

RTHERM7

RTHERM8

0.04 in²

1.2e-1

0.5

0.28 in²

1.5e-1

1.0

0.52 in²

2.0e-1

1.0

0.76 in²

2.0e-1

1.0

1.0 in²

2.0e-1

1.0

1.3

2.8

3.0

26

20

15

13

12

39

24

21

19

18

55

38.7

31.3

29.7

25

www.fairchildsemi.com

FDS5672 Rev. A

11

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not

intended to be an exhaustive list of all such trademarks.

ACEx™

FACT Quiet Series™ ImpliedDisconnect™ POP™

Stealth™

ActiveArray™

Bottomless™

CoolFET™

CROSSVOLT™ FRFET™

DOME™

EcoSPARK™

E²CMOS™

EnSigna™

FACT™

FAST^®

FASTr™

FPS™

IntelliMAX™

ISOPLANAR™

LittleFET™

Power247™

PowerEdge™

PowerSaver™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

MICROCOUPLER™ PowerTrench^®

GlobalOptoisolator™ MicroFET™

QFET^®

GTO™

HiSeC™

I²C™

MicroPak™

MICROWIRE™

MSX™

MSXPro™

OCX™

QS™

TinyLogic^®

QT Optoelectronics™ TINYOPTO™

Quiet Series™

RapidConfigure™

RapidConnect™

µSerDes™

TruTranslation™

UHC™

i-Lo™

UltraFET^®

UniFET™

Across the board. Around the world.™ OCXPro™

The Power Franchise^®

OPTOLOGIC^®

OPTOPLANAR™

PACMAN™

SILENT SWITCHER^®VCX™

SMART START™

SPM™

Programmable Active Droop™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

FDS5672 Rev. A

12

www.fairchildsemi.com

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

www.onsemi.com

1


型号：	FDS5672
厂家：	ONSEMI
描述：	N 沟道 PowerTrench® MOSFET 60V，12A，10mΩ 开关光电二极管晶体管
文件：	总14页 (文件大小：435K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FDS5672 [ONSEMI]

相关型号：

FDS5680

FDS5680

FDS5680D84Z

FDS5680F011

FDS5680L99Z

FDS5680S62Z

FDS5680_NL

FDS5682

FDS5682_08

FDS5682_NL

FDS5690

FDS5690