FDS4559 [ONSEMI]
60V，互补，PowerTrench® MOSFET;
| 型号： | FDS4559 |
| 厂家： | 
ONSEMI |
| 描述： | 60V，互补，PowerTrench® MOSFET 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总10页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET – Complementary,
POWERTRENCH)
V
I
Max
R
Max
DSS
D
DS(on)
55 mW @ 10 V
N−Channel
4.5 A
60 V
75 mW @ 4.5 V
105 mW @ −10 V
135 mW @ −4.5 V
60 V
P−Channel
−60 V
−3.5 A
FDS4559
General Description
This complementary MOSFET device is produced using onsemi’s
advanced PowerTrench process that has been especially tailored to
minimize the on−state resistance and yet maintain low gate charge for
superior switching performance.
D2
D2
D1
D1
G2
S2
G1
S1
Pin 1
Features
SOIC8
CASE 751EB
• Q1: N−Channel
♦ 4.5 A, 60 V
R
DS(on)
R
DS(on)
= 55 mΩ @ V = 10 V
GS
= 75 mΩ @ V = 4.5 V
GS
MARKING DIAGRAM
• Q2: P−Channel
♦ −3.5 A, −60 V
FDS4559
ALYW
R
DS(on)
= 105 mΩ @ V = –10 V
GS
R
DS(on)
= 135 mΩ @ V = –4.5 V
GS
Applications
• DC/DC converter
• Power management
• LCD backlight inverter
• This is a Pb−Free and Halide Free Device
FDS4559 = Specific Device Code
A
= Assembly Site
L
YW
= Wafer Lot Number
= Assembly Start Week
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Drain−Source Voltage
Q1
Q2
−60
20
Unit
V
N−Channel / P−Channel
V
60
20
DSS
GSS
Q2
V
Gate−Source Voltage
V
5
4
3
2
1
I
D
Drain Current
Continuous (Note 1a) 4.5
−3.5
−20
A
6
7
8
Pulsed
Power Dissipation for Dual Operation
20
Q1
P
D
2
W
Power Dissipation
for Single Operation
(Note 1a)
1.6
1.2
1
(Note 1b)
(Note 1c)
ORDERING INFORMATION
T ,
STG
Operating and Storage Junction
Temperature Range
−55 to +175
°C
J
T
†
Package
Device
Shipping
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
SOIC8
FDS4559
2500 /
(Pb−Free,
Halide Free)
Tape & Reel
THERMAL CHARACTERISTICS
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifica-
tions Brochure, BRD8011/D.
Symbol
Parameter
Value
Unit
R
Thermal Resistance,
Junction−to−Ambient
78
_C/W
q
JA
(Note 1a)
(Note 1)
R
Thermal Resistance,
Junction−to−Case
40
_C/W
q
JC
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
July 2022 − Rev.4
FDS4559/D
FDS4559
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Test Condition
Typ
Min
Typ
Max
Unit
DRAIN−SOURCE AVALANCHE RATINGS (Note 1)
W
Single Pulse Drain−Source
V
DD
= 30 V, I = 25 A
Q1
Q1
−
−
−
−
90
V
V
DSS
D
Avalanche Energy
I
Maximum Drain−Source
Avalanche Current
4.5
AR
OFF CHARACTERISTICS
BV
Drain−Source Breakdown
Voltage
V
GS
V
GS
= 0 V, I = 250 mA
Q1
Q2
60
−60
−
−
−
−
V
DSS
D
= 0 V, I = −250 mA
D
Breakdown Voltage
Temperature Coefficient
I = 250 mA, Referenced to 25_C
Q1
Q2
−
−
58
−49
−
−
mV/_C
D
DBVDSS
DTJ
I = −250 mA, Referenced to 25_C
D
I
Zero Gate Voltage Drain
Current
V
DS
V
DS
= 48 V, V = 0 V
Q1
Q2
−
−
−
−
1
−1
mA
DSS
GS
= −48 V, V = 0 V
GS
I
Gate–Body Leakage
V
GS
V
GS
=
=
20 V, V = 0 V
Q1
Q2
−
−
−
−
100
100
nA
GSS
DS
20 V, V = 0 V
DS
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
V
DS
= V , I = 250 mA
Q1
Q2
1
−1
2.2
−1.6
3
−3
V
GS
D
= V , I = −250 mA
GS
D
Gate Threshold Voltage
Temperature Coefficient
I = 250 mA, Referenced to 25_C
Q1
Q2
−
−
−5.5
4
−
−
mV/_C
DVGS(th)
DTJ
D
I = −250 mA, Referenced to 25_C
D
R
Static Drain−Source
On−Resistance
V
V
V
= 10 V, I = 4.5 A
Q1
−
−
−
42
72
55
55
94
75
mW
mW
DS(on)
GS
GS
GS
D
= 10 V, I = 4.5 A, T = 125_C
D
j
= 4.5 V, I = 4 A
D
V
GS
V
GS
V
GS
= −10 V, I = −3.5 A
Q2
−
−
−
82
130
105
105
190
135
D
= −10 V, I = −3.5 A, T = 125_C
D
j
= −4.5 V, I = −3.1 A
D
I
On–State Drain Current
V
V
= 10 V, V = 5 V
Q1
Q2
20
−
−
−
−
A
S
D(on)
GS
GS
DS
= −10 V, V = −5 V
−20
DS
g
FS
Forward Transconductance
V
DS
V
DS
= 10 V, I = 4.5 A
Q1
Q2
−
−
14
9
−
−
D
= −5 V, I = −3.5 A
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
Q1
DS
f = 1.0 Mhz
Q1
Q2
−
−
650
759
−
−
pF
pF
pF
iss
V
= 25 V, V = 0 V,
GS
C
Output Capacitance
Q1
Q2
−
−
80
90
−
−
oss
Q2
V
DS
= −30 V, V = 0 V,
GS
C
Reverse Transfer Capacitance
Q1
Q2
−
−
35
39
−
−
rss
f = 1.0 MHz
SWITCHING CHARACTERISTICS (Note 2)
t
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Q1
Q1
Q2
−
−
11
7
20
14
ns
ns
d(on)
V
DD
V
GS
= 30 V, I = 1 A,
D
= 10 V, R
= 6 W
GEN
t
r
Q1
Q2
−
−
8
10
18
20
Q2
V
DD
V
GS
= −30 V, I = −1 A,
D
t
Q1
Q2
−
−
19
19
35
34
ns
d(off)
= −10 V, R
= 6 W
GEN
t
f
Q1
Q2
−
−
6
12
15
22
ns
Q
Q1
Q1
Q2
−
−
12.5
15
18
21
nC
nC
nC
g
V
DD
V
GS
= 30 V, I = 4.5 A,
D
= 10 V
Q
Q1
Q2
−
−
2.4
2.5
−
−
gs
Q2
V
= −30 V, I = −3.5 A,
Q
Q1
Q2
−
−
2.6
3.0
−
−
DD
GS
D
gd
V
= −10 V
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2
FDS4559
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
DRAIN–SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
Maximum Continuous Drain–Source Diode Forward Current
Q1
Q2
−
−
−
−
1.3
A
V
S
−1.3
V
SD
Drain–Source Diode
Forward Voltage
V
GS
V
GS
= 0 V, I = 1.3 A
(Note 2)
(Note 2)
Q1
Q2
−
−
0.8
−0.8
1.2
−1.2
S
= 0 V, I = −1.3 A
S
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
q
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design.
q
q
JC
CA
b) 125°C/W when mounted
c) 135°C/W when mounted
a) 78°C/W when
mounted on a 0.5 in
pad of 2 oz copper
2
on a .02 in pad of 2 oz
2
on a minimum pad
copper
Scale 1:1 on letter size paper
2. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%
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3
FDS4559
TYPICAL CHARACTERISTICS (Q2 P−CHANNEL)
1.8
15
12
9
V
GS
= −10 V
−6.0 V
−5 V
−4.5 V
V
GS
= −3.5 V
1.6
1.4
−4.0 V
−4.5 V
−3.5 V
−4 V
−5 V
−6.0 V
−3.0 V
−2.5 V
1.2
1
6
3
0
−10.0 V
−8.0 V
−7.0 V
0.8
1
5
4
2
2
4
6
8
0
3
0
10
−I DRAIN CURRENT (A)
D,
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 2. On−Resistance Variation with
Figure 1. On−Region Characteristics
Drain Current and Gate Voltage
2
1.8
1.6
1.4
1.2
1
0.4
I
D
= −1.5 A
I
V
= −3.5 A
D
= −10 V
GS
0.3
0.2
T = 125°C
A
0.8
0.6
0.4
0.1
0
T = 25°C
A
150 175
125
T , JUNCTION TEMPERATURE (°C)
8
−50 −25
0
25
50
100
6
75
4
2
10
−V , GATE TO SOURCE VOLTAGE (V)
J
GS
Figure 3. On−Resistance Variation with
Figure 4. On−Resistance Variation with
Gate−to−Source Voltage
Temperature
100
10
1
15
12
V
DS
= −5 V
V
GS
= 0 V
T = −55°C
A
25°C
9
6
3
0
125°C
T = 125°C
A
0.1
0.01
25°C
−55°C
0.001
2
1
1.4
1.2
1
3
4
0.4
0.6
5
0
0.2
0.8
−V , GATE TO SOURCE VOLTAGE (V)
GS
−V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage
Variation with Source Current and Temperature
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4
FDS4559
TYPICAL CHARACTERISTICS (Q2 P−CHANNEL) (continued)
1200
10
8
I
D
= −3.0 A
V
DS
= 10 V
f = 1 MHz
= 0 V
V
GS
1000
800
600
400
200
0
C
ISS
20 V
6
4
30 V
C
OSS
2
0
C
RSS
0
4
12
16
8
50
60
30
0
10
20
40
Q , GATE CHARGE (nC)
g
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 8. Capacitance Characteristics
Figure 7. Gate Charge Characteristics
100
10
1
40
30
20
SINGLE PULSE
R
= 135°C/W
θ
JA
R
Limit
100 μs
DS(ON)
T = 25°C
A
10 ms
100 ms
1 s
10 s
VGS = −10 V
SINGLE PULSE
DC
0.1
10
0
R
= 135°C/W
θ
JA
T = 25°C
A
0.01
0.1
1
0.01
10
t , TIME (s)
1000
100
0.1
1
10
100
−V , DRAIN−SOURCE VOLTAGE (V)
DS
1
Figure 10. Single Pulse Maximum Power
Dissipation
Figure 9. Maximum Safe Operating Area
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5
FDS4559
TYPICAL CHARACTERISTICS (Q1 N−CHANNEL)
20
16
1.8
V
GS
= 10 V
6.0 V
5 V
V
GS
= 4.0 V
1.6
1.4
1.2
1
4.5 V
4.0 V
3.5 V
4.5 V
12
8
5.0 V
6.0 V
8.0 V
10 V
4
0
0.8
1
4
4
0
2
3
8
16
0
12
20
I
D,
DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 12. On−Resistance Variation with
Figure 11. On−Region Characteristics
Drain Current and Gate Voltage
0.14
2.2
I
D
= 2.3 A
I
V
= 4.5 A
= 10 V
D
2
0.12
0.1
GS
1.8
1.6
1.4
1.2
1
T = 125°C
A
0.08
0.06
0.04
T = 25°C
A
0.8
0.6
0.4
0.02
0
150 175
125
T , JUNCTION TEMPERATURE (°C)
8
−50 −25
0
25
50
100
6
75
4
2
10
V
, GATE TO SOURCE VOLTAGE (V)
J
GS
Figure 13. On−Resistance Variation with
Figure 14. On−Resistance Variation with
Gate−to−Source Voltage
Temperature
20
16
100
10
1
T = −55°C
A
V
DS
= 5 V
V
GS
= 0 V
25°C
125°C
12
8
T = 125°C
A
0.1
0.01
4
0
0.001
0.0001
25°C
−55°C
2
1
4
3
5
0.6
1
6
0.4
1.2
0
0.2
0.8
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 16. Body Diode Forward Voltage
Variation with Source Current and Temperature
Figure 15. Transfer Characteristics
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6
FDS4559
TYPICAL CHARACTERISTICS (Q1 N−CHANNEL) (continued)
900
10
8
= 10 V
= 4.5 A
V
f = 1 MHz
V = 0 V
GS
I
DS
D
800
700
C
ISS
20 V
600
500
30 V
6
4
400
300
200
100
0
C
OSS
2
0
C
RSS
2
4
6
10
0
8
12
14
50
, DRAIN TO SOURCE VOLTAGE (V)
60
30
0
10
20
40
Q , GATE CHARGE (nC)
g
V
DS
Figure 18. Capacitance Characteristics
Figure 17. Gate Charge Characteristics
100
10
1
40
30
20
SINGLE PULSE
R
= 135°C/W
θ
JA
R
Limit
DS(ON)
T = 25°C
A
100 μs
1 m
10 ms
100 ms
1 s
V
= 10 V
DC
GS
0.1
10
0
SINGLE PULSE
= 135°C/W
R
θ
JA
T = 25°C
A
0.01
0.1
0.01
1
10
1000
0.1
1
10
100
100
V
DS
, DRAIN−SOURCE VOLTAGE (V)
SINGLE PULSE TIME (s)
Figure 20. Single Pulse Maximum Power
Dissipation
Figure 19. Maximum Safe Operating Area
1
D = 0.5
0.2
R
(t) = r(t) + R
q
JA
q
JA
0.1
R
= 135°C/W
q
JA
0.1
0.05
0.02
0.01
P
(pk)
t
1
0.01
Single Pulse
t
2
T − T = P * R (t)
q
JA
J
A
Duty Cycle, D = t / t
1
2
0.001
0.0001
0.001
100
1000
0.01
1
10
0.1
t , TIME (s)
1
Figure 21. Transient Thermal Response Curve
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
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7
FDS4559
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries.
www.onsemi.com
8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13735G
SOIC8
PAGE 1 OF 1
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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