FDP3682 [ONSEMI]
N 沟道，PowerTrench® MOSFET，100V，32A，36mΩ;
| 型号： | FDP3682 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，PowerTrench® MOSFET，100V，32A，36mΩ |
| 文件： | 总16页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET – N-Channel,
POWERTRENCHꢀ
D
100 V, 32 A, 36 mW
G
G
D
S
FDB3682, FDP3682
S
D2PAK−3
(TO−263, 3−LEAD)
TO−220−3LD
CASE 340AT
Features
CASE 418AJ
• R
• Q
= 32 mW (Typ.) @ V = 10 V, I = 32 A
GS D
DS(on)
G(tot)
= 18.5 nC (Typ.) @ V = 10 V
GS
• Low Miller Charge
MARKING DIAGRAM
• Low Q Body Diode
• UIS Capability (Single Pulse and Repetitive Pulse)
• These Devices are Pb−Free and are RoHS Compliant
rr
XXXXXXXG
AYWW
Applications
• Consumer Appliances
• Synchronous Rectification
• Battery Protection Circuit
• Motor Drives and Uninterruptible Power Supplies
• Micro Solar Inverter
XXXXXX = Specific Device Code
(FDB3862 or FDP3862)
A
= Assembly Location
= Year
Y
WW
G
= Work Week
= Pb−Free Package
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
FDB3682 /
FDP3682
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Unit
V
V
DSS
100
SCHEMATIC
V
GS
20
V
D
I
D
Drain
Current
Continuous
C
32
A
(T = 25°C, V = 10 V)
GS
G
Continuous
C
23
6
A
A
(T = 100°C, V = 10 V)
GS
S
Continuous (T
= 25°C,
= 43°C/W)
amb
V
GS
= 10 V, R
q
JA
Pulsed
Figure 4
55
A
mJ
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
E
Single Pulse Avalanche Energy (Note 1)
Power Dissipation
AS
P
95
W
D
Derate above 25°C
0.63
mW/°C
°C
T , T
Operating and Storage Temperature
–55 to 175
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Starting T = 25°C, L = 0.27 mH, I = 20 A.
J
AS
© Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
March, 2022 − Rev. 3
FDP3682/D
FDB3682, FDP3682
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
1.58
62
Unit
°C/W
°C/W
°C/W
R
q
JC
R
q
JA
R
q
JA
Thermal Resistance, Junction to Case TO−220, TO−263, Max.
Thermal Resistance, Junction to Ambient TO−220, TO−263 (Note 2), Max.
2
Thermal Resistance, Junction to Ambient TO−263, 1 in copper pad area, Max.
43
2. Pulse Width = 100 s
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
I
= 250 mA, V = 0 V
100
V
VDSS
D
GS
I
V
V
V
= 80 V, V = 0 V
1
mA
DSS
DS
DS
GS
GS
= 80 V, V = 0 V, T = 150_C
250
100
GS
C
I
Gate to Source Leakage Current
=
20 V
nA
GSS
ON CHARACTERISTICS
V
GS(TH)
R
DS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
= V , I = 250 mA
2
4
V
GS
DS
D
I
D
I
D
I
D
= 32 A, V = 10 V
0.032
0.040
0.080
0.036
0.060
0.090
W
GS
= 16 V, V = 6 V
GS
= 32 A, V = 10 V, T = 175 °C
GS
C
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 25 V, V = 0 V, f = 1 MHz
1250
190
45
pF
pF
pF
nC
ISS
DS
GS
C
Output Capacitance
OSS
RSS
C
Reverse Transfer Capacitance
Total Gate Charge at 10 V
Q
V
GS
V
DD
= 0 V to 10 V,
18.5
28
g(TOT)
= 50 V, I = 32 A, I = 1.0 mA
D
g
Q
Threshold Gate Charge
V
GS
V
DD
= 0 V to 2 V,
2.4
3.6
nC
g(TH)
= 50 V, I = 32 A, I = 1.0 mA
D
g
Q
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V
DD
= 50 V, I = 32 A, I = 1.0 mA
6.5
4.1
4.6
nC
nC
nC
gs
D
g
Q
gs2
Q
gd
RESISTIVE SWITCHING CHARACTERISTICS (V = 10 V)
GS
t
Turn-On Time
Turn-On Delay Time
Rise Time
V
DD
V
GS
= 50 V, I = 32 A,
83
87
ns
ns
ns
ns
ns
ns
ON
D
= 10 V, R = 16 W
GS
t
9
d(ON)
t
r
46
26
32
t
Turn-Off Delay Time
Fall Time
d(OFF)
t
f
t
Turn-Off Time
OFF
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Voltage
I
I
I
I
= 32 A
= 16 A
1.25
1.0
55
V
V
SD
SD
SD
SD
SD
t
Reverse Recovery Time
= 32 A, dl /dt = 100 A/ms
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 32 A, dl /dt = 100 A/ms
90
RR
SD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDB3682, FDP3682
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
C
1.2
1.0
0.8
0.6
0.4
0.2
0
35
30
25
20
15
10
5
V
= 10 V
GS
0
0
25
50
75
100 125
150
175
25
50
75
100
125
150
175
T , CASE TEMPERATURE (°C)
C
T , CASE TEMPERATURE (°C)
C
Figure 1. Normalized Power Dissipation vs.
Case Temperature
Figure 2. Maximum Continuous Drain Current vs.
Case Temperature
2
DUTY CYCLE − DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
x Z
x R
+ T
qJC C
J
DM
qJC
0.01
10−4
10−3
10−2
10−1
100
101
10−5
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
400
o
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T
= 25 C
C
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
o
CURRENT AS FOLLOWS:
175 − T
C
I = I
25
V
= 10V
GS
150
100
30
10−5
10−4
10−3
10−2
10−1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
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3
FDB3682, FDP3682
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted) (continued)
C
100
200
100
10 ms
If R = 0
t
AV
= (L)(I )/(1.3*RATED BV
− V
)
AS
DSS
DD
If R ꢁ 0
100 ms
1 ms
10 ms
t
= (L/R)ln[(I *R)/(1.3*RATED BV
− V ) +1]
AV
AS
DSS DD
10
o
STARTING T = 25 C
J
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1
o
SINGLE PULSE
STARTING T = 150 C
DC
J
T
= MAX RATED
J
o
T
= 25 C
C
1
0.1
200
0.001
0.01
0.1
1
1
10
100
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
t , TIME IN AVALANCHE (ms)
AV
NOTE: Refer to onsemi Application Notes AN−7514 and AN−7515
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching Capability
80
80
PULSE DURATION = 80 ms
V
= 20 V
GS
DUTY CYCLE = 0.5% MAX
DD
V
= 10 V
= 6 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
GS
V
= 15 V
60
40
20
0
60
40
20
0
o
T
= 25 C
C
V
GS
o
T
= 175 C
J
o
T
= 25 C
J
o
V
= 5 V
T
= −55 C
GS
J
0
1
2
3
4
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
, GATE TO SOURCE VOLTAGE (V)
V
GS
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
60
50
40
30
20
3.0
2.5
2.0
1.5
1.0
0.5
PULSE DURATION = 80 ms
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
V
= 6 V
GS
V
= 10 V
GS
V
= 10V, I = 32A
D
GS
0
5
10
15
20
25
30
35
−80 −40
0
40
80
120 160 200
I , DRAIN CURRENT (A)
D
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Drain to Source On Resistance
vs. Drain Current
Figure 10. Normalized Drain to Source
On Resistance vs. Junction Temperature
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4
FDB3682, FDP3682
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted) (continued)
J
1.2
1.2
1.0
0.8
0.6
0.4
V
= V , I = 250 mA
DS D
GS
I
= 250 mA
D
1.1
1.0
0.9
−80 −40
0
40
80
120 160 200
−80 −40
0
40
80
120 160 200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Normalized Gate Threshold Voltage
vs. Junction Temperature
Figure 12. Normalized Drain to Source Breakdown
Voltage vs. Junction Temperature
10
2000
1000
V
= 50 V
DD
C
= C + C
GS GD
8
6
4
2
0
ISS
C
C
C
+ C
@
OSS
DS GD
= C
RSS
GD
100
20
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 32 A
= 16 A
D
D
V
= 0 V, f = 1 MHz
GS
0
5
10
15
20
0.1
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 13. Capacitance vs. Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
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FDB3682, FDP3682
TEST CIRCUITS AND WAVEFORMS
VDS
BVDSS
tP
VDS
L
IAS
VDD
VARY t TO OBTAIN
P
+
VDD
−
REQUIRED PEAK I
RG
AS
VGS
DUT
t P
IAS
0.01 W
0 V
0
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS = 10 V
VGS
+
VDD
VGS
−
DUT
VGS = 2 V
Qgs2
Qgs
0
Ig(REF)
Qg(TH)
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
tON
td(ON)
tOFF
td(OFF)
VDS
t
t
f
r
RL
VDS
90%
90%
+
VGS
VDD
−
10%
10%
0
90%
50%
DUT
RGS
VGS
50%
PULSE WIDTH
10%
0
VGS
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
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FDB3682, FDP3682
THERMAL RESISTANCE VS. MOUNTING PAD AREA
The maximum rated junction temperature, T , and the
junction temperature or power dissipation. Pulse
JM
thermal resistance of the heat dissipating path determines
applications can be evaluated using the onsemi device Spice
thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
the maximum allowable device power dissipation, P , in
DM
an application. Therefore the application’s ambient
temperature, T (°C), and thermal resistance R
(°C/W)
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
A
qJA
must be reviewed to ensure that T is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(TJM * TA)
PDM
+
(eq. 1)
RqJA
19.84
In using surface mount devices such as the TO−263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
RqJA + 26.51 )
(eq. 2)
0.262 ) Area
2
Area in in .
128
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
is
DM
RqJA + 26.51 )
(eq. 3)
1.69 ) Area
2
1. Mounting pad area onto which the device is
Area in cm .
attached and whether there is copper on one side
or both sides of the board.
2. The number of copper layers and the thickness of
the board.
3. The use of external heat sinks.
4. The use of thermal vias.
80
60
40
R
= 26.51+ 19.84/(0.262+Area) EQ.2
QJA
R
= 26.51+ 128/(1.69+Area) EQ.3
QJA
5. Air flow and board orientation.
6. For non steady state applications, the pulse width,
the duty cycle and the transient thermal response of
the part, the board and the environment they are in.
onsemi provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
20
defines the R for the device as a function of the top copper
qJA
0.1
1
10
(component side) area. This is for a horizontally positioned
FR−4 board with 1 oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
(0.645)
(6.45)
(64.5)
2
2
AREA, TOP COPPER AREA in (cm )
Figure 21. Thermal Resistance vs. Mounting Pad Area
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FDB3682, FDP3682
PSPICE ELECTRICAL MODEL
.SUBCKT FDB3682 2 1 3 ; rev May 2002
Ca 12 8 4e−10
Cb 15 14 5.5e−10
Cin 6 8 1.22e−9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 108
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.96e−9
Ldrain 2 5 1.0e−9
Lsource 3 7 3.19e−9
RLgate 1 9 59.6
RLdrain 2 5 10
RLsource 3 7 31.9
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 10.5e−3
Rgate 9 20 1.86
RSLC1 5 51 RSLCMOD 1.0e−6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 11.9e−3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*70),2.5))}
.MODEL DbodyMOD D (IS=2.4E−12 RS=4.4e−3 TRS1=2.0e−3 TRS2=4.5e−7
+ CJO=9e−10 M=0.57 TT=2.9e−8 XTI=4.0)
.MODEL DbreakMOD D (RS=0.6 TRS1=1.4e−3 TRS2=−5.0e−5)
.MODEL DplcapMOD D (CJO=2.7e−10 IS=1.0e−30 N=10 M=0.56)
.MODEL MstroMOD NMOS (VTO=4.16 KP=32 IS=1e−30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=3.48 KP=2.7 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=1.86)
.MODEL MweakMOD NMOS (VTO=2.97 KP=0.04 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=18.6 RS=0.1)
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FDB3682, FDP3682
.MODEL RbreakMOD RES (TC1=1.05e−3 TC2=−1.1e−8)
.MODEL RdrainMOD RES (TC1=1.6e−2 TC2=4e−5)
.MODEL RSLCMOD RES (TC1=3.0e−3 TC2=2.9e−6)
.MODEL RsourceMOD RES (TC1=1e−3 TC2=1e−6)
.MODEL RvthresMOD RES (TC1=−4.1e−3 TC2=−1.4e−5)
.MODEL RvtempMOD RES (TC1=−3.5e−3 TC2=1.3e−6)
.MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−5.0 VOFF=−2.0)
.MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−2.0 VOFF=−5.0)
.MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−0.4 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=0.3 VOFF=−0.4)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written
by William J. Hepp and C. Frank Wheatley.
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
DBODY
RSLC1
DBREAK
11
51
+
RSLC2
5
51
ESLC
−
+
50
−
17
18
−
RDRAIN
6
8
EBREAK
MWEAK
ESG
EVTHRES
+
16
21
+
−
19
8
LGATE
EVTEMP
RGATE
GATE
1
+
6
−
18
22
MMED
9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
−
S1B
S2B
13
CB
CA
IT
14
+
+
6
8
VBAT
5
8
EGS
EDS
+
−
−
8
22
RVTHRES
Figure 22.
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FDB3682, FDP3682
SABER ELECTRICAL MODEL
REV May 2002
template FDB3682 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e−12,rs=4.4e−3,trs1=2.0e−3,trs2=4.5e−7,cjo=9e−10,m=0.57,tt=2.9e−8,xti=4.0)
dp..model dbreakmod = (rs=0.6,trs1=1.4e−3,trs2=−5e−5)
dp..model dplcapmod = (cjo=2.7e−10,isl=10e−30,nl=10,m=0.56)
m..model mstrongmod = (type=_n,vto=4.16,kp=32,is=1e−30, tox=1)
m..model mmedmod = (type=_n,vto=3.48,kp=2.7,is=1e−30, tox=1)
m..model mweakmod = (type=_n,vto=2.97,kp=0.04,is=1e−30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−5,voff=−2)
sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−2,voff=−5)
sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−0.4,voff=0.3)
sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=0.3,voff=−0.4)
c.ca n12 n8 = 4e−10
c.cb n15 n14 = 5.5e−10
c.cin n6 n8 = 1.22e−9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 108
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.96e−9
l.ldrain n2 n5 = 1.0e−9
l.lsource n3 n7 = 3.19e−9
res.rlgate n1 n9 = 59.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 31.9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=1.05e−3,tc2=−1.1e−8
res.rdrain n50 n16 = 10.5e−3, tc1=1.6e−2,tc2=4e−5
res.rgate n9 n20 = 1.86
res.rslc1 n5 n51 = 1.0e−6, tc1=3.0e−3,tc2=2.9e−6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 11.9e−3, tc1=1e−3,tc2=1e−6
res.rvthres n22 n8 = 1, tc1=−4.1e−3,tc2=−1.4e−5
res.rvtemp n18 n19 = 1, tc1=−3.5e−3,tc2=1.3e−6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
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10
FDB3682, FDP3682
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 2.5))
}
}
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
DBREAK
50
−
RDRAIN
6
8
11
ESG
DBODY
EVTHRES
+
16
21
+
−
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
6
+
−
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
−
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
−
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
−
−
8
22
RVTHRES
Figure 23.
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11
FDB3682, FDP3682
JUNCTION
th
SPICE THERMAL MODEL
REV 20 May 2002
FDB3682_JC TH TL
RTHERM1
CTHERM1
CTHERM1 TH 6 1.6e−3
CTHERM2 6 5 4.5e−3
CTHERM3 5 4 5.0e−3
CTHERM4 4 3 8.0e−3
CTHERM5 3 2 8.2e−3
CTHERM6 2 TL 4.7e−2
6
5
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 TH 6 3.3e−2
RTHERM2 6 5 7.9e−2
RTHERM3 5 4 9.5e−2
RTHERM4 4 3 1.4e−1
RTHERM5 3 2 2.9e−1
RTHERM6 2 TL 6.7e−1
4
3
2
SABER THERMAL MODEL
SABER thermal model FDB3682
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1.6e−3
ctherm.ctherm2 6 5 =4.5e−3
ctherm.ctherm3 5 4 =5.0e−3
ctherm.ctherm4 4 3 =8.0e−3
ctherm.ctherm5 3 2 =8.2e−3
ctherm.ctherm6 2 tl =4.7e−2
rtherm.rtherm1 th 6 =3.3e−2
rtherm.rtherm2 6 5 =7.9e−2
rtherm.rtherm3 5 4 =9.5e−2
rtherm.rtherm4 4 3 =1.4e−1
rtherm.rtherm5 3 2 =2.9e−1
rtherm.rtherm6 2 tl =6.7e−1
}
tl
CASE
Figure 24.
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12
FDB3682, FDP3682
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
Device Marking
Package Type
Shipping
FDB3682
FDP3682
FDB3682
FDP3682
D2PAK−3 (TO−263) (Pb−Free)
TO−220−3LD (Pb−Free)
800 / Tape & Reel
800 / Tube
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220−3LD
CASE 340AT
ISSUE A
DATE 03 OCT 2017
Scale 1:1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13818G
TO−220−3LD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
DATE 11 MAR 2021
SCALE 1:1
XXXXXX = Specific Device Code
A
= Assembly Location
WL
Y
= Wafer Lot
= Year
GENERIC MARKING DIAGRAMS*
WW
W
M
G
AKA
= Work Week
= Week Code (SSG)
= Month Code (SSG)
= Pb−Free Package
= Polarity Indicator
XX
AYWW
XXXXXXXXG
AKA
XXXXXXXXG
AYWW
XXXXXX
XXYMW
XXXXXXXXX
AWLYWWG
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
IC
Standard
Rectifier
SSG
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON56370E
D2PAK−3 (TO−263, 3−LEAD)
PAGE 1 OF 1
DESCRIPTION:
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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