FDMS86202 [ONSEMI]
N 沟道，屏蔽门极，PowerTrench® MOSFET，120V，64A，7.2mΩ;
| 型号： | FDMS86202 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，屏蔽门极，PowerTrench® MOSFET，120V，64A，7.2mΩ |
| 文件： | 总8页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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July 2014
FDMS86202
N-Channel Shielded Gate PowerTrench® MOSFET
120 V, 64 A, 7.2 mΩ
Features
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized for the on-state resistance and yet maintain superior
switching performance.
Shielded Gate MOSFET Technology
Max rDS(on) = 7.2 mΩ at VGS = 10 V, ID = 13.5 A
Max rDS(on) = 10.3 mΩ at VGS = 6 V, ID = 11.5 A
Advanced Package and Silicon combination for low rDS(on)
and high efficiency
Application
MSL1 robust package design
100% UIL tested
DC-DC Conversion
RoHS Compliant
Bottom
Top
Pin 1
S
S
D
D
D
D
S
Pin 1
S
G
S
S
G
D
D
D
D
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
120
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
V
V
±20
TC = 25 °C
TA = 25 °C
64
ID
(Note 1a)
(Note 4)
(Note 3)
13.5
A
-Pulsed
240
EAS
Single Pulse Avalanche Energy
Power Dissipation
600
mJ
W
TC = 25 °C
TA = 25 °C
156
PD
Power Dissipation
(Note 1a)
2.7
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
0.8
45
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS86202
FDMS86202
Power 56
3000 units
©2013 Fairchild Semiconductor Corporation
FDMS86202 Rev. C3
www.fairchildsemi.com
1
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
120
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
I
D = 250 μA, referenced to 25 °C
103
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 96 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
1
μA
±100
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
2.0
3.1
-10
4.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
I
D = 250 μA, referenced to 25 °C
mV/°C
V
GS = 10 V, ID = 13.5 A
6.0
8.1
7.2
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 6 V, ID = 11.5 A
10.3
13.2
mΩ
VGS = 10 V, ID = 13.5 A,TJ = 125 °C
VDS = 5 V, ID = 13.5 A
10.9
44
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
3195
449
17
4250
600
30
pF
pF
pF
Ω
VDS = 60 V, VGS = 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
0.1
0.9
2.7
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
21
6
33
13
44
11
64
41
ns
ns
VDD = 60 V, ID = 13.5 A,
V
GS = 10 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
27
5
ns
ns
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
VGS = 0 V to 6 V
45
29
14.3
8.7
nC
nC
nC
nC
Qg
VDD = 60 V,
D = 13.5 A
I
Qgs
Qgd
Drain-Source Diode Characteristics
V
GS = 0 V, IS = 2.1 A
(Note 2)
(Note 2)
0.69
0.76
73
1.2
1.3
VSD
Source to Drain Diode Forward Voltage
V
VGS = 0 V, IS = 13.5 A
trr
Reverse Recovery Time
118
187
ns
IF = 13.5 A, di/dt = 100 A/μs
Qrr
Reverse Recovery Charge
117
nC
Notes:
2
1. R
is determined with the device mounted on a 1in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined by
θCA
θJA
θJC
the user's board design.
b)
115 °C/W when mounted on a
minimum pad of 2 oz copper.
a)
45 °C/W when mounted on a
1 in pad of 2 oz copper
2
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. E of 600 mJ is based on starting T = 25 °C, L = 3 mH, I = 20 A, V = 120 V, V = 10 V. 100% test at L = 0.1 mH, I = 65 A.
AS
J
AS
DD
GS
AS
4. Pulse Id limited by junction temperature, td ≤ 100 μs, please refer to SOA curve for more details.
©2013 Fairchild Semiconductor Corporation
FDMS86202 Rev. C3
www.fairchildsemi.com
2
Typical Characteristics TJ = 25 °C unless otherwise noted
240
5
4
3
2
1
0
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 5 V
VGS = 8 V
180
VGS = 6 V
VGS = 7 V
VGS = 6 V
120
VGS = 7 V
VGS = 8 V
60
VGS = 5 V
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
4
5
0
60
120
180
240
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs Drain Current and Gate Voltage
Figure 1. On Region Characteristics
2.4
40
ID = 13.5 A
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
30
20
10
0
ID = 13.5 A
TJ = 125 o
C
TJ = 25 o
C
4
5
6
7
8
9
10
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
240
300
VGS = 0 V
100
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
180
120
60
10
VDS = 10 V
TJ = 150 o
C
1
TJ = 150 o
C
TJ = 25 oC
0.1
TJ = 25 o
C
0.01
TJ = -55 o
C
TJ = -55 o
C
0
0.001
0.0
0.2
0.4
0.6
0.8
1.0
1.2
2
3
4
5
6
7
8
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2013 Fairchild Semiconductor Corporation
FDMS86202 Rev. C3
www.fairchildsemi.com
3
Typical Characteristics TJ = 25 °C unless otherwise noted
10
10000
1000
100
10
ID = 13.5 A
VDD = 35 V
Ciss
8
6
4
2
0
VDD = 60 V
Coss
VDD = 85 V
Crss
f = 1 MHz
= 0 V
V
GS
1
0
10
20
30
40
50
0.1
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
100
80
60
40
20
0
100
10
1
TJ = 25 o
C
VGS = 10 V
Limited by Package
TJ = 100 oC
VGS = 6 V
TJ = 125 o
C
RθJC = 0.8 oC/W
50
25
75
100
125
150
0.01
0.1
1
10
100
1000
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs Case Temperature
1000
100
10
50000
SINGLE PULSE
θJC = 0.8 oC/W
TC = 25 oC
R
10 us
10000
1000
100
THIS AREA IS
LIMITED BY rDS(on)
100 us
1 ms
SINGLE PULSE
TJ = MAX RATED
RθJC = 0.8 oC/W
TC = 25 oC
1
CURVE BENT TO
MEASURED DATA
10 ms
DC
0.1
0.1
10-5
10-4
10-3
t, PULSE WIDTH (sec)
10-2
10-1
1
10
100
400
1
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure12. Single Pulse Maximum
Power Dissipation
©2013 Fairchild Semiconductor Corporation
FDMS86202 Rev. C3
www.fairchildsemi.com
4
Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
P
0.1
DM
0.05
0.02
0.1
t
0.01
1
t
2
NOTES:
(t) = r(t) x R
0.01
Z
θJC
θJC
o
R
= 0.8 C/W
θJC
SINGLE PULSE
Peak T = P
x Z (t) + T
J
DM
θJC C
Duty Cycle, D = t / t
1
2
0.001
10-5
10-4
10-3
10-2
10-1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
©2013 Fairchild Semiconductor Corporation
FDMS86202 Rev. C3
www.fairchildsemi.com
5
5.10
4.90
A
4.42
3.81
PKG
C
L
B
7
6
5
8
8
5
1.14
KEEP OUT AREA
3.65
6.25
5.90
C
PKG
L
6.61
4.79
1.27
1
4
PIN #1
IDICATOR
TOP VIEW
SIDE VIEW
1
2
1.27
3
4
0.61
SEE
DETAIL A
3.81
5.10
LAND PATTERN
RECOMMENDATION
3.81
1.27
0.10
C A B
0.47
0.37
(0.38)
(8X)
1
4
(0.35)
0.65
0.55
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
PIN #1
INDICATOR
4.66
4.46
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08JREV3.
8
5
0.70
4.33
4.13
BOTTOM VIEW
0.10 C
1.10
0.90
0.08 C
C
0.05
0.00
0.25
0.15
SEATING
PLANE
SCALE: 2:1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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