FDMS4D5N08LC [ONSEMI]
Power MOSFET 80V Single N Channel, 116A, 4.2mΩ in Power 56 Package.;
| 型号： | FDMS4D5N08LC |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 80V Single N Channel, 116A, 4.2mΩ in Power 56 Package. 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总7页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FDMS4D5N08LC
MOSFET, N-Channel
Shielded Gate,
POWERTRENCH)
80 V, 116 A, 4.2 mW
www.onsemi.com
General Description
This N−Channel MV MOSFET is produced using
ON Semiconductor’s advanced POWERTRENCH process that
ELECTRICAL CONNECTION
®
incorporates Shielded Gate technology. This process has been
optimized to minimise on−state resistance and yet maintain superior
switching performance with best in class soft body diode.
G
S
S
S
D
D
D
D
5
6
7
8
4
3
2
1
Features
• Shielded Gate MOSFET Technology
• Max r
• Max r
= 4.2 mW at V = 10 V, I = 37 A
GS D
DS(on)
= 6.1 mW at V = 4.5 V, I = 29 A
DS(on)
GS
D
N-Channel MOSFET
• 50% Lower Qrr than Other MOSFET Suppliers
• Lowers Switching Noise/EMI
• MSL1 Robust Package Design
• 100% UIL Tested
D
D
D
D
G
S
S
S
• RoHS Compliant
Pin 1
Top
Typical Applications
Bottom
• Primary DC−DC MOSFET
• Synchronous Rectifier in DC−DC and AC−DC
• Motor Drive
Power 56
(PQFN8 5x6)
CASE 483AE
• Solar
MARKING DIAGRAM
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current − Continuous T = 25°C (Note 5)
Ratings Unit
$Y&Z&3&K
FDMS
4D5N08LC
V
DS
V
GS
80
20
V
V
A
I
D
116
73
C
− Continuous T = 100°C
C
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
(Note 5)
− Continuous T = 25°C
17
A
(Note 1a)
FDMS4D5N08LC = Specific Device Code
− Pulsed (Note 4)
633
384
E
AS
Single Pulse Avalanche Energy
Power dissipation T = 25°C
(Note 3)
mJ
W
P
D
113.6
2.5
ORDERING INFORMATION
See detailed ordering and shipping information on page 2
of this data sheet.
C
Power dissipation T = 25°C (Note 1a)
A
T
STG
Operating and Storage Junction Temperature
Range
−55 to
+150
°C
J,
T
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
November, 2018 − Rev. 0
FDMS4D5N08LC/D
FDMS4D5N08LC
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
1.1
Unit
°C/W
R
R
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient (Note 1a)
q
q
JC
JA
50
PACKAGE MARKING AND ORDERING INFORMATION
†
Device Marking
Device
Package
Shipping
FDMS4D5N08LC
FDMS4D5N08LC
PQFN8 5×6
(Pb−Free/Halogen Free)
3000 Units/
Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= 250 mA, V = 0 V
80
V
DSS
D
GS
Breakdown Voltage Temperature
Coefficient
= 250 mA, referenced to 25°C
66
DBVDSS
DTJ
D
mV/°C
I
Zero Gate Voltage Drain Current
V
V
= 64 V, V = 0 V
1
mA
DSS
DS
GS
I
Gate−to−Source Leakage Current
=
20 V, V = 0 V
100
nA
GSS
GS
DS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
V
I
= V , I = 210 mA
1.0
1.4
2.5
V
GS(th)
GS
DS
D
Gate to Source Threshold Voltage
Temperature Coefficient
= 210 mA, referenced to 25°C
−5.1
DVGS(th)
DTJ
D
mV/°C
mW
r
Static Drain to Source On Resistance
Forward Transconductance
V
GS
V
GS
V
GS
V
DS
= 10 V, I = 37 A
3.2
4.5
5.7
135
4.2
6.1
7.5
DS(on)
D
= 4.5 V, I = 29 A
D
= 10 V, I = 37 A, T = 125°C
D
J
g
FS
= 5 V, I = 37 A
S
D
DYNAMIC CHARACTERISTICS
C
C
Input Capacitance
V
DS
= 40 V, V = 0 V, f = 1MHz
3640
834
39
5100
1170
65
iss
GS
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
pF
W
oss
C
rss
R
0.1
0.6
1.1
g
SWITCHING CHARACTERISTICS
V
V
= 40 V, I = 37 A,
ns
td
t
Turn*On Delay Time
Rise Time
13
19
59
17
51
24
8
23
34
94
30
71
34
DD
GS
D
(on)
= 10 V, R
= 6 W
GEN
t
r
Turn*Off Delay Time
Fall Time
D(off)
t
f
V
V
= 0V to 10 V
= 0V to 4.5 V
Q
Q
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
Output Charge
nC
nC
GS
g
g
GS
V
D
= 40 V,
DD
Q
gs
gd
i
= 37 A
Q
6
Q
V
V
= 40 V, V = 0 V
51
46
oss
DD
GS
Q
Total Gate Charge Sync.
= 0 V, I = 37 A
D
sync
DS
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2
FDMS4D5N08LC
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Forward Voltage
V
V
= 0 V, I = 2.1 A (Note 2)
0.7
0.8
22
38
17
82
1.2
1.3
36
V
SD
GS
S
= 0 V, I = 37 A (Note 2)
GS
S
t
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
I = 18 A, di/dt = 300 A/ms
F
ns
nC
ns
rr
Q
61
rr
t
I = 18 A, di/dt = 1000 A/ms
F
27
rr
Q
132
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTES:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 × 1.5 in. board of FR−4 material. R
is determined
CA
q
q
JA
by the user’s board design.
a) 50°C/W when mounted on
b) 125°C/W when mounted on
a minimum pad of 2 oz copper.
2
a 1 in pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. E of 384 mJ is based on starting T = 25_C; N−ch: L = 3 mH, I = 16 A, V = 72 V, V = 10 V. 100% tested at L = 0.1 mH, I = 41 A,
AS
GS
J
AS
DD
GS
AS
V
= 10 V.
4. Pulsed I please refer to Figure 11 SOA graph for more details.
D
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal &
electro−mechanical application board design.
TYPICAL CHARACTERISTICS T = 25°C unless otherwise noted
J
250
200
150
100
50
5
4
3
2
1
0
V
= 10 V
GS
V
= 4.5 V
V
= 3 V
GS
GS
V
= 8 V
GS
V
= 3.5 V
V
= 4 V
GS
GS
V
= 4 V
GS
V
= 6 V
GS
V
= 3.5 V
GS
V
= 4.5 V
= 6 V
GS
V
GS
V
= 3 V
GS
V
= 10 V
GS
PULSE DURATIONV = 80 ms
DUTY CYCLE = 0.5% MAX
PULSE DURATIONV = 80 ms
DUTY CYCLE = 0.5% MAX
V
= 8 V
GS
0
0
1
2
3
4
5
0
70
140
210
280
V
DS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
Figure 2. Normalized On−Resistance
vs. Drain Current and Gate Voltage
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3
FDMS4D5N08LC
TYPICAL CHARACTERISTICS T = 25°C unless otherwise noted (continued)
J
2.1
1.8
1.5
1.2
40
PULSE DURATIONV = 80 ms
DUTY CYCLE = 0.5% MAX
I
V
= 37 A
D
= 10 V
GS
I
D
= 37 A
30
20
10
T
= 125°C
J
0.9
0.6
T
= 25°C
J
0
1
2
3
4
5
6
7
8
9
10
−75 −50 −25
0
25
50
75 100 125 150
TJ, JUNCTION TEMPERATURE ( oC)
V
GS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs. Junction Temperature
Figure 4. On−Resistance vs. Gate
to Source Voltage
280
210
140
70
280
V
= 0 V
GS
PULSE DURATIONV = 80 ms
DUTY CYCLE = 0.5% MAX
100
10
1
V
= 5 V
DS
T
= 150°C
J
T
= 25°C
J
0.1
T
= 150°C
J
0.01
T
= 25°C
J
T
= −55°C
J
T
= −55°C
J
0
0.001
1
2
3
4
5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward
Voltage vs. Source Current
10
8
10000
C
I
D
= 37 A
iss
V
= 30 V
DD
1000
C
oss
V
= 40 V
DD
6
100
10
1
V
= 50 V
DD
4
C
rss
2
f = 1 Mhz
= 0 V
V
GS
0
0
10
20
30
40
50
60
0.1
1
10
80
Qg, GATE CHARGE (nC)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Capacitance vs. Drain
to Source Voltage
Figure 7. Gate Charge Characteristics
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4
FDMS4D5N08LC
TYPICAL CHARACTERISTICS T = 25°C unless otherwise noted (continued)
J
100
10
1
120
90
R
= 1.1°C/W
q
JC
V
= 10 V
GS
T
= 25°C
J
60
30
0
V
= 4.5 V
GS
T
= 100°C
J
T
= 125°C
J
0.001
0.01
0.1
1
10
100
1000
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure 9. Unclamped Inductive
Switching Capability
Figure 10. Maximum Continous Drain
Current vs. Case Temperature
100000
1000
100
10
SINGLE PULSE
R
= 1.1°C/W
q
JC
10 ms
T
= 25°C
C
10000
1000
100 ms
THIS AREA IS
LIMITED BY r
DS(on)
1 ms
100
1
SINGLE PULSE
T
= MAX RATED
10 ms
J
CURVE BENT TO
MEASURED DATA
R
= 1.1°C/W
= 25°C
q
JC
100 ms/DC
T
C
0.1
0.1
10
−5
−4
−3
−2
−1
1
10
100
500
10
10
10
10
10
1
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Unclamped Inductive
Switching Capability
Figure 12. Maximum Continuous Drain
Current vs. Case Temperature
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
P
DM
0.1
0.1
0.05
0.02
0.01
t
1
t
2
NOTES:
0.01
Z
q
(t) = r(t) × R
= 1.1°C/W
SINGLE PULSE
q
JC
JC
R
q
JC
PEAK T = P
× Z
q
(t) + T
JC C
J
DM
Duty cycle, D = t /t
1
2
0.001
−5
−4
−3
−2
−1
10
10
10
10
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction−to−Case Transient Thermal Response Curve
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE C
DATE 21 JAN 2022
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13655G
PQFN8 5X6, 1.27P
PAGE 1 OF 1
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