FDMS3604S [ONSEMI]
不对称双 N 沟道，PowerTrench® 功率级 MOSFET，30V;
| 型号： | FDMS3604S |
| 厂家： | 
ONSEMI |
| 描述： | 不对称双 N 沟道，PowerTrench® 功率级 MOSFET，30V |
| 文件： | 总16页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FDMS3604S
MOSFET – N-Channel,
POWERTRENCH), Power
Stage, Asymetric Dual
General Description
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This device includes two specialized N−Channel MOSFETs in a
dual PQFN package. The switch node has been internally connected to
enable easy placement and routing of synchronous buck converters.
The control MOSFET (Q1) and synchronous SyncFET™ (Q2) have
been designed to provide optimal power efficiency.
G1
D1
D1
D1
D1
PHASE
(S1/D2)
Features
Q1: N−Channel
G2
S2
S2
• Max r
• Max r
= 8 mW at V = 10 V, I = 13 A
GS D
= 11 mW at V = 4.5 V, I = 11 A
S2
DS(on)
Top
Bottom
DS(on)
GS
D
Q2: N−Channel
PQFN8 5x6, 1.27P
CASE 483AJ
• Max r
= 2.6 mW at V = 10 V, I = 23 A
GS D
DS(on)
• Max r
= 3.5 mW at V = 4.5 V, I = 21 A
GS D
DS(on)
• Low Inductance Packaging Shortens Rise/Fall Times, Resulting in
Lower Switching Losses
MARKING DIAGRAM
• MOSFET Integration Enables Optimum Layout for Lower Circuit
Inductance and Reduced Switch Node Ringing
• This Device is Pb−Free and is RoHS Compliant
$Y&Z&3&K
22CA
N7CC
Applications
• Computing
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
• Communications
• General Purpose Point of Load
• Notebook VCORE
22CA N7CC
= Specific Device Code
PIN CONFIGURATION
Q2
S2
S2
S2
G2
5
6
7
8
4
3
2
1
D1
D1
D1
G1
PHASE
Q1
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
January, 2020 − Rev. 3
FDMS3604S/D
FDMS3604S
MOSFET MAXIMUM RATINGS T = 25°C Unless Otherwise Noted
A
Symbol
VDS
Parameter
Q1
30
33
20
Q2
30
33
20
Units
Drain to Source Voltage
V
V
V
A
VDSt
VGS
Drain to Source Transient Voltage ( t < 100 ns)
Transient
Gate to Source Voltage (Note 3)
ID
Drain Current
−Continuous (Package limited)
TC = 25 °C
TC = 25 °C
TA = 25 °C
30
60
40
130
−Continuous (Silicon limited)
−Continuous
13 (Note 1a)
40
23 (Note 1b)
100
−Pulsed
EAS
PD
Single Pulse Avalanche Energy
40 (Note 4)
2.2 (Note 1a)
1.0 (Note 1c)
60 (Note 5)
2.5 (Note 1b)
1.0 (Note 1d)
mJ
W
Power Dissipation for Single Operation TA = 25 °C
Power Dissipation for Single Operation TA = 25 °C
Operating and Storage Junction Temperature Range
TJ, TSTG
−55 to +150
°C
THERMAL CHARACTERISTICS
Symbol
Parameter
Q1
Q2
Unit
°C/W
57 (Note 1a)
50 (Note 1b)
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
125 (Note 1c)
3.5
120 (Note 1d)
2
PACKAGE MARKING AND ORDERING INFORMATION
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
22CA N7CC
FDMS3604S
Power 56
13”
12 mm
3000 Units
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2
FDMS3604S
ELECTRICAL CHARACTERISTICS T = 25°C Unless Otherwise Noted
J
Column Head
Symbol
Parameter
Test Conditions
Type Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
Drain to Source Breakdown
Voltage
I
= 250 mA, V = 0 V I = 1 mA,
GS
Q1
Q2
30
30
V
mV/°C
mA
DSS
D
GS
D
V
= 0 V
DBV
DT
/
Breakdown Voltage Temperature
Coefficient
I
D
= 250 mA, referenced to 25°C
Q1
Q2
15
12
DSS
J
D
I
= 10 mA, referenced to 25°C
I
Zero Gate Voltage Drain Current
V
V
= 24 V, V = 0 V
Q1
Q2
1
DSS
DS
GS
GS
500
I
Gate to Source Leakage Current,
Forwad
= 20 V, V = 0 V
Q1
Q2
100
100
nA
GSS
DS
ON CHARACTERISTICS
V
GS(th)
Gate to Source Threshold Voltage
V
D
= V , I = 250 mA V = V ,
DS
Q1
Q2
1.1
1.1
2
1.8
2.7
3
V
GS
DS
D
GS
I
= 1 mA
DV
/
Gate to Source Threshold Voltage
Temperature Coefficient
I
I
= 250 mA, referenced to 25°C
= 10 mA, referenced to 25°C
Q1
Q2
−6
−5
mV/°C
mW
GS(th)
DT
D
D
J
r
Drain to Source On Resistance
Forward Transconductance
V
= 10 V, I = 13 A V = 4.5 V,
Q1
5.8
8.5
7.8
8
DS(on)
GS
D
GS
I
= 11 A
11
D
V
= 10 V, I = 13 A , T = 125°C
10.8
GS
D
J
V
= 10 V, I = 23 A V = 4.5 V,
Q2
2.0
3.0
2.6
2.6
3.5
4
GS
D
GS
I
= 21 A
D
V
= 10 V, I = 23 A , T = 125°C
GS
D
J
g
V
= 5 V, I = 13 A V = 5 V, I = 23 A
Q1
Q2
61
130
S
FS
DS
D
DS
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
Q1:
DS
Q2:
Q1
Q2
1340 1785
3240 4310
pF
pF
pF
W
iss
V
= 15 V, V = 0 V, f = 1 MHz
GS
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q1
Q2
485
645
oss
V
= 15 V, V = 0 V, f = 1 MHz
DS GS
1230 1635
C
Q1
Q2
53
103
80
155
rss
R
Q1
Q2
0.2
0.2
0.6
0.8
2
3
g
SWITCHING CHARACTERISTICS
t
Turn−On Delay Time
Q1:
DD
Q2:
Q1
Q2
8.2
13
16
23
ns
ns
d(on)
V
= 15 V, I = 13 A, R
= 6 W
= 6 W
D
GEN
t
r
Rise Time
Q1
Q2
2.5
4.8
10
10
V
= 15 V, I = 23 A, R
DD D
GEN
t
Turn−Off Delay Time
Fall Time
Q1
Q2
20
31
32
50
ns
d(off)
t
f
Q1
Q2
2.2
3.4
10
10
ns
Q
Q
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
V
= 0 V to 10 V
= 0 V to 4.5 V
Q1
DD
Q1
Q2
21
47
29
66
nC
nC
nC
nC
g
g
GS
V
= 15 V, I = 13 A
D
Q2
Q1
Q2
10
22
14
31
GS
V
DD
= 15 V, I = 23 A
D
Q
Q1
Q2
3.9
9
gs
Q
Q1
Q2
3.1
5.5
gd
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3
FDMS3604S
ELECTRICAL CHARACTERISTICS T = 25°C Unless Otherwise Noted (continued)
J
Column Head
Symbol
Parameter
Test Conditions
Type Min
Typ
Max
Units
DRAIN−SOURCE DIODE CHARACTERISTICS
V
SD
Source to Drain Diode Forward
Voltage
V
GS
V
GS
= 0 V, I = 13 A(Note 2)
Q1
Q2
0.8
0.8
1.2
1.2
V
S
= 0 V, I = 23 A(Note 2)
S
t
Reverse Recovery Time
Q1
F
Q2
Q1
Q2
25
32
40
51
ns
nC
rr
I = 13 A, di/dt = 100 A/ms
Q
Reverse Recovery Charge
Q1
Q2
9
39
18
62
rr
I = 23 A, di/dt = 300 A/ms
F
1. R
is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R
is guaranteed
JC
q
q
JA
by design while R
is determined by the user’s board design.
q
CA
b. 50 °C/W when mounted on
a. 57 °C/W when mounted on
2
a 1 in pad of 2 oz copper
2
a 1 in pad of 2 oz copper
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. As an N−ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
4. E of 40 mJ is based on starting T = 25°C; N−ch: L = 1 mH, I = 9 A, V = 27 V, V = 10 V. 100% test at L = 0.3 mH, I = 14 A.
AS
J
AS
DD
GS
AS
5. E of 60 mJ is based on starting T = 25°C; N−ch: L = 1 mH, I = 11 A, V = 27 V, V = 10 V. 100% test at L = 0.3 mH, I = 18 A.
AS
J
AS
DD
GS
AS
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4
FDMS3604S
TYPICAL CHARACTERISTICS (Q1 N−CHANNEL)
T = 25°C Unless Otherwise Noted
J
40
30
20
10
0
4
3
2
1
VGS = 3.5 V
ms
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX
10 V
VGS
=
= 6 V
VGS
VGS = 4.5 V
VGS = 4 V
4 V
=
VGS
VGS = 4.5 V
VGS = 6 V
3.5 V
=
VGS
10 V
=
VGS
ms
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX
0
0
10
20
30
40
0.0
0.2
0.4
0.6
0.8
1.0
, DRAIN TO SOURCE VOLTAGE (V)
VDS
ID, DRAIN CURRENT (A)
Figure 2. Normalized On−Resistance vs Drain
Figure 1. On−Region Characteristics
Current and Gate Voltage
1.6
1.4
1.2
1.0
0.8
0.6
20
ID = 13 A
ms
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX
VGS = 10 V
16
12
8
ID = 13 A
TJ = 125oC
4
TJ = 25oC
0
−75 −50 −25
0
25 50 75 100 125 150
2
4
6
8
10
, JUNCTION TEMPERATURE (oC)
TJ
, GATE TO SOURCE VOLTAGE (V)
VGS
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure 4. On−Resistance vs Gate to Source
Voltage
1000
100
SINGLE PULSE
RqJA = 1255C/W
10
ms
100
100
TA = 255C
1 ms
1
10
10 ms
100 ms
1 s
THIS AREA IS
LIMITED BY r
DS(on)
1
SINGLE PULSE
0.1
T
J = MAX RATED
10 s
JA = 125oC/W
R
q
DC
TA = 25oC
100
10−2
t, PULSE WIDTH (sec)
0.01
0.01
0.1
10−4
0.1
−3−1
100 1000
1
10
200
10
10
1
10
VDS,DRAINtoSOURCEVOLTAGE(V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
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5
FDMS3604S
TYPICAL CHARACTERISTICS (Q1 N−CHANNEL)
T = 25°C Unless Otherwise Noted (continued)
J
10
8
2000
1000
ID = 13 A
VDD = 10 V
Ciss
VDD = 15 V
Coss
6
VDD = 20 V
100
4
Crss
2
f = 1 MHz
GS = 0 V
V
0
10
0
5
10
15
20
25
0.1
1
10
30
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 8. Capacitance vs Drain to Source Voltage
Figure 7. Gate Charge Characteristics
20
100
R
qJC = 3.5 oC/W
80
60
40
20
0
10
V
GS = 10 V
TJ = 25 oC
V
GS = 4.5 V
TJ = 100oC
TJ = 125oC
Limited by Package
1
0.01
0.1
1
10
100
25
50
75
100
125
150
T , CASE TEMPERATUREo(C)
tAV, TIME IN AVALANCHE (ms)
C
Figure 9. Unclamped Inductive Switching
Capability
Figure 10. Maximum Continuous Drain Current
vs Case Temperature
100
1000
SINGLE PULSE
qJA = 125oC/W
100
R
10
1
100
10
1
T
A = 25oC
1 ms
10 ms
THIS AREA IS
r
LIMITED BY
100 ms
DS(on)
SINGLE PULSE
TJ = MAX RATED
1 s
0.1
10 s
= 125o
R
C/W
q
JA
DC
TA = 25o
C
0.01
0.01
0.1
10−4
10−3
10−2
t, PULSE WIDTH (sec)
10−1
1
10
0.1
1
10
100
200
100 1000
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe Operating Area
Figure 12. Single Pulse Maximum Power
Dissipation
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FDMS3604S
TYPICAL CHARACTERISTICS (Q1 N−CHANNEL)
T = 25°C Unless Otherwise Noted (continued)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.01
P
DM
t
1
t
2
SINGLE PULSE
qJA = 125 oC/W
(Note 1c)
NOTES:
DUTY FACTOR: D = t /t
R
1
2
PEAK T = P
J
x Z
x R
+ T
DM
qJA
qJA A
0.001
10−4
10−3
10−2
10−1
t, RECTANGULAR PULSE DURATION (sec)
11
0
100
1000
Figure 13. Junction−to−Ambient Transient Thermal Response Curve
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FDMS3604S
TYPICAL CHARACTERISTICS (Q2 N−CHANNEL)
T = 25°C Unless Otherwise Noted
J
100
80
60
40
20
0
8
6
4
ms
PULSE DURATION = 80
V
GS = 10 V
VGS = 4.5 V
VGS = 4 V
DUTY CYCLE = 0.5% MAX
VGS = 3 V
VGS = 3.5 V
V
= 3.5 V
GS
ms
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX
VGS = 4.5 V
VGS = 4 V
2
0
VGS = 3 V
VGS = 10 V
0
20
40
60
80
100
0.0
0.2
0.4
0.6
0.8
1.0
V
DS, DRAIN TO SOURCE VOLTAGE (V)
I
D, DRAIN CURRENT (A)
Figure 15. Normalized On−Resistance vs Drain
Figure 14. On−Region Characteristics
Current and Gate Voltage
1.6
1.4
1.2
1.0
0.8
12
ID = 23 A
VGS = 10 V
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
9
ID = 23 A
6
TJ = 125 oC
3
TJ = 25 o
C
0
2
4
6
8
10
−75 −50 −25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATUREo(C)
V
GS, GATE TO SOURCE VOLTAGE (V)
Figure 16. Normalized On−Resistance vs Junction
Figure 17. On−Resistance vs Gate to Source
Temperature
Voltage
100
100
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
VGS = 0 V
TJ = 125 o
80
10
1
C
VDS = 5 V
60
TJ = 125 o
C
T
J = 25 oC
40
20
0
0.1
TJ = 25 o
C
TJ = −55oC
0.01
T
J = −55oC
0.001
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Source to Drain Diode Forward Voltage
vs Source Current
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FDMS3604S
TYPICAL CHARACTERISTICS (Q2 N−CHANNEL)
T = 25°C Unless Otherwise Noted (continued)
J
10
8
10000
1000
ID = 23 A
Ciss
VDD = 10 V
Coss
6
VDD = 15 V
4
100
10
V
DD = 20 V
Crss
2
f = 1 MHz
= 0 V
V
GS
0
0.1
1
10
30
0
10
20
30
40
50
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 21. Capacitance vs Drain to Source Voltage
Figure 20. Gate Charge Characteristics
50
10
160
R
qJC = 2 oC/W
120
80
40
0
TJ = 25 oC
V
GS = 10 V
TJ = 100 oC
VGS = 4.5 V
TJ = 125 o
C
Limited by Package
1
0.01
0.1
1
10
100
1000
25
50
75
100
125
150
T , CASE TEMPERATUREo(C)
tAV, TIME IN AVALANCHE (ms)
C
Figure 22. Unclamped Inductive Switching
Capability
Figure 23. Maximum Continuous Drain Current
vs Case Temperature
1000
200
100
SINGLE PULSE
qJA = 120oC/W
R
100
10
1
1 ms
T
A = 25oC
10
10 ms
THIS AREA IS
LIMITED BY r
1
100 ms
DS(on)
1s
SINGLE PULSE
TJ = MAX RATED
0.1
0.01
10s
R
qJA = 120 oC/W
DC
TA = 25 oC
0.1
10−3
10−2
10−1
t, PULSE WIDTH (sec)
1
10
100
1000
0.01
0.1
1
10
100200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 24. Forward Bias Safe Operating Area
Figure 25. Single Pulse Maximum Power
Dissipation
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FDMS3604S
TYPICAL CHARACTERISTICS (Q2 N−CHANNEL)
T = 25°C Unless Otherwise Noted (continued)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
P
0.1
0.01
DM
t
1
t
2
SINGLE PULSE
qJA= 120 o
NOTES:
DUTY FACTOR: D = t /t
R
C/W
1
2
PEAK T = P x Z
x R
+ T
qJA A
(Note 1c)
J
DM
qJA
0.001
10−3
10−2
10−1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 26. Junction−to−Ambient Transient Thermal Response Curve
SyncFET Schottky Body Diode Characteristics
ON Semiconductor’s SyncFET process embeds a
Schottky diode in parallel with PowerTrench MOSFET.
This diode exhibits similar characteristics to a discrete
external Schottky diode in parallel with a MOSFET.
Figure 27 shows the reverse recovery characteristic of the
FDMS3604S.
Schottky barrier diodes exhibit significant leakage at high
temperature and high reverse voltage. This will increase the
power in the device.
10−2
25
TJ = 125 oC
20
10−3
didt = 300 A/ms
TJ = 100 oC
15
10
5
10−4
10−5
TJ = 25 o
C
0
10−6
−5
0
50
100
TIME (ns)
150
200
0
5
10
15
20
25
30
VDS, REVERSE VOLTAGE (V)
Figure 27. FDMS3604S SyncFET Body
Diode Reverse Recovery Characteristics
Figure 28. SyncFET Body Diode Reverse
Leakage versus Drain−source Voltage
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FDMS3604S
APPLICATION INFORMATION
Switch Node Ringing Suppression
ON Semiconductor’s Power Stage products incorporate a
proprietary design* that minimizes the peak overshoot,
ringing voltage on the switch node (PHASE) without the
need of any external snubbing components in a buck
converter. As shown in the Figure 29, the Power Stage
solution rings significantly less than competitor solutions
under the same set of test conditions.
Power Stage Device
*Patent Pending
Competitorrs Solution
Figure 29. Power Stage Phase Node Rising Edge, High Turn On
Figure 30. Shows the Power Stage in a Buck Converter Topology
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FDMS3604S
Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues
in layout to minimize losses and optimize the performance
of the power train. Power Stage is a high power density
solution and all high current flow paths, such as VIN (D1),
PHASE (S1/D2) and GND (S2), should be short and wide
for better and stable current flow, heat radiation and system
performance. recommended layout procedure is
discussed below to maximize the electrical and thermal
performance of the part.
A
Figure 31. Recommended PCB Layout
Following is a guideline, not a requirement which the PCB designer should consider:
1. Input ceramic bypass capacitors C1 and C2 must
be placed close to the D1 and S2 pins of Power
Stage to help reduce parasitic inductance and High
Frequency conduction loss induced by switching
operation. C1 and C2 show the bypass capacitors
placed close to the part between D1 and S2. Input
capacitors should be connected in parallel close to
the part. Multiple input caps can be connected
depending upon the application
2. The PHASE copper trace serves two purposes; In
addition to being the current path from the Power
Stage package to the output inductor (L), it also
serves as heat sink for the lower FET in the Power
Stage package. The trace should be short and wide
enough to present a low resistance path for the
high current flow between the Power Stage and the
inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that
the PHASE node is a high voltage and high
frequency switching node with high noise
3. Output inductor location should be as close as
possible to the Power Stage device for lower
power loss due to copper trace resistance. A
shorter and wider PHASE trace to the inductor
reduces the conduction loss. Preferably the Power
Stage should be directly in line (as shown in
Figure 32) with the inductor for space savings and
compactness
4. The POWERTRENCH Technology MOSFETs
used in the Power Stage are effective at
minimizing phase node ringing. It allows the part
to operate well within the breakdown voltage
limits. This eliminates the need to have an external
snubber circuit in most cases. If the designer
chooses to use an RC snubber, it should be placed
close to the part between the PHASE pad and S2
pins to dampen the high−frequency ringing
5. The driver IC should be placed close to the Power
Stage part with the shortest possible paths for the
High Side gate and Low Side gates through a wide
trace connection. This eliminates the effect of
parasitic inductance and resistance between the
driver and the MOSFET and turns the devices on
and off as efficiently as possible. At
potential. Care should be taken to minimize
coupling to adjacent traces. The reference layout
in Figure 31 shows a good balance between the
thermal and electrical performance of Power Stage
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12
FDMS3604S
higher−frequency operation this impedance can
limit the gate current trying to charge the
MOSFET input capacitance. This will result in
slower rise and fall times and additional switching
losses. Power Stage has both the gate pins on the
same side of the package which allows for back
mounting of the driver IC to the board. This
provides a very compact path for the drive signals
and improves efficiency of the part
7. Use multiple vias on each copper area to
interconnect top, inner and bottom layers to help
smooth current flow and heat conduction. Vias
should be relatively large, around 8 mils to 10
mils, and of reasonable inductance. Critical high
frequency components such as ceramic bypass
caps should be located close to the part and on the
same side of the PCB. If not feasible, they should
be connected from the backside via a network of
low inductance vias
6. S2 pins should be connected to the GND plane
with multiple vias for a low impedance grounding.
Poor grounding can create a noise transient offset
voltage level between S2 and driver ground. This
could lead to faulty operation of the gate driver
and MOSFET
SyncFET IS trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN8 5X6, 1.27P (SAWN TYPE)
CASE 483AJ
ISSUE A
DATE 08 FEB 2021
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13659G
PQFN8 5X6, 1.27P
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN8 5X6, 1.27P (PUNCHED TYPE)
CASE 483AJ
ISSUE A
DATE 08 FEB 2021
0.10
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Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13659G
PQFN8 5X6, 1.27P
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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