FDMC86570L [ONSEMI]
N 沟道屏蔽门极 PowerTrench® MOSFET 60 V，84A，4.3mΩ;
| 型号： | FDMC86570L |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道屏蔽门极 PowerTrench® MOSFET 60 V，84A，4.3mΩ |
| 文件： | 总8页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET – N-Channel,
Shielded Gate
POWERTRENCH)
Pin 1
Pin 1
S
S
S
G
D
D
D
D
60 V, 84 A, 4.3 mW
Top
Bottom
FDMC86570L
WDFN8 3.3x3.3, 0.65P
CASE 483AW
General Description
This N−Channel MOSFET is produced using onsemi’s advanced
POWERTRENCH process that incorporates Shielded Gate
technology. This process has been optimized for the on−state
resistance and yet maintain superior switching performance.
MARKING DIAGRAM
ON
ZXYYKK
Features
FDMC
86570L
• Shielded Gate MOSFET Technology
• Max r
• Max r
= 4.3 mW at V = 10 V, I = 18 A
GS D
DS(on)
= 6.5 mW at V = 4.5 V, I = 15 A
DS(on)
GS
D
Z
X
= Assembly Plant Code
= Year Code
= Week Code
= Lot Code
= Specific Device Code
• High Performance Technology for Extremely Low r
• These Devices are Pb−Free and are RoHS Compliant
DS(on)
YY
KK
FDMC
Application
• DC−DC Conversion
86570L
= Specific Device Code
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
PIN ASSIGNMENT
Symbol
VDS
Parameter
Drain to Source Voltage
Ratings Units
60
20
V
V
A
S
S
1
2
8
7
D
D
VGS
Gate to Source Voltage
Drain Current
ID
−Continuous
−Continuous
−Continuous
−Pulsed
TC = 25°C (Note 5)
84
53
18
416
TC = 100°C (Note 5)
TA = 25°C (Note 1a)
(Note 4)
S
3
4
6
5
D
D
G
EAS
PD
Single Pulse Avalanche Energy (Note 3)
253
54
mJ
W
Power Dissipation TC = 25°C
Power Dissipation TA = 25°C (Note 1a)
N−Channel MOSFET
2.3
TJ, TSTG Operating and Storage Junction Temperature
Range
−55 to
+150
°C
ORDERING INFORMATION
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See detailed ordering and shipping information on page 6 of
this data sheet.
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
Unit
RθJC
Thermal Resistance, Junction−to−Case
(Note 1)
2.3
°C/W
RθJA
Thermal Resistance, Junction−to−Ambient
(Note 1a)
53
°C/W
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
January, 2023 − Rev. 2
FDMC86570L/D
FDMC86570L
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= 250 mA, V = 0 V
60
V
DSS
D
GS
DBV
/DT Breakdown Voltage Temperature
= 250 mA, referenced to 25°C
30
mV/°C
DSS
J
D
Coefficient
mA
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
V
= 48 V, V = 0 V
1
DSS
DS
GS
I
=
20 V, V = 0 V
100
nA
GSS
GS
DS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
V
I
= V , I = 250 mA
1.0
1.8
3.0
V
GS(th)
GS
DS
D
DV
/DT Gate to Source Threshold Voltage
= 250 mA, referenced to 25°C
−7
mV/°C
GS(th)
J
D
Temperature Coefficient
r
Static Drain to Source On Resistance
mW
V
V
V
V
= 10 V, I = 18 A
3.1
4.7
5.0
75
4.3
6.5
6.9
DS(on)
GS
D
= 4.5 V, I = 15 A
GS
GS
DS
D
= 10 V, I = 18 A, T = 125°C
D
J
g
FS
Forward Transconductance
= 5 V, I = 18 A
S
D
DYNAMIC CHARACTERISTICS
V
= 30 V, V = 0 V,
C
Input Capacitance
4790
821
19
6705
1150
30
pF
pF
pF
W
DS
GS
iss
f = 1 MHz
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
oss
C
rss
R
0.1
0.9
2.7
g
SWITCHING CHARACTERISTICS
V
= 30 V, I = 18 A, V = 10 V,
D GS
GEN
t
Turn−On Delay Time
Rise Time
19
6.2
38
34
12
61
10
88
41
ns
ns
DD
R
d(on)
= 6 W
t
r
t
Turn−Off Delay Time
Fall Time
ns
d(off)
t
f
3.9
63
ns
V
D
= 30 V
Q
Q
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
= 0 V to 10 V
= 0 V to 4.5 V
GS
nC
nC
nC
nC
DD
g(TOT)
GS
I = 18 A
V
29
g(TOT)
Qgs
14
Qgd
6.3
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Forward Voltage V = 0 V, I = 18 A (Note 2)
V
0.8
0.7
43
1.3
1.2
69
SD
GS
S
V
GS
= 0 V, I = 1.9 A (Note 2)
S
t
I = 18 A, di/dt = 100 A/ms
F
Reverse Recovery Time
ns
rr
Q
Reverse Recovery Charge
26
42
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDMC86570L
NOTES:
1. R
2
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R
is determined
θ
θ
CA
JA
by the user’s board design.
a. 53 °C/W when mounted on
b. 125 °C/W when mounted on
a minimum pad of 2 oz copper.
2
pad of 2 oz copper.
a 1 in
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. E of 253 mJ is based on starting T = 25 °C, L = 3 mH, I = 13 A, V = 60 V, V = 10 V. 100% test at L = 0.1 mH, I = 43 A.
AS
J
AS
DD
GS
AS
4. Pulsed I please refer to Figure 11 SOA graph for more details.
D
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal &
electro−mechanical application board design.
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3
FDMC86570L
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
5
200
160
120
80
V
= 10 V
= 6 V
GS
V
GS
= 3.5 V
V
GS
4
3
V
= 5 V
GS
V
GS
= 4 V
V
GS
= 5 V
V
= 4.5 V
GS
V
GS
= 4.5 V
2
1
0
V
= 4 V
GS
40
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
GS
= 10 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
= 3.5 V
1
GS
V
GS
= 6 V
0
0
2
3
4
5
0
40
80
120
160
200
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 1. On−Region Characteristics
Figure 2. Normalized On−Resistance vs.
Drain Current and Gate Voltage
1.8
20
PULSE DURATION = 80 ms
I
V
= 18 A
DUTY CYCLE = 0.5% MAX
16
D
1.6
1.4
1.2
1.0
0.8
0.6
= 10 V
GS
I
D
= 18 A
12
8
T = 125°C
J
4
T = 25°C
J
0
−75 −50 −25
0
25 50 75 100 125 150
4
2
6
8
10
T , JUNCTION TEMPERATURE (°C)
J
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On−Resistance
Figure 4. On−Resistance vs. Gate to
vs. Junction Temperature
Source Voltage
200
200
100
V
GS
= 0 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
160
10
V
DS
= 5 V
T = 150°C
J
120
80
40
0
1
T = 150°C
J
T = 25°C
J
0.1
T = 25°C
J
0.01
0.001
T = −55°C
J
T = −55°C
J
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1
2
3
4
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward
Voltage vs. Source Current
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4
FDMC86570L
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
10
8
10000
I
D
= 18 A
C
iss
V
= 20 V
DD
1000
100
10
C
oss
V
DD
= 30 V
6
V
= 40 V
DD
4
C
rss
2
f = 1 MHz
= 0 V
V
GS
0
1
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
DS
60
0
14
28
42
56
70
Q , GATE CHARGE (nC)
V
g
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain
to Source Voltage
100
80
60
40
20
0
50
R
= 2.3°C/W
q
JC
T = 25°C
J
T = 100°C
J
10
V
= 10 V
GS
V
GS
= 4.5 V
100
T = 125°C
J
1
25
50
75
125
150
0.001 0.01
0.1
1
10
100 400
t , TIME IN AVALANCHE (ms)
AV
T , CASE TEMPERATURE (°C)
C
Figure 9. Unclamped Inductive Switching
Capability
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
1000
100
10000
1000
100
10 ms
10
1
THIS AREA IS
LIMITED BY r
100 ms
DS(on)
SINGLE PULSE
1 ms
10 ms
DC
T
J
= MAX RATED
SINGLE PULSE
R
q
= 2.3°C/W
JC
R
= 2.3°C/W
q
JC
CURVE BENT TO
MEASURED DATA
T
C
= 25°C
T
C
= 25°C
0.1
0.1
10
10
−5
−4
−3
−2
−1
1
10
100 200
10
10
10
10
1
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
Figure 11. Forward Bias Safe Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
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5
FDMC86570L
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
t
1
t
2
NOTES:
0.01
Z
q
(t) = r(t) × R
q
JC
JC
SINGLE PULSE
R
= 2.3°C/W
q
JC
Peak T = P
× Z (t) + T
q
JC C
J
DM
Duty Cycle, D = t / t
1
2
0.001
10−5
10−4
10−3
10−2
10−1
1
t, RECTANGULAR PULSE DURATION (s)
Figure 13. Junction−to−Case Transient Thermal Response Curve
ORDERING INFORMATION
Device
†
Device Marking
Package Type
Shipping
FDMC86570L
FDMC86570L
WDFN8 3.3x3.3, 0.65P
3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3X3.3, 0.65P
CASE 483AW
ISSUE A
DATE 10 SEP 2019
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXX = Specific Device Code
A
Y
= Assembly Location
= Year
XXXX
AYWW
WW = Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13672G
WDFN8 3.3X3.3, 0.65P
PAGE 1 OF 1
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