FDD8880 [ONSEMI]
N 沟道，PowerTrench® MOSFET，30V，58A，9mΩ;
| 型号： | FDD8880 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，PowerTrench® MOSFET，30V，58A，9mΩ 开关 晶体管 |
| 文件： | 总14页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET – N-Channel,
POWERTRENCH)
V
MAX
r
MAX
I MAX
D
DSS
DS(ON)
30 V
9 mW @ 10 V
58 A
12 mW @ 4.5 V
30 V, 58 A, 9 mW
FDD8880, FDD8880-G
D
G
General Description
S
This N−Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using either
synchronous or conventional switching PWM controllers. It has been
DPAK3
(TO−252 3 LD)
CASE 369AS
optimized for low gate charge, low r
and fast switching speed.
DS(ON)
Features
MARKING DIAGRAM
• r
• r
= 9 mW, V = 10 V, I = 35 A
GS D
DS(ON)
DS(ON)
= 12 mW, V = 4.5 V, I = 35 A
GS
D
$Y&Z&3&K
FDD
• High Performance Trench Technology for Extremely Low r
• Low Gate Charge
DS(ON)
8880
• High Power and Current Handling Capability
• These Devices are Pb−Free and are RoHS Compliant
Applications
• DC/DC Converters
$Y
&Z
&3
&K
= onsemi Logo
= Assembly Plant Code
= 3−Digit Date Code Format
= 2−Digits Lot Run Traceability Code
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
FDD8880 = Device Code
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Ratings
30
Unit
V
V
DSS
D
V
GS
20
V
I
D
Drain
Current
Continuous (T = 25°C,
GS
58
A
A
V
= 10 V) (Note 1)
Continuous (T = 25°C,
GS
51
13
A
A
A
G
V
= 4.5 V) (Note 1)
Continuous (T
GS
(Note 1)
= 25°C,
q
amb
S
N−Channel
V
= 10 V, with R
= 52°C/W)
JA
Pulsed
Figure 4
53
A
mJ
E
AS
Single Pulse Avalanche Energy (Note 2)
Power Dissipation
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
P
55
W
D
Derate above 25°C
0.37
mW/°C
°C
T , T
Operating and Storage Temperature
–55 to 175
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Package current limitation is 35A.
2. Starting T = 25°C, L = 0.14 mH, I = 28 A, V = 27 V, V = 10 V.
J
AS
DD
GS
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
March, 2022 − Rev. 3
FDD8880/D
FDD8880, FDD8880−G
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
2.73
100
Unit
°C/W
°C/W
°C/W
R
q
JC
R
q
JA
R
q
JA
Thermal Resistance, Junction to Case TO−252
Thermal Resistance, Junction to Ambient TO−252
Thermal Resistance, Junction to Ambient TO−252, 1 in Copper Pad Area
2
52
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
I
= 250 mA, V = 0 V
30
−
−
−
−
−
−
V
VDSS
D
GS
I
V
V
V
= 24 V, V = 0 V
1
mA
DSS
DS
DS
GS
GS
= 24 V, V = 0 V, T = 150°C
−
250
100
GS
C
I
Gate to Source Leakage Current
=
20 V
−
nA
GSS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
= V , I = 250 mA
1.2
−
−
2.5
V
GS(TH)
DS(ON)
GS
DS
D
r
I
D
I
D
I
D
= 35 A, V = 10 V
0.007
0.009
0.013
0.009
0.012
0.015
W
GS
= 35 A, V = 4.5 V
−
GS
= 35 A, V = 10 V, T = 175°C
−
GS
J
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 15 V, V = 0 V, f = 1 MHz
−
−
−
−
−
1260
260
150
2.3
−
−
pF
pF
pF
W
ISS
DS
GS
C
OSS
C
RSS
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
−
R
V
V
= 0.5 V, f = 1 MHz
−
G
GS
Q
Total Gate Charge at 10 V
= 0 V to 10 V, V = 15 V,
23
31
nC
g(TOT)
GS
DD
I
= 35 A, I = 1.0 mA
D
g
Q
Total Gate Charge at 5 V
Threshold Gate Charge
V
D
= 0 V to 5 V, V = 15 V,
−
−
13
17
nC
nC
g(5)
GS
DD
I
= 35 A, I = 1.0 mA
g
Q
V
D
= 0 V to 1 V, V = 15 V,
1.3
1.7
g(TH)
GS
DD
I
= 35 A, I = 1.0 mA
g
Q
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V
DD
= 15 V, I = 35 A, I = 1.0 mA
−
−
−
3.8
2.5
5.0
−
−
−
nC
nC
nC
gs
D
g
Q
gs2
Q
gd
SWITCHING CHARACTERISTICS (V = 10 V)
GS
t
Turn−On Time
Turn−On Delay Time
Rise Time
V
= 15 V, I = 35 A, V = 10 V,
−
−
−
−
−
−
−
8
147
−
ns
ns
ns
ns
ns
ns
ON
DD
GS
D
GS
R
= 10 W
t
d(ON)
t
r
91
38
32
−
−
t
Turn−Off Delay Time
Fall Time
−
d(OFF)
t
f
−
t
Turn−Off Time
108
OFF
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Voltage
I
I
I
I
= 35 A
= 15 A
−
−
−
−
−
−
−
−
1.25
1.0
27
V
V
SD
SD
SD
SD
SD
t
Reverse Recovery Time
= 35 A, dI /dt = 100 A/ms
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 35 A, dI /dt = 100 A/ms
14
RR
SD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDD8880, FDD8880−G
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
J
1.2
1.0
0.8
0.6
0.4
0.2
0
60
50
40
30
20
10
0
CURRENT LIMITED
BY PACKAGE
V
GS
= 10 V
V
= 4.5 V
GS
0
25
50
75
100
125
150 175
25
50
75
100
125
150
175
T , CASE TEMPERATURE (°C)
C
T , CASE TEMPERATURE (°C)
C
Figure 1. Normalized Power Dissipation vs.
Case Temperature
Figure 2. Maximum Continuous Drain Current vs.
Case Temperature
2
DUTY CYCLE−DESCENDING ORDER
1
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.01
t1
t2
NOTES:
DUTY FACTOR: D = t / t
1
2
SINGLE PULSE
10−4
PEAK T = P
x Z
x R
+ T
JC C
q
q
J
DM
JC
0.001
10−5
10−3
10−2
10−1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
500
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T = 25°C
C
FOR TEMPERATURES
ABOVE 25°C DERATE PEAK
CURRENT AS FOLLOWS:
V
V
= 10 V
GS
175 * TC
Ǹ
I + I25 ƪ ƫ
= 4.5 V
150
GS
100
30
10−5
10−4
10−3
10−2
10−1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
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3
FDD8880, FDD8880−G
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted) (continued)
J
1000
500
If R = 0
t
AV
= (L) (I ) / (1.3 x RATED BV
− V
DD
)
AS
DSS
If R ≠ 0
= (L / R) ln [(I x R) / (1.3 x RATED BV
10 ms
t
AV
− V ) +1]
DD
AS
DSS
100
10
1
100
10
1
100 ms
STARTING T = 25°C
J
OPERATION IN
THIS AREA MAY BE
LIMITED BY r
1 ms
DS(ON)
STARTING T = 150°C
J
SINGLE PULSE
10 ms
DC
T = MAX RATED
J
T
C
= 25°C
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
60
4.0
10
0.01
0.1
t , TIME IN AVALANCHE (ms)
AV
1
10
V
DS
NOTE: Refer to onsemi Application Notes AN−7514 and AN−7515
Figure 5. Forward Bis Safe Operating Area
Figure 6. Unclamped Inductive Switching Capability
80
80
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
GS
= 5 V
V
DD
= 15 V
60
40
60
40
20
0
V
GS
= 10 V
V
GS
= 4 V
T = 25°C
J
V
GS
= 3 V
20
0
T
C
= 25°C
T = 175°C
J
T = −55°C
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
J
1.5
2.0
2.5
3.0
3.5
0
0.25
0.5
0.75
1.0
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
1.8
1.6
1.4
1.2
1.0
0.8
0.6
25
20
15
10
5
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
I
D
= 35 A
I
= 1 A
D
V
GS
= 10 V, I = 35 A
D
2
4
6
8
−80
−40
0
40
80
120
160 200
V
GS
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
J
Figure 10. Normalized Drain to Source
On Resistance vs. Junction Temperature
Figure 9. Drain to Source On Resistance vs.
Gate Voltage and Drain Current
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4
FDD8880, FDD8880−G
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted) (continued)
J
1.2
1.0
0.8
0.6
0.4
1.10
I
D
= 250 mA
V
= V , I = 250 mA
DS D
GS
1.05
1.00
0.95
0.90
−80
−40
0
40
80
120
160 200
−80
−40
0
40
80
120
160 200
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Normalized Gate Threshold Voltage vs.
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
2000
10
V
DD
= 15 V
C
= C + C
ISS
GS
GD
1000
8
6
4
2
0
C
≅ C + C
GD
OSS
DS
C
= C
GD
RSS
WAVEFORMS IN
DESCENDING ORDER:
I
D
I
D
= 35 A
= 1 A
V
= 0 V, f = 1 MHz
1
GS
100
0.1
10
30
0
5
10
15
20
25
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 13. Capacitance vs. Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Current
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5
FDD8880, FDD8880−G
TEST CIRCUITS AND WAVEFORMS
VDS
BVDSS
tP
VDS
L
IAS
VDD
VARY t TO OBTAIN
P
+
VDD
−
REQUIRED PEAK I
RG
AS
VGS
DUT
t P
IAS
0.01 W
0 V
0
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
VGS
L
VGS = 10 V
Qg(5)
VGS
Qgs2
+
VDD
VGS = 5 V
−
DUT
VGS = 1 V
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
tON
td(ON)
tOFF
td(OFF)
VDS
t
t
f
r
RL
VDS
90%
90%
+
VGS
VDD
−
10%
10%
0
90%
50%
DUT
RGS
VGS
50%
PULSE WIDTH
10%
0
VGS
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
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FDD8880, FDD8880−G
THERMAL RESISTANCE VS. MOUNTING PAD AREA
The maximum rated junction temperature, T , and the
applications can be evaluated using the onsemi device Spice
JM
thermal resistance of the heat dissipating path determines
thermal model or manually utilizing the normalized
the maximum allowable device power dissipation, P , in
maximum transient thermal impedance curve.
DM
an application. Therefore the application’s ambient
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and Equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
temperature, T (°C), and thermal resistance R
(°C/W)
A
qJA
must be reviewed to ensure that T is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(TJM * TA)
PDM
+
23.84
(eq. 1)
RqJA
RqJA + 33.32 )
Area in Inches Squared
(eq. 2)
(0.268 ) Area)
In using surface mount devices such as the TO−252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
154
RqJA + 33.32 )
Area in Inches Squared
(eq. 3)
(1.73 ) Area)
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
is
DM
1. Mounting pad area onto which the device is
125
attached and whether there is copper on one side
or both sides of the board.
R
= 33.32 + 23.84 / (0.268 + Area) eq.2
= 33.32 + 154 / (1.73 + Area) eq.3
q
JA
R
q
JA
2. The number of copper layers and the thickness of
the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width,
100
75
the duty cycle and the transient thermal response of
the part, the board and the environment they are in.
50
onsemi provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
25
0.01
(0.0645)
0.1
(0.645)
1
10
(64.5)
defines the R for the device as a function of the top copper
qJA
(6.45)
(component side) area. This is for a horizontally positioned
FR−4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
2
2
AREA, TOP COPPER AREA in (cm )
Figure 21. Thermal Resistance vs. Mounting Pad Area
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7
FDD8880, FDD8880−G
PSPICE ELECTRICAL MODEL
.SUBCKT FDD8880 2 1 3 ; rev April 2004
Ca 12 8 9.5e−10
Cb 15 14 9.5e−10
Cin 6 8 1.15e−9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 33.15
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.3e−9
Ldrain 2 5 1.0e−9
Lsource 3 7 1.7e−9
RLgate 1 9 53
RLdrain 2 5 10
RLsource 3 7 17
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 3.2e−3
Rgate 9 20 2.2
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3.2e−3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*170),5))}
.MODEL DbodyMOD D (IS=2E−12 IKF=10 N=1.01 RS=3.76e−3 TRS1=8e−4 TRS2=2e−7
+ CJO=4.8e−10 M=0.55 TT=1e−17 XTI=2)
.MODEL DbreakMOD D (RS=0.2 TRS1=1e−3 TRS2=−8.9e−6)
.MODEL DplcapMOD D (CJO=5.5e−10 IS=1e−30 N=10 M=0.45)
.MODEL MmedMOD NMOS (VTO=2.0 KP=10 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=2.2)
.MODEL MstroMOD NMOS (VTO=2.5 KP=170 IS=1e−30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.69 KP=0.05 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=22 RS=0.1)
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FDD8880, FDD8880−G
.MODEL RbreakMOD RES (TC1=8.3e−4 TC2=−8e−7)
.MODEL RdrainMOD RES (TC1=1.8e−3 TC2=8e−6)
.MODEL RSLCMOD RES (TC1=9e−4 TC2=1e−6)
.MODEL RsourceMOD RES (TC1=5e−3 TC2=1e−6)
.MODEL RvthresMOD RES (TC1=−1e−3 TC2=−8.2e−6)
.MODEL RvtempMOD RES (TC1=−2.6e−3 TC2=2e−7)
.MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4 VOFF=−3.5)
.MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−3.5 VOFF=−4)
.MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.3 VOFF=−0.8)
.MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−0.8 VOFF=−1.3)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written
by William J. Hepp and C. Frank Wheatley.
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
DBODY
RSLC1
DBREAK
11
51
+
RSLC2
5
51
ESLC
−
+
50
−
17
18
−
RDRAIN
6
8
EBREAK
MWEAK
ESG
EVTHRES
+
16
21
+
−
19
8
LGATE
EVTEMP
RGATE
GATE
1
+
6
−
18
22
MMED
9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
−
S1B
S2B
13
CB
CA
IT
14
+
+
6
8
VBAT
5
8
EGS
EDS
+
−
−
8
22
RVTHRES
Figure 22.
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9
FDD8880, FDD8880−G
SABER ELECTRICAL MODEL
rev April 2004
template FDD8880 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2e−12,ikf=10,nl=1.01,rs=3.76e−3,trs1=8e−4,trs2=2e−7,cjo=4.8e−10,m=0.55,tt=1e−17,xti=2)
dp..model dbreakmod = (rs=0.2,trs1=1e−3,trs2=−8.9e−6)
dp..model dplcapmod = (cjo=5.5e−10,isl=10e−30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=2.0,kp=10,is=1e−30, tox=1)
m..model mstrongmod = (type=_n,vto=2.5,kp=170,is=1e−30, tox=1)
m..model mweakmod = (type=_n,vto=1.69,kp=0.05,is=1e−30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−4,voff=−3.5)
sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−3.5,voff=−4)
sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−1.3,voff=−0.8)
sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=−0.8,voff=−1.3)
c.ca n12 n8 = 9.5e−10
c.cb n15 n14 = 9.5e−10
c.cin n6 n8 = 1.15e−9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 33.15
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.3e−9
l.ldrain n2 n5 = 1.0e−9
l.lsource n3 n7 = 1.7e−9
res.rlgate n1 n9 = 53
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 17
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=8.3e−4,tc2=−8e−7
res.rdrain n50 n16 = 3.2e−3, tc1=1.8e−3,tc2=8e−6
res.rgate n9 n20 = 2.2
res.rslc1 n5 n51 = 1e−6, tc1=9e−4,tc2=1e−6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.2e−3, tc1=5e−3,tc2=1e−6
res.rvthres n22 n8 = 1, tc1=−1e−3,tc2=−8.2e−6
res.rvtemp n18 n19 = 1, tc1=−2.6e−3,tc2=2e−7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
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10
FDD8880, FDD8880−G
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5))
}
}
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
DBREAK
50
−
RDRAIN
6
8
11
ESG
DBODY
EVTHRES
+
16
21
+
−
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
6
+
−
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
−
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
−
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
−
−
8
22
RVTHRES
Figure 23.
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11
FDD8880, FDD8880−G
JUNCTION
th
SPICE THERMAL MODEL
REV 23 April 2004
FDD8880T
RTHERM1
CTHERM1
CTHERM1 TH 6 8e−4
CTHERM2 6 5 1e−3
CTHERM3 5 4 2.5e−3
CTHERM4 4 3 2.6e−3
CTHERM5 3 2 8e−3
CTHERM6 2 TL 1.5e−2
6
5
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 TH 6 1.44e−1
RTHERM2 6 5 1.9e−1
RTHERM3 5 4 3.0e−1
RTHERM4 4 3 4.0e−1
RTHERM5 3 2 5.7e−1
RTHERM6 2 TL 5.8e−1
4
3
2
SABER THERMAL MODEL
SABER thermal model FDD8880T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =8e−4
ctherm.ctherm2 6 5 =1e−3
ctherm.ctherm3 5 4 =2.5e−3
ctherm.ctherm4 4 3 =2.6e−3
ctherm.ctherm5 3 2 =8e−3
ctherm.ctherm6 2 tl =1.5e−2
rtherm.rtherm1 th 6 =1.44e−1
rtherm.rtherm2 6 5 =1.9e−1
rtherm.rtherm3 5 4 =3.0e−1
rtherm.rtherm4 4 3 =4.0e−1
rtherm.rtherm5 3 2 =5.7e−1
rtherm.rtherm6 2 tl =5.8e−1
}
tl
CASE
Figure 24.
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
FDD8880
Device Marking
Package Type
Reel Size
Tape Width
Shipping
FDD8880
DPAK3 (TO−252 3 LD)
(TO−252AA)
13”
16 mm
2500 / Tape & Reel
(Pb−Free)
FDD8880−G
FDD8880
DPAK3 (TO−252 3 LD)
(TO−252AA)
13”
16 mm
2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK3 (TO−252 3 LD)
CASE 369AS
ISSUE A
DATE 28 SEP 2022
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
AYWWZZ
XXXX = Specific Device Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ
= Assembly Lot Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON13810G
DPAK3 (TO−252 3 LD)
PAGE 1 OF 1
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相关型号：
FDD8880_NL
Power Field-Effect Transistor, 35A I(D), 30V, 0.015ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, D2PAK-3
FAIRCHILD
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