FDBL9406L-F085 [ONSEMI]
汽车级 MOSFET，N 沟道，逻辑电平，40 V，240 A，1.1 mΩ;
| 型号： | FDBL9406L-F085 |
| 厂家： | 
ONSEMI |
| 描述： | 汽车级 MOSFET，N 沟道，逻辑电平，40 V，240 A，1.1 mΩ |
| 文件： | 总8页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET - Power, Single
N-Channel
40 V, 1.1 mW, 240 A
FDBL9406L-F085
Features
• Small Footprint (TOLL) for Compact Design
www.onsemi.com
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
1.1 mW @ 10 V
40 V
80 A
1.78 mW @ 4.5 V
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
D (9)
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
V
DSS
Gate−to−Source Voltage
V
GS
20
V
G (1)
Continuous Drain
Current R
T
T
= 25°C
I
240
A
C
D
q
JC
(Notes 1, 3)
Steady
State
S (2−8)
Power Dissipation
= 25°C
P
300
150
43
W
A
C
D
N−CHANNEL MOSFET
R
(Note 1)
q
JC
T
C
= 100°C
Continuous Drain
Current R
T = 25°C
A
I
D
q
JA
T = 100°C
A
31
(Notes 1, 2, 3)
Steady
State
Power Dissipation
T = 25°C
A
P
3.5
W
D
R
(Notes 1, 2)
q
JA
T = 100°C
A
1.7
MO−299A
CASE 100CU
Pulsed Drain Current
T
= 25°C, t = 10 ms
I
DM
2755
A
C
p
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
MARKING DIAGRAM
Source Current (Body Diode)
I
100
217
A
S
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (I
= 85 A; L = 60 mH)
L(pk)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
&Z&3&K
FDBL
9406L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
&Z
&3
&K
= Assembly Plant Code
= Numeric Date Code
= Lot Code
Parameter
Symbol
Value
0.5
Unit
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
°C/W
q
JC
FDBL9406L
= Specific Device Code
R
43
q
JA
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
Current is limited by bondwire configuration.
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
December, 2019 − Rev. 1
FDBL9406L−F085/D
FDBL9406L−F085
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
40
−
−
−
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
−
19.3
mV/°C
(BR)DSS
J
Zero Gate Voltage Drain Current
I
V
= 0 V, V = 40 V, T = 25°C
−
−
−
−
−
−
1
mA
mA
nA
DSS
GS
DS
J
V
GS
= 0 V, V = 40 V, T = 175°C
1
DS
J
Zero Gate Voltage Drain Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
V
= 0 V, V =
GS
20 V
100
GSS
DS
V
GS(th)
= V , I = 250 mA
1
−
−
−
1.9
−6.5
0.9
3
−
V
GS
DS
D
Threshold Temperature Coefficient
Drain−to−Source On Resistance
V
/T
mV/°C
mW
GS(th)
J
R
V
GS
= 10 V, I = 80 A
1.1
1.78
DS(on)
D
V
GS
= 4.5 V, I = 40 A
1.25
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
V
= 0 V, f = 1 MHz, V = 20 V
−
−
−
−
−
−
−
−
−
−
8600
2380
106
2
−
−
−
−
−
−
−
−
−
−
pF
pF
pF
W
iss
GS
DS
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
C
oss
C
rss
R
V
GS
= 0.5 V, f = 1 MHz
g
Total Gate Charge
Q
V
GS
= 4.5 V, V = 32 V, I = 80 A
58
nC
G(TOT)
DS
D
V
GS
= 10 V, V = 32 V, I = 80 A
121
7
DS
D
Threshold Gate Charge
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
Plateau Voltage
Q
V
GS
= 0 to 1 V
g(th)
Q
V
DD
= 32 V, I = 80 A
26
gs
D
Q
19
gd
V
GP
3.2
V
SWITCHING CHARACTERISTICS
Turn-On Delay Time
t
V
GS
= 20 V, I = 80 A,
−
−
−
−
22
22
−
−
−
−
ns
ns
ns
ns
d(on)
DD
D
V
= 10 V, R
= 6 W
GEN
Turn-On Rise Time
t
r
Turn-Off Delay Time
t
134
44
d(off)
Turn-Off Fall Time
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Source−to−Drain Diode Voltage
V
I
I
= 80 A, V = 0 V
−
−
−
−
−
−
0.81
0.77
77
1.25
1.2
−
V
V
SD
RR
SD
GS
= 40 A, V = 0 V
SD
GS
Reverse Recovery Time
Charge Time
T
V
= 0 V, dI /dt = 100 A/ms
ns
GS
SD
= 80 A
I
S
t
38
−
a
Discharge Time
t
39
−
b
Reverse Recovery Charge
Q
95
−
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
FDBL9406L−F085
TYPICAL CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
450
400
350
300
250
200
150
100
Current Limited by Package
V
GS
= 10 V
0.2
0
50
0
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
T , CASE TEMPERATURE (°C)
C
T , CASE TEMPERATURE (°C)
C
Figure 1. Normalized Power Dissipation vs.
Case Temperature
Figure 2. Maximum Continuous Drain Current
vs. Case Temperature
2
1
50% Duty Cycle
20%
P
DM
10%
5%
0.1
t
1
2%
t
2
1%
Z
q
(t) = r(t) x R
q
JC
JC
Peak T = P
Duty Cycle, D = t /t
x Z (t) + T
q
JC C
J
DM
Single Pulse
1
2
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
5000
1000
1000
V
GS
= 10 V
T
= 25°C
C
For temperatures above
25°C derate peak current
as follows:
100
10
100 ms
175 * T
C
Ǹ
Operation in this
area may be lim-
ited by package
I + I
ƪ ƫ
25
150
1 ms
Operation in this
area may be lim-
ited by R
10 ms
1
Single Pulse
T = Max Rated
100 ms
Single Pulse
DS(on)
J
T
C
= 25°C
100
0.1
0.00001 0.0001 0.001
0.01
0.1
1
10
0.1
1
10
100
t, RECTANGULAR PULSE DURATION (s)
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 4. Peak Current Capability
Figure 5. Forward Bias Safe Operating Area
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3
FDBL9406L−F085
TYPICAL CHARACTERISTICS
500
100
300
If R = 0
= (L)(I )/(1.3*Rated BV
If R ≠ 0
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
t
AV
− V
)
AS
DSS
DD
250
200
150
100
t
AV
= (L/R)In[(I *R)/(1.3*Rated BV
− V ) +1]
DSS DD
V
DS
= 5 V
AS
T
= 25°C
J(initial)
T = 25°C
J
10
1
T
= 150°C
J(initial)
50
0
NOTE: Refer to ON Semiconductor Application
Notes AN7514 and AN7515
T = 175°C
J
T = −55°C
J
0.001 0.01
0.1
1
10
100
1000
1
0
2
2
3
4
2.0
10
t
, TIME IN AVALANCHE (mS)
V
, GATE−TO−SOURCE VOLTAGE (V)
AV
GS
Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characteristics
400
100
350
300
V
= 10 V to 4 V
V
= 0 V
GS
GS
3.5 V
10
1
250
200
150
T = 175°C
J
0.1
100
0.01
Pulse Width = 250 ms
T = 25°C
50
0
T = −55°C
J
J
T = 25°C
J
0.001
0
0.2
0.4
0.6
0.8
1.0
1.2
0.5
V , DRAIN−SOURCE VOLTAGE (V)
DS
1.0
1.5
V
, BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 8. Forward Diode Characteristics
Figure 9. Saturation Characteristics
6
5
4
3
2
10
8
V
GS
= 10 V
I
D
= 80 A
Pulse Width = 250 ms
T = 25°C
J
6
4
V
GS
= 6 V to 3.5 V
T = 175°C
J
2
0
1
0
T = 25°C
J
0
50
100
150
200
250
300
350
3
4
5
6
7
8
9
I , DRAIN CURRENT (A)
D
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 10. Normalized RDS(on) vs. Drain
Current
Figure 11. RDS(on) vs. Gate Voltage
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4
FDBL9406L−F085
TYPICAL CHARACTERISTICS
1.8
1.6
1.4
1.2
1.0
1.4
V
I
= V
DS
= 1 mA
GS
V
= 10 V
= 80 A
D
GS
1.2
1.0
0.8
I
D
0.6
0.4
0.8
0.6
−80
−40
0
40
80
120
160
200
−80
−40
0
40
80
120
160 200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 12. Normalized RDS(on) vs. Junction
Temperature
Figure 13. Normalized Gate Threshold Voltage
vs. Temperature
1.10
1.06
1.02
100,000
10,000
1000
I
D
= 5 mA
C
ISS
C
OSS
C
RSS
0.98
0.94
100
10
V
= 0 V
GS
f = 100 KHz
−80 −40
0
40
80
120
160
200
0.1
1
10
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
40
T , JUNCTION TEMPERATURE (°C)
V
J
Figure 14. Normalized Drain−to−Source
Figure 15. Capacitance vs. Drain−to−Source
Breakdown Voltage vs. Junction Temperature
Voltage
10
8
V
DD
= 20 V
6
V
DD
= 16 V
V
DD
= 24 V
4
2
0
0
28
56
84
112
140
Q , GATE CHARGE (nC)
g
Figure 16. Gate Charge vs. Gate−to−Source
Voltage
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5
FDBL9406L−F085
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Marking
Package
Reel Size
Tape Width
Quantity
FDBL9406L−F085
FDBL9406L
H−PSOF8L
(Pb-Free / Halogen Free)
13″
24 mm
2000 Units
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
H−PSOF8L 11.68x9.80
CASE 100CU
ISSUE C
DATE 22 MAY 2023
GENERIC
MARKING DIAGRAM*
AYWWZZ
XXXXXXXX
XXXXXXXX
A
Y
= Assembly Location
= Year
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
WW = Work Week
ZZ
XXXX = Specific Device Code
= Assembly Lot Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13813G
H−PSOF8L 11.68x9.80
PAGE 1 OF 1
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