FDB9509L-F085 [ONSEMI]
PowerTrench® MOSFET，P 沟道，-40 V，-83 A，8.0 mΩ;
| 型号： | FDB9509L-F085 |
| 厂家： | 
ONSEMI |
| 描述： | PowerTrench® MOSFET，P 沟道，-40 V，-83 A，8.0 mΩ |
| 文件： | 总8页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FDB9509L-F085
Power MOSFET, Single
P-Channel
−40 V, −83 A, 8.0 mW
Features
• Low R
to Minimize Conduction Losses
DS(on)
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• Low QG and Capacitance to Minimize Driver Losses
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
8.0 mW @ −10 V
−40 V
−83 A
12.5 mW @ −4.5 V
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
VDSS
Value
−40
16
Unit
V
D
Gate−to−Source Voltage
VGS
V
Continuous Drain
Current R
T
= 25_C
−83
C
G
I
A
q
JC
D
(Notes 1, 3)
T
C
T
C
T
C
T
C
= 100_C
= 25_C
= 100_C
= 25_C
−59
93.8
46.9
−16.1
Steady
State
Power Dissipation
(Note 1)
S
P
W
A
R
D
q
JC
Continuous Drain
Current R
1, 2, 3)
(Notes
I
D
q
JA
T
C
T
C
T
C
= 100_C
= 25_C
= 100_C
−11.4
3.5
Steady
State
Power Dissipation
(Notes 1 & 2)
P
W
A
R
D
q
JA
2
1.7
D PAK−3 (TO−163AB)
CASE 418AJ
Pulsed Drain Current
T
C
= 25_C, t = 10 ms
−669
IDM
p
Operating Junction and Storage Temperature
−55 to
+175
MARKING DIAGRAM
TJ, Tstg
°C
Source Current (Body Diode)
I
S
−80
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = −64)
&Z&3&K
FDB
EAS
82
mJ
9509L
Lead Temperature for Soldering Purposes
(1/83 from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
&Z
&3
&K
= Assembly Plant Code
= Numeric Date Code
= Lot Code
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
1.6
Unit
°C/W
°C/W
FDB9509L= Specific Device Code
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
R
q
JC
43
R
q
JA
1. The entire application environment impacts the thermal resistance values
shown, they are not constants and are only valid for the particular conditions
noted.
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 6 of this data sheet.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
October, 2018 − Rev. 0
FDB9509L−F085/D
FDB9509L−F085
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Off Characteristics
Symbol
Test Condition
Min
Typ
Max
Unit
Drain to Source Breakdown Voltage
V(BR)DSS
V(BR)DSS/ T
IDSS
V
= 0 V, I = −250 mA
V
−40
GS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
J
mV/_C
20
Zero Gate Voltage Drain Current
T = 25°C
J
mA
mA
nA
−1
V
GS
= 0 V, V = −40 V
DS
T = 175°C
J
−1
Zero Gate Voltage Drain Current
IGSS
V
= 0 V, V
=
16 V
100
DS
GS
On Characteristics (Note 4)
Gate Threshold Voltage
VGS(TH)
V
GS
= V I = −250 mA
DS, D
−1
−1.7
−3
V
mV/_C
mW
Threshold Temperature Coefficient
VGS(TH)/TJ
RDS(on)
−5
Drain−to−Source On Resistance
V
= −10 V
= −4.5 V
I
I
= −80 A
= −40 A
6.4
8.0
GS
D
V
GS
9.6
12.5
D
Charges, Capacitances & Gate Resistance
Input Capacitance
V
GS
= 0 V, f = 1 MHz, V = −20 V
DS
Ciss
Coss
Crss
3400
1250
39
pF
pF
pF
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
W
R
V
GS
= 0.5 V, f = 100 kHz
21
g
Total Gate Charge
QG(TOT)
nC
V
GS
= −10 V, V = −32 V; I = −80 A
48
DS
D
V
GS
= −4.5V, V = −32 V; I = −80 A
22
DS
D
Threshold Gate Charge
Qg(th)
Qgs
V
= 0 to −1 V
6
12
GS
V
DD
= −32 V I = −80 A
D
,
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Plateau Voltage
Qgd
5
VGP
V
−3.5
Switching Characteristics
V
= −20 V, I = −80 A,
D
DD
GS
Turn−On Delay Time
Turn−On Rise Time
Turn−Off Delay Time
td(ON)
9
4
ns
ns
ns
ns
V
= −10 V, R
= 6 W
GEN
t
r
td(OFF)
200
57
Turn−Off Fall Time
t
f
Drain−Source Diode Characteristics
Source to Drain Diode Voltage
VSD
I
= −80 A, V = 0 V
−1.25
−1.2
V
−0.98
−0.9
SD
GS
I
= −40 A, V = 0 V
V
SD
GS
V
GS
= 0 V, dI /dt = 100 A/us, I = −80 A
ns
SD
S
Reverse Recovery Time
Charge Time
TRR
78
33
46
95
t
t
a
Discharge Time
b
Reverse Recovery Charge
QRR
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%
5. Switching characteristics are independent of operating junction temperatures.
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2
FDB9509L−F085
TYPICAL CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
90
80
70
60
CURRENT LIMITED BY
PACKAGE
50
40
30
20
V
GS
= −10 V
0.2
0
10
0
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
T , CASE TEMPERATURE (°C)
C
T , CASE TEMPERATURE (°C)
C
Figure 1. Normalized Power Dissipation vs.
Case Temperature
Figure 2. Maximum Continuous Drain Current
vs. Case Temperature
2
1
50% Duty Cycle
P
DM
20%
10%
5%
0.1
t
1
t
2
2%
DUTY CYCLE, D = t /t
1 2
Peak T = P X Z X R + T
C
q
q
JC
Single Pulse
J
DM
JC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
V
GS
= −10 V
T
C
= 25°C
For temperatures above 25°C
derate peak current as follows:
175 * TC
Ǹ
I + I25
ƪ ƫ
150
100
10
Single Pulse
0.00001
0.0001
0.001
0.01
0.1
1
10
t, RECTANGULAR PULSE DURATION (s)
Figure 4. Peak Current Capability
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3
FDB9509L−F085
TYPICAL CHARACTERISTICS
1000
100
If R = 0
=(L)(I )/(1.3*Rated BV
t
AV
− V
DD
)
AS
DSS
If R ≠ 0
100
10
1
t
=(L/R)In[(I *R)/(1.3*Rated BV
− V )+1]
DSS DD
AV
AS
100 ms
Starting T = 25°C
J
OPERATION IN
THIS AREA MAY
10
Starting T = 150°C
J
BE LIMITED BY
PACKAGE
1 ms
10 ms
100 ms
OPERATION IN
THIS AREA MAY
BE LIMITED BY
(on)
SINGLE PULSE
T = max rated
r
DS
J
T = 25°C
C
0.1
1
0.01
0.1
1
10
100
0.1
1
10
100
1000
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
t , TIME IN AVALANCHE (mS)
AV
Note: Refer to ON Semiconductor Application Notes AN7514
and AN7515
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching
Capability
300
200
160
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
100
10
1
V
GS
= 0 V
V
DS
= −5 V
120
80
40
0
T = 25°C
J
0.1
T = 175°C
J
0.01
T = 175°C
J
T = −55°C
J
T = −55°C
J
T = 25°C
J
0.001
1
2
3
4
5
6
0
0.2
0.4
0.6
0.8
1.0
1.2
−V , GATE−TO−SOURCE VOLTAGE (V)
GS
−V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 7. Transfer Characteristics
Figure 8. Forward Diode Characteristics
6
300
225
V
= 3.5 V
250 ms Pulse Width
T = 25°C
GS
4.0 V
4.5 V
5.0 V
7.0 V
10 V
J
V
= −10 V
GS
5
4
3
2
−7.0 V
−5.0 V
−4.5 V
150
−4.0 V
−3.5 V
75
0
1
0
250 ms Pulse Width
T = 25°C
J
0
60
120
180
240
300
0
1
2
3
4
5
−V , DRAIN−SOURCE VOLTAGE (V)
DS
−I , DRAIN CURRENT (A)
D
Figure 9. Saturation Characteristics
Figure 10. Normalized RDS(ON) vs. Drain Current
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4
FDB9509L−F085
TYPICAL CHARACTERISTICS
60
50
40
1.8
I
V
= −80 A
D
I
= −80 A
D
= −10 V
GS
1.6
1.4
1.2
1.0
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
30
20
10
0
T = 175°C
J
0.8
0.6
T = 25°C
J
2
3
4
5
6
7
8
9
10
−80
−40
0
40
80
120
160
200
−V , GATE−TO−SOURCE VOLTAGE (V)
GS
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. RDS(on) vs. Gate Voltage
Figure 12. Normalized RDS(on) vs. Junction
Temperature
1.3
1.10
1.05
1.00
V
= V
DS
= −250 mA
GS
I
D
= −5 mA
I
D
1.1
0.9
0.7
0.95
0.90
0.5
0.3
−80
−40
0
40
80
120
160
200
−80
−40
0
40
80
120
160 200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. Normalized Gate Threshold Voltage
vs. Temperature
Figure 14. Normalized Drain−to−Source
Breakdown Voltage vs. Junction Temperature
10K
1K
10
8
C
ISS
V
= −20 V
DD
V
DD
= −16 V
C
OSS
6
100
10
1
V
DD
= −24 V
4
C
RSS
2
0
f = 1 MHz
= 0 V
V
GS
0
10
20
30
40
50
0.1
1
10
40
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Q , GATE CHARGE (nC)
g
Figure 15. Capacitance vs. Drain−to−Source
Figure 16. Gate Charge vs. Gate−to−Source
Voltage
Voltage
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5
FDB9509L−F085
ORDERING INFORMATION
Device
†
Device Marking
FDB9509L
Package
Shipping
2
FDB9509L−F085
D PAK−3
3,000 / Tape & Reel
(Pb−Free, Halogen Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
DATE 11 MAR 2021
SCALE 1:1
XXXXXX = Specific Device Code
A
= Assembly Location
WL
Y
= Wafer Lot
= Year
GENERIC MARKING DIAGRAMS*
WW
W
M
G
AKA
= Work Week
= Week Code (SSG)
= Month Code (SSG)
= Pb−Free Package
= Polarity Indicator
XX
AYWW
XXXXXXXXG
AKA
XXXXXXXXG
AYWW
XXXXXX
XXYMW
XXXXXXXXX
AWLYWWG
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
IC
Standard
Rectifier
SSG
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON56370E
D2PAK−3 (TO−263, 3−LEAD)
PAGE 1 OF 1
DESCRIPTION:
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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