FDB070AN06A0-F085 [ONSEMI]
N 沟道 PowerTrench® MOSFET 60 V、80 A、6.1 mΩ;
| 型号： | FDB070AN06A0-F085 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道 PowerTrench® MOSFET 60 V、80 A、6.1 mΩ |
| 文件： | 总14页 (文件大小：1714K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FDB070AN06A0-F085
N-Channel PowerTrench® MOSFET
60V, 80A, 7mΩ
Features
Applications
rDS(ON) =6.1mΩ (Typ.), VGS = 10V, ID = 80A
Qg(tot) = 51nC (Typ.), VGS = 10V
Low Miller Charge
Motor / Body Load Control
ABS Systems
Pow ertrain Management
Low QRR Body Diode
Injection Systems
UIS Capability (Single Pulse and Repetitive
Pulse)
DC-DC converters and Off-line UPS
Distributed Pow er Architectures and VRMs
Primary Sw itch for 12V and 24V systems
Qualified to AEC Q101
RoHS Compliant
Formerly developmental type 82567
Ordering Information
Device
Output Voltage
TBD
Marking
FDB070AN06A0
Package
Shipping
FDB070AN06A0-F085
TO-263AB
Tape and Reel
© 2017 Semiconductor Components Industries, LLC
August-2017, Rev. 2
Publication Order Number:
FDB070AN06A0-F085/D
Absolute Maximum Ratings TC = 25℃ unless otherwise noted
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDSS
Parameter
Ratings
60
Unit
V
Drain to Source Voltage
VGS
Gate to Source Voltage
Drain Current
±20
V
Continuous(TC < 97℃, VGS = 10V)
80
15
A
A
ID
Continuous(TA = 25℃, VGS = 10V, RJA = 43℃/W)
Pulsed
Figure 4
190
A
EAS
PD
Single Pulse AvalancheEnergy (1)
mJ
Power dissipation
175
W
W/℃
℃
1.17
Derate above 25℃
TJ, TSTG
Operating andStorageTemperature
-55 to 175
Thermal Characteristics
Thermal Resistance Junction to Case TO-220,TO-263
0.86
62
RJC
RJA
RJA
℃/W
℃/W
℃/W
Thermal Resistance Junction to Ambient TO-220,TO-263 (2)
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
43
Notes:
1.
2.
Starting TJ = 25 ℃, L = 93 H, IAS = 64A.
Pulse width = 100s.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry.
All ON Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
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2
Electrical Characteristics TC = 25℃ unless otherw ise noted
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
60
V
ID = 250 A, VGS = 0 V
1
VDS = 50 V
VGS = 0 V
IDSS
Zero Gate Voltage DrainCurrent
A
nA
250
TC = 150 ℃
IGSS
Gate to Source Leakage Current
VGS = ±20 V
±100
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
2
4
V
VGS = VDS, ID = 250A
ID = 80A, VGS = 10V
ID = 80A, VGS = 10V,
0.0061 0.007
rDS(ON)
Drain to Source On Resistance
Ω
0.0127 0.015
TJ = 175℃
Dynamic Characteristics
CISS
COSS
CRSS
Qg(TOT)
Qg(TH)
Qgs
Input Capacitance
3000
510
pF
pF
pF
nC
nC
nC
nC
nC
VDS = 25V, VGS = 0 V,
F = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Total Gate Chargeat 10V
Threshold Gate Charge
230
VGS = 0V to 10V
VGS = 0V to 2V
51
5.4
17
66
7
VDD = 30 V
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
ID = 80 A
Ig = 1.0 mA
Qgs2
11.6
16
Qgd
Switching Characteristics (VGS = 10 V)
tON
Td(ON)
tr
Turn-On Time
Turn-On Delay Time
Rise Time
256
ns
ns
ns
ns
ns
ns
12
159
27
VDD = 30 V, ID = 80 A
VGS = 10 V, RGS = 5.6 Ω
Td(OFF)
tf
Turn-Off Delay Time
Fall Time
35
tOFF
Turn-Off Time
93
Drain-Source Diode Characteristics
ISD = 80 A
1.25
1.0
67
V
V
VSD
Source to Drain Diode Voltage
ISD = 40 A
trr
Reverse Recovery Time
ns
nC
ISD = 75 A, dISD/dt = 100 A/s
ISD = 75 A, dISD/dt = 100 A/s
QRR
Reverse Recovered Charge
80
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3
Typical Characteristics TC = 25℃ unless otherw ise noted
Figure 1.
Normalized Power Dissipation vs
Ambient Temperature
Figure 2.
Maximum Continuous Drain Current vs
Case Temperature
Figure 3.
Normalized Maximum Transient Thermal Impedance
Figure 4.
Peak Current Capability
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4
Typical Characteristics TC = 25℃ unless otherw ise noted
NOTE: Refer to ON Semiconductor Application Notes AN7514 and
AN7515
Figure 5.
Forward Bias Safe Operating Area
Figure 6.
Unclamped Inductive Switching
Capability
Figure 7.
Transfer Characteristics
Figure 8.
Saturation Characteristics
Figure 9.
Drain to Source On Resistance vs Drain
Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
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5
Typical Characteristics TC = 25℃ unless otherw ise noted
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source Breakdown
Voltage vs Junction Temperature
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Current
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6
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 17. Gate Charge Test Circuit
Figure 19. Switching Time Test Circuit
Figure 16. Unclamped Energy Waveforms
Figure 18. Gate Charge Waveforms
Figure 20. Switching Time Waveforms
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7
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and
the thermal resistance of the heat dissipating path
determines the maximum allow able device pow er
dissipation, PDM, in an application. Therefore the
application’s ambient temperature, TA( ℃ ), and
thermal resistance RθJA(℃/W) must be review ed to
ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship
and serves as the basis for establishing the rating of
the part.
In using surface mount devices such as the TO-263
package, the environment in w hich it is applied w ill
have a significant influence on the part’s current and
maximum pow er dissipation ratings.
determination of PDM is complex and influenced by
many factors:
Precise
Figure 21. Thermal Resistance vs Mounting Pad
Area
1. Mounting pad area onto w hich the device is
attached and w hether there is copper on one
side or both sides of the board.
2. The number of copper layers and the thickness
of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse
w idth, the duty cycle and the transient thermal
response of the part, the board and the
environment they are in.
ON Semiconductor provides thermal information to
assist the designer’s
preliminary
application
evaluation. Figure 21 defines the RJA for the device
as a function of the top copper (component side)
area. This is for a horizontally positioned FR-4 board
w ith 1oz copper after 1000 seconds of steady state
pow er with no air flow . This graph provides the
necessary information for calculation of the steady
state junction temperature or pow er dissipation. Pulse
applications can be evaluated using the ON
Semiconductor device Spice thermal model or
manually utilizing the normalized maximum transient
thermal impedance curve.
Thermal resistances corresponding to other copper
areas can be obtained from Figure 21 or by
calculation using Equation 2 or 3. Equation 2 is used
for copper area defined in inches square and equation
3 is for area in centimeters square. The area, in
square inches or square centimeters is the top copper
area including the gate and source pads.
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8
PSPICE Electrical Model
.SUBCKT FDB070AN06A0 2 1 3 ; rev March 2003
Ca 12 8 1.5e-9
Cb 15 14 1.5e-9
Cin 6 8 2.9e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 62
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 4.8e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 3e-9
RLgate 1 9 48
RLdrain 2 5 10
RLsource 3 7 3
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.3e-3
Rgate 9 20 2.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3.1e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))}
.MODEL DbodyMOD D (IS=7.6E-12 N=1.04 RS=2.2e-3 TRS1=2.7e-3 TRS2=2e-7
+ CJO=1.6e-9 M=0.55 TT=5e-12 XTI=3.9)
.MODEL DbreakMOD D (RS=8e-1 TRS1=5e-4 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.05e-9 IS=1e-30 N=10 M=0.45)
.MODEL MmedMOD NMOS (VTO=3.7 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.7)
.MODEL MstroMOD NMOS (VTO=4.7 KP=100 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.01 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=27 RS=0.1)
.MODEL RbreakMOD RES (TC1=7.1e-4 TC2=-5.5e-7)
.MODEL RdrainMOD RES (TC1=1.7e-2 TC2=4e-5)
.MODEL RSLCMOD RES (TC1=3e-3 TC2=1e-5)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.2e-3 TC2=-1.5e-5)
.MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
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9
SABER Electrical Model
rev March 2003
template FDB070AN06A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=7.6e-12,nl=1.04,rs=2.2e-3,trs1=2.7e-3,trs2=2e-7,cjo=1.6e-9,m=0.55,tt=5e-12,xti=3.9)
dp..model dbreakmod = (rs=8e-1,trs1=5e-4,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.05e-9,isl=10e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=3.7,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.7,kp=100,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.01,kp=0.03,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.5)
c.ca n12 n8 = 1.5e-9
c.cb n15 n14 = 1.5e-9
c.cin n6 n8 = 2.9e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 62
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 4.8e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 3e-9
res.rlgate n1 n9 = 48
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u,
w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod,
l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=7.1e-4,tc2=-5.5e-7
res.rdrain n50 n16 = 1.3e-3, tc1=1.7e-2,tc2=4e-5
res.rgate n9 n20 = 2.7
res.rslc1 n5 n51 = 1e-6, tc1=3e-3,tc2=1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.1e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.2e-3,tc2=-1.5e-5
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1.3e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10))
}
}
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10
PSPICE Thermal Model
REV 23 March 2003
FDB070AN06A0T
CTHERM1 TH 6 3.5e-3
CTHERM2 6 5 1.7e-2
CTHERM3 5 4 1.8e-2
CTHERM4 4 3 1.9e-2
CTHERM5 3 2 4.7e-2
CTHERM6 2 TL 7e-2
RTHERM1 TH 6 2e-2
RTHERM2 6 5 7e-2
RTHERM3 5 4 1e-1
RTHERM4 4 3 1.5e-1
RTHERM5 3 2 1.6e-1
RTHERM6 2 TL 1.85e-1
SABER Thermal Model
SABER thermal model FDB070AN06A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.5e-3
ctherm.ctherm2 6 5 =1.7e-2
ctherm.ctherm3 5 4 =1.8e-2
ctherm.ctherm4 4 3 =1.9e-2
ctherm.ctherm5 3 2 =4.7e-2
ctherm.ctherm6 2 tl =7e-2
rtherm.rtherm1 th 6 =2e-2
rtherm.rtherm2 6 5 =7e-2
rtherm.rtherm3 5 4 =1e-1
rtherm.rtherm4 4 3 =1.5e-1
rtherm.rtherm5 3 2 =1.6e-1
rtherm.rtherm6 2 tl =1.85e-1
}
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Physical Dimensions
Figure 22. TO-263 2L (D2PAK), 4.445 x 10.16 x 15.24mm, TAPE REEL
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United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A
listing of ON Semiconductor’s product/patent coverage maybe accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make
changes without further notice to anyproducts herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitabilityof its products for any
particular purpose, nor does ON Semiconductor assume any liabilityarising out of the application or use of any product or circuit, and specificallydisclaims anyand all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor
products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by
ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and
actual performance may varyover time. All operating parameters, including “Typicals” must be validated for each customer application bycustomer’s technical experts.
ON Semiconductor does not convey anylicense under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for
use as a critical component in life support systems or anyFDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or
any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in anymanner.
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相关型号：
FDB070AN06A0_F085
Power Field-Effect Transistor, 15A I(D), 60V, 0.007ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, ROHS COMPLIANT PACKAGE-3/2
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