FAN7340MX [ONSEMI]
LED 背光灯驱动升压开关;
| 型号： | FAN7340MX |
| 厂家： | 
ONSEMI |
| 描述： | LED 背光灯驱动升压开关 开关 驱动 接口集成电路 |
| 文件： | 总18页 (文件大小：1278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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July 2013
FAN7340
LED Backlight Driving Boost Switch
Features
Description
The FAN7340 is a single-channel boost controller that
integrates an N-channel power MOSFET for PWM
dimming using Fairchild’s proprietary planar Double-
diffused MOS (DMOS) technology.
.
.
Single-Channel Boost LED Switch
Internal Power MOSFET for PWM Dimming:
RDS(on) = 3.4 Ω at VGS=10 V, BVDSS=400 V
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Current Mode PWM Control
The IC operates as a constant-current source for driving
high-current LEDs.
Internal Programmable Slope Compensation
Wide Supply Voltage Range: 10 Vto 35 V
LED Current Regulation: ±1%
Programmable Switching Frequency
Analog and PWM Dimming
It uses Current Mode control with programmable slope
compensation to prevent subharmonic oscillation. The IC
provides protections including: open-LED protection,
over-voltage protection, and direct-short protection for
high system reliability.
Wide Dimming Ratio: On Time=10 µs to DC
Cycle-by-Cycle Current Limiting
Thermal Shutdown: 150°C
The IC internally generates a FAULT signal with delay if
an abnormal LED string condition occurs. PWM dimming
and analog dimming functions can be implemented
independently. Internal soft-start prevents inrush current
flowing into output capacitor at startup.
Open-LED Protection (OLP)
Over-Voltage Protection (OVP)
Over-Current Protection (OCP)
Error Flag Generation (for External Load Switch)
Internal Soft-Start
16-Lead SOIC Package
Applications
.
.
.
LED Backlight for LCD TV
LED Backlight for LCD Monitor
LED Lighting
Ordering Information
Operating
Temperature
Range
Packaging
Part Number
Package
Method
FAN7340MX
-40°C to +125°C
16-Lead, Small-Outline Integrated Circuit (SOIC)
Tape & Reel
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
Block Diagram
20µs Delay
3V
-
OVP
+
OVP
100mV
FAULT
OLP
TSD
1µs
Delay
+
S
R
Q
ADIM*4
1.4~4V
OCP
-
POR
640µs at 200kHz
Auto-Restart
Current
Sense
PWM
-
1/4
gm
-
+
ADIM
CMP
R
S
Dim off
0.3~3V
+
DRV
CS
Q
Gate
Driver
PWM
Slope
Compensation
5k
100mV
-
Burst
Operation
+
0.5V
CLK+LEB
4V
+
Switch Off
-
16 Steps
0.5V
Internal Soft-Start 3ms at 200kHz
Oscillator
RT
GND
45µA
Drain
-
UVLO 9V
PWM
+
VCC
ENA
OLPi
Dim off
Hys. 1.0V
-
1.22V
BDIM
+
OLP
Hys. 70mV
Current
Sense
+
0.2V
5µs Delay
OLPi
Voltage Reference
& Internal Bias
-
40.96ms
at 200kHz
Debounce
Time
REF
5V, max. 3mA
PWM
End of Soft-Start
SEN
BDIM
Figure 1. Internal Block Diagram
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
2
Pin Assignments
1
2
3
4
5
6
7
8
16
15
14
13
12
VCC
BDIM
DRV
GND
CS
ADIM
CMP
OVP
ENA
REF
FAULT
10
9
DRAIN
DRAIN
RT
SENSE
Figure 2. Package Diagram
Pin Definitions
Pin #
Name
VCC
Description
1
2
3
This pin is the supply voltage of the IC.
DRV
GND
This pin is the gate drive signal of the boostswitch.
This pin is the ground of the IC.
This pin is for sensing the current flowing through an external MOSFET. It includes a built-in
300 ns blanking time. The peak of the current flowing through the MOSFET is limited to this
pin voltage. Slope compensation of the boost controller can be programmed through the
series resistor of this pin.
4
CS
5
6
7
REF
FAULT
RT
This pin is the 5 V reference voltage pin. Maximum current capability is 3 mA.
This pin is for indicating the fault signal. This pin is connected to the open drain. When OLP
protection is occurred, the FAULT pin is pulled HIGH.
Oscillator frequency set of the boost switch (50 kHz ~ 300 kHz).
This pin is for sensing the current flowing through the LEDs. Asensing resistor is connected
from this pin to ground. This pin is connected to the negative input of the internal error
amplifier.
8
SENSE
9, 10
12
DRAIN
ENA
Drain pin of PWM dimming power MOSFET.
Enable input pin. If voltage of this pin is higher than 1.22 V, IC is starting to operate. If the
voltage of this pin is lower than 1.15 V, the IC stops operating.
Over-voltage protection input pin. Output voltage of the boost circuit is connected to this pin
through a resistor divider circuit. If this pin voltage is higher than 3 V, OVP is triggered.
13
14
15
16
OVP
CMP
ADIM
BDIM
This pin is the error amplifier output. Typically, a compensation capacitor and resistor are
connected to this pin from the ground.
This pin is for setting the current flowing through the LEDs. This pin is connected to the
positive inputs of the internal error amplifier. Linear voltage range of ADIM is 0.3 V~3.0 V.
This pin is for the burst dimming signal. If this pin voltage is HIGH, the internal dimming
MOSFET is turned on. If this pin voltage is LOW, the dimming MOSFET is turned off.
Note:
1. Pin 11 is a “No Connect” pin (not shown in Figure 2).
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25C unless otherwise specified.
Symbol
VCC
Parameter
Min.
10
Max.
35
Unit
V
Supply Voltage
TA
Operating Temperature Range
Junction Temperature
-40
+125
+150
+150
120
C
TJ
C
TSTG
ӨJA
Storage Temperature Range
Thermal Resistance Junction-to-Ambient(2, 3)
Power Dissipation
-65
C
C/W
W
PD
0.9
Notes:
2. Thermal resistance test board;size 76.2 mm x 114.3 mm x 1.6 mm (1S0P); JEDEC standard: JESD51-2, JESD51-
3.
3. Assume no ambient airflow.
Pin Breakdown Voltage
Pin #
Name
Value
35
Unit
Pin #
Name
Value
400
Unit
1
2
3
4
5
6
7
8
VCC
DRV
GND
CS
V
V
V
V
V
V
V
V
9
DRAIN
DRAIN
N/A
V
V
V
V
V
V
V
V
20
10
11
12
13
14
15
16
400
6
6
ENA
6
6
6
6
6
REF
OVP
FAULT
RT
35
6
CMP
ADIM
BDIM
SENSE
6
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
4
Electrical Characteristics
For typical values, TA = 25°C and VCC = 15 V unless otherwise specified. Specifications to -40°C ~ 125°C are
guaranteed by design based on final characterization results.
Symbol
Parameter
Condition
Min.
Typ.
Max. Unit
Supply Voltage Section
VCC
ISD
Input DC Supply Voltage Range(4)
10
35
4
V
Shutdown Mode Supply Current
BDIM Connected to GND
2
mA
Under-Voltage Lockout Section
Start Threshold Voltage
Start Threshold Voltage Hysteresis
Standby Current
8.3
0.5
9.0
1.0
9.7
1.5
V
V
V
th
V
th,hys
Ist
VCC=V -0.2
200
300
μA
th
ON/OFF Section
On-State Input Voltage
Off-State Input Voltage
2
5
V
V
Von
Voff
0.8
Error Amplifier Section
Gm
AV_ro
AV
Error Amplifier Transconductance(4)
VADIM=1 V
100
300
20
500
µmho
MΩ
dB
mV
µA
µA
V
Error Amplifier Output impedance(4)
Error Amplifier Open-Loop Gain(4)
Input Offset Voltage
60
Voffset
Isin
VADIM=1 V
-10
100
100
0
10
300
300
3
CMP Sink Current
VADIM=1 V, VSENSE=2 V
VADIM=1 V, VSENSE=0 V
200
200
Isur
CMP Source Current
V
IDR
Input Differential Voltage Range
Output Voltage Range
VO
0.7
4.0
V
Oscillator Section
Min.
50
200
300
90
kHz
kHz
kHz
%
fosc
Boost Oscillator Frequency
Maximum Duty Cycle(4)
RT=100 kΩ
Max.
190
86
210
94
Dmax
Reference Section
VREF
5VRegulation Voltage
4.9
5.0
5.1
25
25
V
VREF,Line
VREF,Load
5VLine Regulation
5VLoad Regulation
mV
mV
0<I5<3 mA
PWM Dimming Section
VPDIM,L
VPDIM,H
RPDIM
PWM Dimming Input Low Voltage
0.8
5
V
V
PWM Dimming Input High Voltage
2
PWM Dimming Pull-Down Resistance
100
160
220
kΩ
FET Section (for Dimming)
BVDSS
IDSS
Drain-Source Breakdown Voltage(4)
400
V
VCC=0 V, ID=250 μA
Zero-Gate-Voltage Drain Current(4)
VDS=250 V, TA=25°C
1
30
µA
RDS(ON)
Drain-Source On-State Resistance
VGS=10 V, ID=1 A
3.4
Ω
CISS
Input Capacitance(4)
Output Capacitance(4)
VDS=25 V, VGS=0V, f=1 MHz
VDS=25 V,VGS=0V, f=1 MHz
173
30
225
40
pF
pF
COSS
Continued on the following page…
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
5
Electrical Characteristics (Continued)
For typical values, TA = 25°C and VCC = 15 V, unless otherwise specified. Specifications to -25°C ~ 85°C are
guaranteed by design based on final characterization results.
Symbol
Parameter
Condition
Min.
Typ.
Max. Unit
Output Section (Boost / Dimming)
VDRV
Vuv
Idsur
Idsin
trh
Gate Output Voltage
VCC=15 V
10.8
-0.5
80
11.8
12.8
0.5
V
V
Gate Output Voltage Before Startup
Gate Output Drive Source Current(4)
Gate Output Drive Sink Current(4)
Gate Output Rising Time (Boost)(4)
Gate Output Falling Time (Boost) (4)
180
180
200
120
280
280
mA
mA
ns
ns
80
CL=2.0 nF
CL=2.0 nF
tfl
Current Sense Section
tblank
Leading-Edge Blanking(4)
150
300
450
180
ns
ns
Delay to Output of Current-Limit
Comparator(4)
tdelay,cl
Offset Voltage of Current-Limit
Comparator(4)
Voffset,clc
-20
36
20
54
mV
Slope Compensation Section
Islope
Ramp Generator Current
Slope Compensation Resistor (4)
45
5
µA
Rslope
kΩ
Soft-Start Section
tss
Soft-Start Period(4)
fosc=200 kHz
3
ms
µs
Protection Section
Delay for Triggering Over-Voltage
td,ovp.tr
15
10
20
25
18
Protection(4)
Delay for Releasing Over-Voltage
Protection(4)
Delay for Over-Current Protection(4)
td,ovpr
td.ocp
tAR
14
1
µs
µs
µs
Auto-Restart Time for Over-Current
Protection(4)
Delay for Triggering Open-LED Protection(4)
fosc=200 kHz
fosc=200 kHz
640
td,olpi
td,olp
3
5
7
µs
ms
V
Delay for Open-LED Protection
40.96
3.00
0.1
V
Over-Voltage Protection Threshold Voltage
2.85
3.15
th,ovp
Vhys,ovp Over-Voltage Protection Voltage Hysteresis
Boost Switch Current Limit Threshold
V
V
0.45
0.50
0.55
V
V
th.csocp
Voltage
1.4
(Min.
Clamp)
4.0
(Max.
Clamp)
LED Over-Current Protection Threshold
Voltage
V
4.0xVADIM
th,ocp
V
Open-LED Protection Threshold Voltage(4)
Thermal Shutdown Temperature(4)
Thermal Shutdown Hysteresis(4)
0.15
140
0.20
150
20
0.25
160
V
th,olp
TSD
THYS
°C
°C
Notes:
4. These parameters, although guaranteed, are not tested in production.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
6
Typical Performance Characteristics
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
9.9
9.7
9.5
9.3
9.1
8.9
8.7
8.5
8.3
8.1
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 3. Start Threshold Voltage vs. Temperature
Figure 4. Start Threshold Voltage Hysteresis
vs. Temperature
350
300
250
200
150
100
50
4.5
4
3.5
3
2.5
2
1.5
1
0.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 5. Standby Current vs. Temperature
Figure 6. Shutdown Mode Supply Current vs.
Temperature
1.4
1.3
1.35
1.3
1.25
1.2
1.15
1.1
1.25
1.2
1.15
1.1
1.05
1
1.05
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 7. On-State Input Voltage vs. Temperature
Figure 8. Off-State Input Voltage vs. Temperature
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
7
Typical Performance Characteristics (Continued)
600
500
400
300
200
100
0
14
10
6
2
-2
-6
-10
-14
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 9. Error Amplifier Transconductance
vs. Temperature
Figure 10. Input Offset Voltage vs. Temperature
350
350
300
250
200
150
100
50
300
250
200
150
100
50
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 11. CMP Sink Current vs. Temperature
Figure 12. CMP Source Current vs. Temperature
215
210
205
200
195
190
185
96
94
92
90
88
86
84
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 13. Boost Oscillator Frequency vs. Temperature
Figure 14. Maximum Duty Cycle vs. Temperature
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
8
Typical Performance Characteristics (Continued)
5.15
5.1
1.8
1.7
1.6
1.5
1.4
1.3
1.2
5.05
5
4.95
4.9
4.85
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 15. 5V Regulation Voltage vs. Temperature
Figure 16. PWM Dimming Input High Voltage
vs. Temperature
1.7
1.6
1.5
1.4
1.3
1.2
1.1
240
220
200
180
160
140
120
100
80
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 17. PWM Dimming Input Low Voltage
vs. Temperature
Figure 18. PWM Dimming Pull-Down Resistance
vs. Temperature
300
250
200
150
100
50
13.5
13
12.5
12
11.5
11
10.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 19. Gate Output Voltage vs. Temperature
Figure 20. Gate Output Drive Sink Current
vs. Temperature
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
9
Typical Performance Characteristics (Continued)
0.85
55
51
47
43
39
35
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 21. Ramp Generator Current vs. Temperature
Figure 22. Auto-Restart Time for OCP
vs. Temperature
3.2
3.15
3.1
0.2
0.16
0.12
0.08
0.04
0
3.05
3
2.95
2.9
2.85
2.8
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Temperature, [℃]
Figure 23. OVP Threshold Voltage vs. Temperature
Figure 24. OVP Hysteresis Voltage vs. Temperature
55
50
45
40
35
30
25
-50
-25
0
25
50
75
100
125
Temperature, [℃]
Figure 25. Delay for Over-Current Protection vs. Temperature
© 2013 Fairchild Semiconductor Corporation
FAN7340 • 1.0.1
www.fairchildsemi.com
10
Functional Description
The FAN7340 operates as a constant-current source for
driving high-current LEDs. It uses Current-Mode control
with programmable slope compensation to prevent sub-
harmonic oscillation.
V
GATE
The IC provides protections such as open-LED
protection, over-voltage protection, and over-current
protection for improved system reliability. The IC
internally generates a FAULT OUT signal with a delay in
case an abnormal LED string condition occurs. PWM
dimming and analog dimming functions can be
implemented independently. Internal soft-start prevents
inrush current flowing into output capacitor at startup.
Circuit operation is explained in the following sections.
VLED
VCMP
Soft-Start Period
ILED
t
Figure 26. Soft-Start Waveforms
VCC Under-Voltage Lockout (UVLO)
LED Current Setting
During the boost converter operating periods, the output
LED current can be set by equation:
An internal regulator provides the regulated 5 V used to
power the IC. The Under-Voltage Lockout (UVLO) turns
off the IC in the event of the voltage dropping below the
specific threshold level. The UVLO circuit inhibits
powering the IC until a voltage reference is established,
up to predetermined threshold level.
ꢧꢨꢣꢩꢅꢪꢔ
ꢣꢤꢥꢦ
ꢃ
(3)
where ADIM(V) is
ꢫꢁꢥꢬꢁꢥ ꢭ ꢝꢞꢮΩ
Enable
ADIM pin applied voltage and, RSENSE is the sensing
Applying voltage higher than 1.22 V (typical) to the ENA
pin enables the IC. Applying voltage lower than 1.15 V
(typical) to the ENA pin disables the IC. If ENA pin
voltage is higher than 1.22 V (typical) and VCC is higher
than 9.0 V(typical.), the IC starts to supply 5 Vreference
resistor value. An additional 60 mΩ comes from an
internal wire bonding resistor. To calculate LED
current precisely, consider the wire bonding resistor.
Analog Dimming and PWM Dimming
voltage from VCC
.
Analog dimming is achieved by varying the voltage level
at the ADIM pin. This can be implemented either with a
potentiometer from the VREF pin or from an external
voltage source and a resistor divider circuit. The ADIM
voltage level is adjusted to be the same as the feedback
level (VSENSE). A VADIM range from 0.3 V to 3 V is
recommended.
Oscillator (Boost Switching Frequency)
Boost switching frequency is programmed by the value
of the resistor connected from the RT pin to ground. RT
pin voltage is set to 2 V. The current through the RT pin
resistor determines boost switching frequency according
to formula:
PWM dimming (BDIM) helps achieve a fast PWM
dimming response in spite of the shortcomings of the
boost converter. The PWM dimming signal controls three
nodes in the IC; gate signal to the switching FET, gate
signal to the dimming FET, and output connection of the
trans-conductance amplifier. When the PWM dimming
signal is HIGH, the gates of the switching FET and
dimming FET are enabled. At the same time, the output
of the transconductance ap-amp is connected to the
compensation network. This allows the boost converter
to operate normally.
ꢄ
ꢍ ꢐ
ꢗꢘꢙ
ꢕꢖ
ꢀꢁꢂ ꢃ ꢅ
(1)
ꢍ
ꢐ
ꢔ
ꢆꢇꢈꢉꢊꢋꢌ ꢎꢏ ꢑꢒꢉꢓ ꢊꢄꢓ
Soft-Start Function at Startup
During initial startup, the switching device can be
damaged due to the over-current coming from the input
line by the negative control. This can result in the initial
overshoot of the LED current. Therefore, during initial
startup, the soft-start control gradually increases the duty
cycle so that the output voltage can rise smoothly to
control inrush current and overshoot.
Dynamic Contrast Ratio
FAN7340 adapts the soft-start function in the boost
converter stage. During soft-start period, boost switch
turn-on duty is limited by clamped CMP voltage. The
soft-start period is dependent on boost switching
frequency, which is decided by the RT resistor (Equation
(1)). Soft-start period is set to be cumulative time when
the BDIM (PWM dimming) signal is HIGH:
The Dynamic Contrast Ratio (DCR) means the maximum
contrast ratio achievable by adjusting the amount of light
(dimming) of the screen instantaneously using the
backlight during the extremely short period of time.
FAN7340 can normally drive the LED backlight under
0.1% dimming duty cycle at 200 Hz dimming frequency.
Even operating at 5 µs-dimming FET turn-on time and
extremely low dimming duty, FAN7340 can operate
LEDs with normal peak current level.
(2)
ꢚꢚꢚꢚꢚꢚꢚꢛꢜꢜ ꢃ ꢝꢞꢞꢚꢟꢚ ꢀꢁꢂꢚꢍꢠꢡꢢꢐ
© 2013 Fairchild Semiconductor Corporation
FAN7340 • 1.0.1
www.fairchildsemi.com
11
Internal Dimming MOSFET
Iinductor
Ipeak=45µA
m
A dimming MOSFET (400 V N-channel MOSFET; such
as FDD3N40) is incorporated in the FAN7340. The
power transistor is produced using Fairchild’s
proprietary, planar stripe, DMOS technology. This
advanced technology is tailored to minimize on-state
m1 m2
Iramp
Ts
R1
5k
VCS
VSC
VS
resistance (RDS(on)=3.4 ), to provide superior switching
performance. This device is suited for high-efficiency
SMPS and shows desirable thermal characteristic during
operation. To prevent initial LED current overshoot at low
VADIM levels, gate resistance of the internal dimming FET
RS
VCMP
Figure 27. Slope Compensation Block Diagram
is designed as 5 kexperimentally.
Cycle-by-Cycle Over-Current Protection
Feedback Loop Compensation
In boost topology, the switch can be damaged in
abnormal conditions (inductor short, diode short, output
short). It is always necessary to sense the switch current
to protect against over-current failures. Switch failures
due to excessive current can be prevented by limiting Id.
Stable closed-loop control can be accomplished by
connecting a compensation network between COMP and
GND. The compensation needed to stabilize the
converter can be either a Type-I circuit (a simple
integrator) or a Type-II circuit (and integrator with and
additional pole-zero pair). The type of the compensation
circuit required is dependent on the phase of the power
stage at the crossover frequency.
Id
DRV
FAN7340 adopts a Type-II compensator circuit.
Programmed Current Control
5k
vcs
CS
FAN7340 uses a Current-Mode control method. Current-
Mode control loops: an outer feedback loop that senses
output voltage (current) and delivers a DC control
voltage to an inner feedback loop, which senses the
peak current of the inductor and keeps it constant on a
pulse-by-pulse basis. One of the advantages of the
Current-Mode control is line/load regulation, which is
corrected instantaneously against line voltage changes
without the delay of an error amplifier.
CLK+LEB
R1
RS
+
Switch Off
-
0.5V
Figure 28. Cycle-by-Cycle OCP Circuit
When the voltage drops at R1 and RS exceed a
threshold of approximately 0.5 V, the power MOSFET
over-current function is triggered after minimum turn-on
time or LEB time (300 ns).
Programmable Slope Compensation
The peak voltage level at CS terminal:
When the power converter operates in Continuous
Conduction Mode (CCM), the current programmed
controller is inherently unstable when duty is larger than
50%, regardless of the converter topology. The
FAN7340 uses a Peak-Current-Mode control scheme
with programmable slope compensation and includes an
internal transconductance amplifier to accurately control
the output current over all line and load conditions.
ꢅ
ꢔ
ꢪꢯꢰꢱꢲꢳꢴꢎ ꢃ ꢵꢶꢷ ꢊ ꢫꢄ ꢭ ꢫꢰ ꢊ ꢨꢛꢰ ꢭ ꢸꢹ ꢊ ꢫꢰ
(4)
Choose the boostswitch current-sensing resistor (RCS):
ꢞꢈꢻꢶ
ꢸꢤꢱꢲꢳꢴꢎ
ꢫꢂꢁ
ꢺ
(5)
Open-LED Protection (OLP)
An internal Rslope resistor (5 kΩ) connected to sensing
resistor RS and an external resistor R1 can control the
slope of VSC for the slope compensation. Although the
normal operating mode of the power converter is DCM,
the boost converter operates in CCM in the case of rapid
LED current increase. As a result, slope compensation
circuit is an important feature.
After the first PWM dimming-HIGH signal, the feedback
sensing resistor (RSENSE) starts sensing the LED
current. If the feedback voltage of the SENSE pin drops
below 0.2 V, the OLP triggers to generate an error flag
signal. Because OLP can be detected only in PWM
dimming-HIGH; if OLP detecting time is over 5 μs, PWM
dimming signal is pulled HIGH internally regardless of
external dimming signal. If OLP signal continues over
blanking time, an error flag signal is triggered.
The value of an external series resistor (R1) can be
programmed by the user. In normal DCM operation, 5 k
Ω is recommended.
OLP blanking time is dependent on boost switch
frequency per Equation (6). FAULT OUT signal is made
through the FO pin, which needs to be connected 5 V
reference voltage through a pull-up resistor. In normal
operation, FO pin voltage is pulled down to ground. In
OLP condition, FO pin voltage is pulled HIGH.
ꢼꢽꢈꢾꢿꣀ ꢃ ꣁꣂꣃꢻꢚꢟꢚ ꢀꢁꢂꢚꢍꢠꢡꢢꢐ
(6)
© 2013 Fairchild Semiconductor Corporation
FAN7340 • 1.0.1
www.fairchildsemi.com
12
In system operation, OLP is triggered in only direct-short
condition. Direct short means that some point of the LED
string is shorted to set ground. In direct-short condition,
the boost controller cannot control the LED current and a
large current flows into the LED string directly from input
power. To prevent this abnormal condition, the FO signal
is used to turn off input power or the total system. FO
signal is only triggered in OLP condition.
LED Over-Current Protection (OCP)
The primary purpose of the over-current protection
function is to protect the internal dimming MOSFET from
excessive current. The OCP is triggered when the
feedback voltage meets the clamping level (1.4 V ~ 4 V)
of the ADIM voltage x4. At 1 μs delay after the OCP is
triggered, the IC turns off both the boost FET and
dimming FET and restarts the gate signal every tAR
automatically. tAR can be calculated as:
V
8192/f
seconds
FO
(7)
꣄ꣅ ꢃ ꣂꢻꣁꢚꢟꢚ ꢀꢁꢂꢚꢍꢠꢡꢢꢐ
VSENSE
0.2V
1. When VADIM=0.3 V(VADIMx4=1.2 V).
2. OCP threshold level is set to 1.4 V.
3. OCP is triggered at feedback voltage level = 1.4 V.
Dimming
Time
Dimming
off
Dimming
off
VSENSE=1.4V
VSENSE
OLPi
If OLPi is triggerd,
Dimming is pulled
to 100% full duty
OLP Released
VSENSE>0.2V
Triggered
VSENSE<0.2V
over 5µs
VADIM=0.3V
GATE
Figure 29. Open-LED Protection
In LED open load condition, OVP is triggered ahead of
OLP.
Over-Voltage Protection (OVP)
Figure 32. OCP Waveforms at VADIM=0.3 V
Over-voltage protection is triggered when the voltage of
the external output voltage trip point meets 3 V. After
triggering OVP, the dimming switch and boost switch are
turned off. The protection signal is recovered when the
output voltage divider is below 2.9 V.
1.
2.
3.
When VADIM=0.8 V(VADIM x4=3.2 V).
OCP threshold level is set to 3.2 V.
OCP is triggered at VSENSE = 3.2 V.
VLED
(Open)
VSENSE=3.2V
VSENSE
ROVP1
VADIM=0.8V
GATE
OVP
3V
ROVP2
Figure 33. OCP Waveforms at VADIM=0.8 V
When VADIM=1.2 V(VADIM x4=4.8 V).
OCP threshold level is set to 4.0 V.
OCP is triggered at VSENSE = 4.0 V.
Figure 30. Over-Voltage Trip Point
1.
2.
3.
VOVP
3.0V
2.9V
VSENSE=4.0V
Boost
Gate
VSENSE
Time
VADIM=1.2V
GATE
Figure 31. OVP Trigger and Release
Figure 34. OCP Waveforms at VADIM=1.2 V
© 2013 Fairchild Semiconductor Corporation
FAN7340 • 1.0.1
www.fairchildsemi.com
13
Typical Application Circuit (Boost Topology for LED Backlight)
Output current
(Rated Voltage)
Application
Input Voltage Range Rated Output Power
LED
LED Backlight TV
250 mA (230 V)
72-LEDs/1-String
120 VDC 10%
Features
.
.
.
High Efficiency
Constant Current Boost Converters
High-Voltage, High-Current LED Driving
Typical Application Circuit
D1
CN2
1
CN1
Vin
Vin
Vin
GND
GND
GND
L1
1
2
3
4
5
6
200uH/PC44
N.C
2
3
4
5
6
N.C
C1
22uF/160V
VLED
VLED
LED1
LED2
FFD04H60S
C2
R1 10R
CON6
47uF/400V
R2
300k
CON6
R21
330k
0
Q1
FDPF7N50F
D2 1SS355 R9 0R
0
R4
R5
100K
300k
IC1
1
R22
330k
VCC
16
R6
300k
BDIM
VCC
DRV
GND
CS
BDIM
ADIM
CMP
OVP
ENA
R7
OVP
C12
1.2n
R23
10k
D3
1N4148
5.1k
2
3
4
5
6
7
8
15
ADIM
C13
R10
11k
1.2n
14
On/Off
VCC
C5
0
13
12
OVP
CN3
open
R11
15k
1
2
3
4
5
6
C6
6.8n
VCC
GND
FO
BDIM
ADIM
On/Off
C3
C4
1u
FO
C7
100n
REF
FO
ENA
10uF/50V
C8
10n
R19
10k
CON6
FO
ENA
TP1
R12
100K
10
9
On/Off
RT
DRAIN
DRAIN
ADIM
R13 3.9K
R14
20K
R20
100k
TP
SENSE
R15
220K
C10
1.2n
R16
2.7R/1W
FAN7340
BDIM
R17 3.9K
Vin
Vout
Output current
:
120V
: 230V
R18
220K
C11
1.2n
: 250mA
Switching frequency
:
200kHz
0
Figure 35.
Typical Application Circuit
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
Physical Dimension
10.00
9.80
A
8.89
16
9
B
1.75
4.00
3.80
6.00
5.6
1
8
PIN ONE
INDICATOR
0.51
0.35
1.27
(0.30)
1.27
0.65
M
0.25
C B A
LAND PATTERN RECOMMENDATION
1.75 MAX
1.50
SEE DETAIL A
1.25
0.25
0.19
0.25
0.10
C
0.10
C
0.50
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AC, ISSUE C.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD
FLASH AND TIE BAR PROTRUSIONS
GAGE PLANE
0.36
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
E) LANDPATTERN STANDARD: SOIC127P600X175-16AM
F) DRAWING FILE NAME: M16AREV12.
SEATING PLANE
0.90
0.50
(1.04)
DETAIL A
SCALE: 2:1
Figure 36. 16-Lead, Small Outline Integrated Circuit (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings maychange in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2013 Fairchild Semiconductor Corporation
FAN7340 • 1.0.1
www.fairchildsemi.com
15
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7340 • 1.0.1
16
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