FAN5909UCX [ONSEMI]
Multi-Mode Buck Converter;
| 型号： | FAN5909UCX |
| 厂家： | 
ONSEMI |
| 描述： | Multi-Mode Buck Converter 开关 |
| 文件： | 总15页 (文件大小：665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAN5909
Multi-Mode Buck Converter
with LDO Assist for GSM /
EDGE, 3 G/3.5 G and 4 G PAs
Description
The FAN5909 is a high−efficiency, low−noise, synchronous,
step−down, DC−DC converter optimized for powering Radio
Frequency (RF) Power Amplifiers (PAs) in handsets and other mobile
applications. Load currents up to 2.5 A are allowed, which enables
GSM / EDGE, 3 G/3.5 G, and 4G platforms under very poor VSWR
conditions.
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The output voltage may be dynamically adjusted from 0.40 V to
WLCSP
16 BUMP
CASE 567SD
3.60 V, proportional to an analog input voltage V
ranging from
CON
0.16 V to 1.44 V, optimizing power−added efficiency. Fast transition
times of less than 6 ms are achieved, allowing excellent inter−slot
settling.
An integrated LDO is automatically enabled under heavy load
conditions or when the battery voltage and voltage drop across the
DC−DC PMOS device are within a set range of the desired output
voltage. This LDO−assist feature supports heavy load currents under
the most stringent battery and V
conditions while maintaining
SWR
high efficiency, low dropout, and superior spectral performance.
The FAN5909 DC−DC operates in PWM Mode with a
2.9 MHz switching frequency and supports a single, small
form−factor inductor ranging from 1.0 mH to 2.2 mH. In
addition, PFM operation is allowed at low load currents for
output voltages below 1.5 V to maximize efficiency. PFM
operation can be disabled by setting MODE pin to LOW.
When output regulation is not required, the FAN5909 may
• Input Under−Voltage Lockout / Thermal Shutdown
• 1.615 mm x 1.615 mm, 16−Bump, 0.4 mm Pitch
WLCSP
• 2.9 MHz PWM Mode
• 6 ms Output Voltage Step Response for early Tx
Power−Loop Settling with 14 mF Load Capacitance
• Sleep Mode for ~50 mA Standby Current Consumption
be placed in Sleep Mode by setting V
below 100 mV
CON
nominally. This ensures a very low I (<50 mA) while
• Forced PWM Mode
Q
enabling a fast return to output regulation.
♦ Up to 95% Efficient Synchronous Operation in High
Power Conditions
FAN5909 is available in a low profile, small form factor,
16 bump, Wafer−Level Chip−Scale Package (WLCSP) that
is 1.615 mm x 1.615 mm. Only three external components
are required: two 0402 capacitors and one 2016 inductor.
♦ 2.9 MHz PWM−Only Mode
• Auto PFM/PWM Mode
♦ 2.9 MHz PWM Operation at High Power and PFM
Operation at Low Power and Low Output Voltage
for Maximum Low Current Efficiency
Features
2
• Solution Size < 9.52 mm
• 2.7 V to 5.5 V Input Voltage Range
Applications
• Dynamic Supply Bias for Polar or Linear GSM / EDGE
PAs and 3 G/3.5 G and 4 G PAs
• V
Range from 0.40 V to 3.60 V (or V )
IN
OUT
• Single, Small Form−Factor Inductor
• 29 mW Integrated LDO
• 100% Duty Cycle for Low−Dropout Operation
• Dynamic Supply Bias for GSM / EDGE Quad Band
Amplifiers for Mobile Handsets and Data Cards
ORDERING INFORMATION
†
Part Number
Output Voltage
Temperature Range
Package
Packing
FAN5909UCX
0.4 V to PVIN
−40°C to +85°C
1.615 mm x 1.615 mm, 16−Bump 0.4 mm Pitch,
Wafer−Level Chip−Scale Package (WLCSP)
Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
November, 2017 − Rev. 2
FAN5909/D
FAN5909
Block Diagrams
0.4V to3.6V
up to2.5A for
VBAT >3.7V
Up to3A in
Bypass Mode
PVIN
PVIN
FB
VOUT
VOUT
m
10 F
220pF
m
H
1.0
VOUT
AVIN
V
IN
SW
.7V to
5.5V
2
FAN5909
SW
BPEN
PGND
4.7mF
6.8pF
4.7μF
4. 7μF
PGND
PGND
MODE
EN
From
External
DAC
AGND
VCON
Figure 1. Typical Application
1. The three 4.7 mF capacitors include the FAN5909 output capacitor and PA bypass capacitors.
2. Regulator requires only one 4.7 mF; the V
bus should not exceed 14 mF capacitance over DC bias and temperature.
OUT
PVIN
VOUT
LDO
FB
Assist
AVIN
Positive
Current Limit
AGND
PFM/PWM
Controller
VCON
SW
3MHz
Oscillator
BPEN
MODE
EN
to PWM
Controller
Negative
Current Limit
PGND
Figure 2. Simplified Block Diagram
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FAN5909
Pin Configuration
PGND
A1
SW
A2
PVIN VOUT
VOUT PVIN
SW
A2
PGND
A1
A3
A4
A4
A3
B1
B2
B3
B4
B4
B3
B2
B1
AGND
C1
EN
C2
BPEN PGND
PGND BPEN
EN
C2
AGND
C1
C3
C4
C4
C3
AVIN VCON MODE
D1 D2 D3
FB
D4
FB
D4
MODE VCON AVIN
D3 D2 D1
Figure 3. Bumps Face Down – Top−Through View
Figure 4. Bumps Face Up
PIN DEFINITIONS
Pin #
Name
AGND
VOUT
Description
Analog ground, reference ground for the IC. Follow PCB routing notes for connecting this pin.
C1
A4, B4
Output voltage sense pin. Connect to V to establish feedback path for regulation point. Connect
OUT
together on PCB.
D4
C2
D2
D1
C3
D3
FB
Feedback pin. Connect to positive (+) pad of C
on V
OUT OUT.
EN
Enables switching when HIGH; Shutdown Mode when LOW. This pin should not be left floating.
Analog control pin. Shield signal routing against noise.
VCON
AVIN
BPEN
MODE
Analog supply voltage input. Connect to PVIN.
Force Bypass Mode when HIGH; Auto Bypass Mode when LOW. This pin should not be left floating.
When MODE is HIGH, the DC−DC permits PFM operation under low load currents and PWM operation
under heavy load currents. When MODE pin is set LOW, the DC−DC operates in forced PWM opera-
tion. This pin should not be left floating.
A3, B3
A2, B2
PVIN
SW
Supply voltage input to the internal MOSFET switches. Connect to input power source.
Switching node of the internal MOSFET switches. Connect to output inductor.
A1, B1,C4
PGND
Power ground of the internal MOSFET switches. Follow routing notes for connections between PGND
and AGND.
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FAN5909
Table 1. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−0.3
−40
−65
Max
Unit
V
Voltage on AVIN, PVIN
Voltage on Any Other Pin
Junction Temperature
Storage Temperature
6.0
V
IN
AV + 0.3
IN
T
+125
+150
+260
°C
°C
°C
kV
J
T
STG
T
Lead Soldering Temperature (10 Seconds)
Electrostatic Discharge Protection Level
L
ESD
Human Body Model, JESD22−A114
Charged Device Model, JESD22−C101
2.0
1.0
LU
Latch Up
JESD 78D
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 2. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.7
Typ
Max
Unit
V
V
IN
Supply Voltage Range
Output Voltage Range
5.5
V
0.35
<V
IN
V
OUT
OUT_BYPASS
I
Output Current in Bypass Mode (100% Duty Cycle)
Output Current
4.5
A
I
3.0
A
OUT
L
Inductor
1
mH
mF
mF
°C
°C
C
Input Capacitor (Note 3)
10
4.7
IN
C
Output Capacitor (Note 4)
OUT
T
A
Operating Ambient Temperature Range
Operating Junction Temperature Range
−40
−40
+85
T
J
+125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. The input capacitor must be large enough to limit the input voltage drop during GSM bursts, bypass transitions, and large output voltage
transitions.
4. Regulator requires only one 4.7 mF; the V
bus should not exceed 14 mF capacitance over DC bias and temperature.
OUT
Table 3. DISSIPATION RATINGS
Symbol
Parameter
Min
Typ
Max
Unit
q
Junction−to−Ambient Thermal Resistance (Note 5)
40
°C/W
JA
5. Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p boards
with vias in accordance to JESD51− JEDEC standard. Special attention must be paid not to exceed junction temperature T at a given
J(MAX)
ambient temperature T .
A
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FAN5909
Table 4. ELECTRICAL CHARACTERISTICS, ALL MODES Recommended operating conditions, unless otherwise noted, circuit
per Figure 1, V = 2.7 V to 5.5 V, T = −40°C to +85°C. Typical values are given V = 3.8 V at T = 25°C. L = 1 mH, Toko DFE201610C,
IN
A
IN
A
C
= 10 mF 0402 TDK C1005X5R0J106MT, C
= 3 x 4.7 mF 0402 TDK C1005X5R0J475KT.
IN
OUT
Symbol
POWER SUPPLIES
Parameter
Condition
Min
2.7
Typ
Max
Unit
V
IN
Input Voltage Range
I
≤ 2.5 A
5.5
3.0
V
mA
V
OUT
I
Shutdown Supply Current
EN = 0 V, MODE = 0
Rising
0.5
2.45
250
SD
V
UVLO
Under Voltage Lockout Threshold
V
2.20
2.60
IN
Hysteresis
mV
LOGIC CONTROL
V
Logic Threshold Voltage;
EN, BPEN, MODE
Input HIGH Threshold
Input LOW Threshold
1.2
1.6
V
V
IH
V
0.4
IL
CTRL
I
Logic Control Input Bias Current;
EN, BPEN, MODE
V
IN
or GND
0.01
1.00
mA
ANALOG CONTROL
V
V
V
V
V
V
Forced Bypass Enter (Note 6)
Forced Bypass Enter (Note 6)
Forced Bypass Exit
V
V
Voltage that Forces Bypass;
= 4.0 V – 4.75 V
V
V
CON_LDO_EN1
CON
CON
CON
CON
IN
V
V
V
Voltage that Forces Bypass;
V /2.5
IN
CON_LDO_EN2
CON
IN
≈ V
OUT
V
V
CON
Voltage that Exits Forced By-
1.4
V
CON_LDO_EX
pass; V = 2.70 V – 4.75 V
IN
V
V
Sleep Enter
Sleep Exit
V
CON
Voltage Forcing Low I Sleep
70
mV
con_SL_en
con
Q
Mode
V
CON
V
CON
Voltage that Exits SLEEP Mode
< 70 mV
125
80
mV
con_SL_ex
con
I
Q
DC−DC Quiescent Current in Sleep Mode
Gain in Control Range 0.16 V to 1.44 V
50
mA
Gain
2.5
V
V
OUT
Accuracy
Ideal = 2.5 x V
CON
−50
+50
mV
OUT_ACC
LDO
R
LDO FET Resistance
LDO Dropout (Note 7)
29
mW
FET
ΔV
I
= 2.0 A
100
mV
OUT_LDO
OUT
OVER TEMPERATURE PROTECTION
T
OTP
Over−Temperature Protection
Rising Temperature
Hysteresis
+150
+20
°C
°C
OSCILLATOR
f
Average Oscillator Frequency
2.6
2.9
3.2
MHz
SW
DC−DC
R
PMOS On Resistance
V
V
= V = 3.7 V
80
60
mW
DSON
IN
GS
NMOS On Resistance
= V = 3.7 V
GS
IN
I
I
P−Channel Current Limit (Note 8)
N−Channel Current Limit (Note 8)
Maximum Transient Discharge Current
LDO Current Limit
1.50
1.50
1.90
1.90
3.7
2.30
2.30
4.5
A
A
A
A
LIMp
LIMn
I
Discharge
I
4.5
LIMLDO
6. Input voltages nominally exceeding the lesser of VIN/2.5 or 1.6 V force 100% duty cycle.
7. Dropout depends on LDO and DC−DC PFET R and inductor DCR.
DSON
8. The current limit is the peak (maximum) current.
9. Guaranteed by design. Maximum values are based on simulation results with 50% COUT derating; not tested in production. Voltage tran-
sient only. Assumes C = 3 x 4.7 mF (1x4.7 mF for regulator and 2x4.7 mF for PA decoupling capacitors).
OUT
10.Protects part under short−circuit conditions
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FAN5909
Table 4. ELECTRICAL CHARACTERISTICS, ALL MODES Recommended operating conditions, unless otherwise noted, circuit
per Figure 1, V = 2.7 V to 5.5 V, T = −40°C to +85°C. Typical values are given V = 3.8 V at T = 25°C. L = 1 mH, Toko DFE201610C,
IN
A
IN
A
C
= 10 mF 0402 TDK C1005X5R0J106MT, C
= 3 x 4.7 mF 0402 TDK C1005X5R0J475KT.
IN
OUT
Symbol
DC−DC
Parameter
Condition
Min
Typ
Max
Unit
V
Minimum Output Voltage
Maximum Output Voltage
V
V
= 0.16 V
0.35
3.55
0.40
3.60
0.45
3.65
V
V
OUT_MIN
OUT_MAX
CON
V
= 1.44 V, V = 3.9 V
IN
CON
DC−DC EFFICIENCY
Power Efficiency, Low−Power Auto Mode,
η
Power
V
OUT
V
OUT
V
OUT
= 3.1 V, I
= 1.8 V, I
= 0.5 V, I
= 250 mA
95
90
65
%
LOAD
LOAD
LOAD
V
IN
= 3.7 V
= 250 mA
= 10 mA
OUTPUT REGULATION
V
V
V
OUT
V
OUT
V
OUT
Line Regulation
Load Regulation
Ripple
3.1 ≤ V ≤ 3.7
5
25
11
mV
mV
mV
OUT_RLine
IN
20 mA ≤ I
≤ 800 mA
OUT_RLoad
OUT
V
PFM Mode, V = 3.7 V,
IN
OUT_Ripple
I
< 100 mA
OUT
PWM Mode, V = 3.7 V
4
IN
TIMING
t
Startup Time (Note 9)
V
C
= 3.7 V, V from 0 V to 3.1 V,
OUT
50
60
ms
ms
SS
IN
= 3 x 4.7 mF, 10 V, X5R
OUT
t
V
Step Response Rise Time (Note 9)
From V
2.7 V (0.7 V – 3.4 V), R
C
to 95% V
, DV ≤
OUT
LOAD
6.0
7.3
DC−DC_TR
CON
CON
CON
OUT
= 5 W,
= 14 mF
OUT
t
V
Step Response Fall Time (Note 9)
From V
to 5% V , DV
OUT OUT
6.8
7.6
ms
DC−DC_TF
CON
2.7 V (3.4 V – 0.7 V), R
= 200 W,
LOAD
C
= 14 mF
OUT
t
Maximum Allowed Time for Consecutive
Current Limit (Note 10)
V
OUT
< 1 V
1500
4800
ms
ms
DC−DC_CL
t
Consecutive Current Limit Recovery Time
(Note 10)
DCDC_CLR
6. Input voltages nominally exceeding the lesser of VIN/2.5 or 1.6 V force 100% duty cycle.
7. Dropout depends on LDO and DC−DC PFET R and inductor DCR.
DSON
8. The current limit is the peak (maximum) current.
9. Guaranteed by design. Maximum values are based on simulation results with 50% COUT derating; not tested in production. Voltage tran-
sient only. Assumes C = 3 x 4.7 mF (1x4.7 mF for regulator and 2x4.7 mF for PA decoupling capacitors).
OUT
10.Protects part under short−circuit conditions
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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FAN5909
Typical Characteristics
Unless otherwise noted, V = EN = 3.7 V, L = 1.0 mH, C = 10 mF, C
= 3 x 4.7 mF, and T = +25°C.
A
IN
IN
OUT
100
100
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
VOUT = 1.6V
VOUT = 2.0V
VOUT = 2.5V
VOUT = 3.0V
VOUT = 3.5V
VOUT = 0.5V
VOUT = 1.0V
VOUT = 1.5V
VOUT = 2.0V
VOUT = 2.5V
VOUT = 3.0V
0
20
40
60
80
100
120
140
160
0ꢀꢀꢀꢁ100ꢀꢀꢀ200ꢀꢀꢀ300ꢀꢀꢀ400ꢀꢀꢀ500ꢀꢀꢀ600ꢀꢀꢀ700ꢀꢀꢀ800
Load Current (mA)
Load Current (mA)
Figure 5. Efficiency vs. Load Current and Output
Voltage, VIN = 3.8 V , IOUT = 10 mA to 150 mA
Figure 6. Efficiency vs. Load Current and Output
Voltage, VIN = 3.8 V
100
100
95
90
80
70
60
50
40
30
20
90
85
VOUT = 1.6V
VOUT = 2.0V
80
VOUT = 2.0V
VOUT = 2.5V
VOUT = 3.0V
VOUT = 3.5V
VOUT = 2.5V
VOUT = 3.0V
75
VOUT = 3.5V
70
0
200
400
600
800
1000
900
1200
1500
1800
2100
2400
2700
Load Current (mA)
Load Current (mA)
Figure 7. Efficiency vs. Load Current and Output
Voltage, VIN = 3.8 V, IOUT = 100 mA to 1 A
Figure 8. Efficiency vs. Load Current and Output
Voltage, VIN = 3.8 V, IOUT = 1 A to 2.5 A
3.6
3.4
3.2
3
4.5
4
3.5
3
2.5
2
2.8
2.6
1.5
1
0.5
0
2.4
2.5ꢀꢀꢀꢀ3ꢀꢀꢀꢀ3.5ꢀꢀꢀꢀ4ꢀꢀꢀꢀ4.5ꢀꢀꢀꢀ5ꢀꢀꢀꢀ5.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VCON (V)
Input Voltage (V)
Figure 9. Output Voltage vs. Supply Voltage,
OUT = 3.4 V, IOUT = 1.5 A, VIN = 4.3 V to Dropout
Figure 10. Output Voltage vs. VCON Voltage,
VIN = 4.2 V, RLOAD = 6.8 W, 0.1 V < VCON < 1.6 V
V
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FAN5909
Typical Characteristics
Unless otherwise noted, V = EN = 3.7 V, L = 1.0 mH, C = 10 mF, C
= 3 x 4.7 mF, and T = +25°C.
A
IN
IN
OUT
850
800
750
700
650
600
550
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
-40°C
+25°C
+85°C
2.5ꢀꢀꢀ3ꢀꢀꢀ3.5ꢀꢀꢀ4ꢀꢀꢀ4.5ꢀꢀꢀ5ꢀꢀꢀ5.5ꢀꢀꢀ6
3ꢀꢀꢀꢀꢁ3.5ꢀꢀꢀꢀꢁ4ꢀꢀꢀꢀꢁ4.5ꢀꢀꢀꢀꢁ5ꢀꢀꢀꢀꢁ5.5
Input Voltage (V)
Input Voltage (V)
Figure 11. Center−Switching Frequency vs. Supply
Voltage, VOUT = 2.5 V, IOUT = 700 mA
Figure 12. Quiescent Current (PFM) vs. Supply
Voltage, VOUT = 1 V, 2.7 V < VIN < 5.5 V (No Load)
20
18
16
14
12
10
8
VOUT
2V/DIV
2V/DIV
VCON
-40°C
6
+25°C
+85°C
4
IOUT
2
0
500mA/DIV
2.5
3
3.5
4
4.5
5
5.5
6
Input Voltage (V)
20ms/DIV
Figure 13. Quiescent Current (PWM) vs. Supply
Voltage, VOUT = 2.5 V, 2.7 V < VIN < 5.5 V (No Load)
Figure 14. VCON Transient (3 G/4 G), VOUT = 0 V to
3 V, RLOAD = 6.8 W, VIN = 3.8 V, 100 ns Edge
VOUT
VOUT
2V/DIV
1V/DIV
2V/DIV
2V/DIV
VCON
VCON
IOUT
IOUT
1A/DIV
500mA/DIV
20ms/DIV
20ms/DIV
Figure 15. VCON Transient (PFM to PWM), VOUT
=
Figure 16. VCON Transient (PWM), VOUT = 1.4 V to
1.4 V to 3.4 V, RLOAD = 6.8 W, VIN = 3.8 V, 100 ns Edge
3.4 V, RLOAD = 1.9 W, VIN = 4.2 V, 100 ns Edge
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FAN5909
Typical Characteristics
Unless otherwise noted, V = EN = 3.7 V, L = 1.0 mH, C = 10 mF, C
= 3 x 4.7 mF, and T = +25°C.
IN
IN
OUT
A
VOUT
VOUT
10mV/DIV
50mA/DIV
20mV/ DIV
IOUT
IOUT
200mA/DIV
20ms/DIV
100ms/DIV
Figure 17. Load Transient in PFM Mode, VIN = 3.6 V,
Figure 18. Load Transient in PWM Mode, VIN = 3.8 V,
VOUT = 1 V, IOUT = 0 mA to 60 mA, 1 ms Edge
VOUT = 2.5 V, IOUT = 0 mA to 300 mA, 10 ms Edge
VOUT
VOUT
50mV/DIV
100mV/DIV
IOUT
IOUT
500mA/DIV
500mA/DIV
100ms/DIV
100ms/DIV
Figure 20. Load Transient in PWM Mode, VIN = 4.2 V,
Figure 19. Load Transient in PWM Mode, VIN = 3.8 V,
OUT = 3.0 V, IOUT = 0 mA to 700 mA, 10 ms Edge
V
OUT = 3.0 V, IOUT = 0 mA to 1.2 A, 10 ms Edge
V
VOUT
VOUT
50mV/DIV
50mV/DIV
VIN
VIN
1V/DIV
1V/DIV
100ms/DIV
100ms/DIV
Figure 22. Line Transient, VIN = 3.6 V to 4.2 V,
OUT = 2.5 V, 6.8 W Load, 10 ms Edge
Figure 21. Line Transient, VIN = 3.6 V to 4.2 V,
OUT = 1.0 V, 6.8 W Load, 10 ms Edge
V
V
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FAN5909
Typical Characteristics
Unless otherwise noted, V = EN = 3.7 V, L = 1.0 mH, C = 10 mF, C
= 3 x 4.7 mF, and T = +25°C.
IN
IN
OUT
A
SW
SW
2V/DIV
2V/DIV
2V/DIV
1V/DIV
VOUT
VOUT
EN
2V/DIV
2V/DIV
EN
20ms/DIV
20ms/DIV
Figure 23. Startup in PFM Mode, VIN = 3.8 V,
OUT = 1.0 V, No Load, EN = Low to High
Figure 24. Startup in PWM Mode, VIN = 4.2 V,
OUT = 3.4 V, No Load, EN = Low to High
V
V
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FAN5909
Operating Description
In all cases, it is recommended that sharp V
CON
The FAN5909 is a high−efficiency, synchronous,
step−down converter (DC−DC) with LDO−assist function.
The DC−DC converter operates with current−mode
control and supports a wide range of load currents.
High−current applications up to a 2.5 A DC output, such as
mandated by GSM/EDGE applications, are allowed.
Performance degradation due to spurs is removed by
spreading the ripple energy through clock dither. A
regulated Bypass Mode continues to regulate the output to
transitions be applied, letting the transition controller
optimize the output voltage slew rate.
DVOUT Positive Step
After a V
positive step, the FAN5909 enters
CON
Current−Limit Mode, where V
ramps with a constant
OUT
slew rate dictated by the output capacitor and the current
limit.
DVOUT Negative Step
the desired voltage as V approaches V
. The LDO
OUT
IN
After a V
negative step, the FAN5909 enters Current
CON
offers a dropout voltage of approximately 100 mV under a
2 A load current.
Limit Mode where V
is reduced with a constant slew
OUT
rate dictated by the output capacitor and the current limit.
The output voltage V
input control voltage, V
is regulated to 2.5 times the
, set by an external DAC. The
OUT
VOUT Transition to or from Forced Bypass
CON
FAN5909 operates in either PWM or PFM Mode, depending
on the output voltage and load current.
The DC−DC is forced into 100% duty cycle for V
CON
nominally greater than 1.6 V. This allows the output to be
connected to the supply through both the low−resistance
DC−DC and the LDO PFETs.
In Pulse Width Modulation (PWM) Mode, regulation
begins with on−state. A P−channel transistor is turned on
and the inductor current is ramped up until the off−state
begins. In the off−state, the P−channel is switched off and an
N−channel transistor is turned on. The inductor current
decreases to maintain an average value equal to the DC load
current. The inductor current is continuously monitored. A
current sense flags when the P−channel transistor current
exceeds the current limit and the switcher is turned back to
off−state to decrease the inductor current and prevent
magnetic saturation. The current sense flags when the
N−channel transistor current exceeds the current limit and
redirects discharging current through the inductor back to
the battery.
VOUT Transition at Startup
At startup, after the EN rising edge is detected, the system
requires 25 ms for all internal voltage references and
amplifiers to start before enabling the DC−DC converter
function.
MODE Pin
The MODE pin enable Forced PWM Mode or Auto
PFM / PWM Mode. When the MODE pin is toggled HIGH
(logic 1), the FAN5909 operates in PFM for V
< 1.5 V
OUT
under light−load conditions and PWM for heavy−load
conditions. If the MODE pin is set LOW (logic = 0), it
operates in Forced PWM Mode.
In Pulse Frequency Modulation (PFM) Mode, the
FAN5909 operates in a constant on−time mode at low load
currents. During on−state, the P−channel is turned on for a
specified time before switching to off−state. In off−state, the
N−channel switch is enabled until inductor current
decreases to 0A. The switcher enters three−state until a new
regulation cycle starts.
PFM operation is allowed only in Low−Power Mode
(MODE=1) for output voltages nominally less than 1.5 V. At
low load currents, PFM achieves higher efficiency than
PWM. The trade−off for efficiency improvement, however,
is larger output ripple. Some applications, such as audio,
may not tolerate the higher ripple, especially at high output
voltages.
Auto PFM / PWM Mode (MODE = 1)
Auto PFM/PWM Mode is appropriate for 3 G/3.5 G and
4 G applications.
Forced PWM Mode (MODE = 0)
Forced PWM Mode is appropriate for applications that
demand minimal ripple over the entire output voltage range.
DC−DC – LDO−Assist
The LDO−assist function maintains output regulation
when V approaches V
, enables fast transition times
OUT
IN
under heavy loads, and minimizes PCB space by enabling a
smaller inductor to be employed by using the LDO to
provide a portion of the necessary load current.
Dynamic Output Voltage Transitions
FAN5909 has a complex voltage transition controller that
realizes 6 ms transition times with a large output capacitor
and output voltage ranges.
The LDO−assist function limits the maximum current that
the DC−DC may supply by shunting current away from the
DC−DC under heavy loads and high duty cycles. In addition,
the LDO−assist enables a seamless transition into 100%
duty cycle, ensuring both low output ripple and constant
output regulation. Since the LDO−assist function limits the
maximum current supplied by the DC−DC, PCB area is
minimized by enabling a lower current capable, and thus
smaller form factor, inductor to be used.
The transition controller manages five transitions:
• DV
• DV
• DV
• DV
positive step
OUT
OUT
OUT
OUT
negative step
transition to or from 100% duty cycle
transition at startup
www.onsemi.com
11
FAN5909
DC−DC – Sleep Mode
The Sleep Mode minimizing current while enabling rapid
return to regulation. Sleep Mode is entered when V is
CON
held below 70 mV for at least 40 ms. In this mode, current
consumption is reduced to under 50 mA. Sleep Mode is
exited after ~12 ms when V
is set above 125 mV.
CON
Application Information
Figure 26 illustrates the FAN5909 in a GSM / EDGE /
WCDMA transmitter configuration, driving multiple GSM
/ EDGE and 3 G/3.5 G and 4 G PAs. Figure 27 presents a
timing diagram designed to meet GSM specifications.
DC Output Voltage
The output voltage is determined by V
external DAC or voltage reference:
Figure 25. Output Voltage vs. Control Voltage
provided by an
CON
The FAN5909 is designed to support voltage transients of
6 ms when configured for GSM/EDGE applications
(MODE=0) and driving a load capacitance of approximately
14 mF. Figure 28 shows a timing diagram for WCDMA
applications.
VOUT + 2.5 VCON
The FAN5909 provides regulated V
(eq. 1)
only if V
CON
OUT
falls within the typical range from 0.16 V to 1.44 V. This
allows V to be adjusted between 0.4 V and 3.6 V. If
OUT
V
CON
is less than 0.16 V, V
is clamped to 0.40 V. In
OUT
Auto PFM/PWM Mode, the FAN5909 automatically
switches between PFM and PWM. In Forced PWM Mode
(MODE = 0), the FAN5909 automatically switches into
PWM Mode.
470nF
0201
m
4.7
F
0402
RFOUT
VRAMP
0.4V to3.5V
up to2.5A for
VBAT > 3.7V.
Up to3A in
GSM/EGSM
850/900MHz
PA
PA
LB_IN
Bypass Mode
FAN5909
FB
PCS/DCS
1800/1900MHz
PVIN
HB_IN
m
10
F
220pF
0201
GSM/EDGE
PAM
0402
LDO
Assist
V
IN
AVIN
VOUT
2.7V to5.5V
2.9MHz
Switcher
0.4V to3.4V
Up to
1mH
800mA
V
OUT
BPEN
SW
470nF
0201
PFM/PWM
Controller
m
F
0402
4.7
m
F
GPIO
GPIO
GPIO
4.7
0402
6.8pF
0201
MODE
EN
PGND
AGND
PA
…
UMTS BAND1, , 9
470nF
0201
Baseband
Processor
DAC
Reference
VCON
Bandgap
PA
…
UMTS BAND1, , 9
470nF
0201
μF capacitor can be replaced by a
*One 4.7
μF decoupling capacitor at the GSM PAs
4.7
.
PA
…
μF capacitors are optional
**220pF and6.8
UMTS BAND1, , 9
.
470nF
0201
PA
…
UMTS BAND1, , 9
Figure 26. Typical Application Diagram with GSM/EDGE/WCDMA Transmitters
www.onsemi.com
12
FAN5909
μs
50
_
DC−DC EN
MODE
−
DC DC
VCON
3.4V
2.5 x VCON
7.3μs
0.7V to 3.4V
0.7V
DC−DC VOUT
VRAMP
PA
PA_TX_EN
RF Packet
ANTENNA
Figure 27. Timing Diagram for GSM/EDGE Transmitters
50μs
_
DC−DC EN
MODE
DC−DC
VCON
3.4V
2.5 x VCON
7.3
μs
0.7V
DC−DC VOUT
_
_
PA TX EN
PA
Continuous RF
ANTENNA
Figure 28. Timing Diagram for WCDMA Transmitters
Inductor Selection
A 6.8 pF capacitor may be added in parallel with C
reduce the capacitor’s parasitic inductance.
to
OUT
The FAN5909 operates at 2.9 MHz switching frequency,
allowing 1.0 mH or 1.5 mH inductors to be used in designs.
For applications requiring the smallest possible PCB area,
use a 1.0 mH 2012 inductor or a 1.0 mH 2016 inductor for
optimum efficiency performance.
Table 6. RECOMMENDED CAPACITOR VALUES
Capacitor
Description
C
10 mF, 20%, X5R, 6.3 V, 0402
IN
(1005 metric) TDK C1005X5R0J106M
Table 5. RECOMMENDED INDUCTORS
C
4.7 mF, 20%, X5R, 6.3 V, 0402
(1005 metric) TDK C1005X5R0J475K
OUT
Inductor
Description
L
1.0 mH 20%, 2.1 A, 2012 Case Size
Cyntec: PSK20121T−1R0MS−63
PCB Layout and Component Placement
1.0 mH 20%, 2.2 A, 2016 Case Size
Toko: DFE201610R−H−1R0M
• The key point in the placement is the power ground
(PGND) connection shared between the FAN5909,
CIN, and COUT. This minimizes the parasitic
inductance of the switching loop paths.
Capacitor Selection
The minimum required output capacitor C
should be
OUT
• Place the inductor away from the feedback pins to
prevent unpredictable loop behavior.
one (1) 4.7 mF, 6.3 V, X5R with an ESR of 10 mW or lower
and an ESL of 0.3 nH or lower in parallel after inductor L1.
Larger case sizes result in increased loop parasitic
inductance and higher noise. One 4.7 mF capacitor should be
used as a decoupling capacitor at the GSM/EDGE PA V
pin and another 4.7 mF capacitor should be placed at V pin
• Ensure the traces are wide enough to handle the
maximum current value, especially in Bypass Mode.
• Ensure the vias are able to handle the current density.
Use filled vias if available.
CC
CC
of the 3 G/4 G PA.
www.onsemi.com
13
FAN5909
PACKAGE DIMENSIONS
WLCSP16 1.615x1.615x0.586
CASE 567SD
ISSUE O
PRODUCT SPECIFIC DIMENSIONS
D
E
X
Y
Unit
1.615 0.030
1.615 0.030
0.2075
0.2075
mm
www.onsemi.com
14
FAN5909
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