FAN54161UCX_技术文档

FAN54161

Battery Charging IC, 98%

Efficient, Safe 6ꢀA Direct

with Regulation and

Protection

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The FAN54161UCX is a low loss direct charger which charges the

battery safely at 6 A and provides active protection, regulation and

monitoring features.

Integrated Protection and Regulation features control a pair of

MOSFETs to ensure that the FAN54161UCX output voltage and

current stay within a safe programmed operating range. Configurable

hardware based safety features turn off the MOSFET in the event of a

fault and notify the system.

An integrated 10−bit Analog−to−Digital Converter (ADC) provides

real−time monitoring of input, output voltage, currents and

temperature so that the system host or microcontroller can effectively

use this information to optimize adapter and charger configuration.

WLCSP42

CASE 567TY

MARKING DIAGRAM

Features

• Integrated Back−to−Back Common Source N−channel MOSFETs

with Combined R = 11 mW

ON

1

2

K

Y

K

Z

• Maximum Input Voltage Tolerance of +22 V

X

• Reverse Input Voltage Tolerance of −2 V

• External N−channel MOSFET Drive Capability with Tolerance up to

+32 V

• Regulation Modes

♦ Charge Current

♦ Input Current

12 = Specific Device Code

KK = Lot Run Code

X = Year Code

♦ Output Voltage

♦ Battery Cell Voltage

Y = 2−Weeks Date Code

Z = Assembly Plant Code

• Hardware−based Safety Protections

♦ Input Over−Voltage

♦ Input Under−Voltage

♦ Output Over−Voltage

♦ Input Over−Current

♦ Die Over−Temperature

♦ Internal Switch Short

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

• 10−bit High−accuracy ADC

Typical Applications

• Mobile Devices

• Tablets

1

Publication Order Number:

July, 2018 − Rev.4

FAN54161/D

FAN54161

Block Diagram and Application Schematic

FAN54511A

/INT

SCL

SW

Power−Path

Switching

Charger

System

Load

SYS

SDA

Body

Control

VBUS

VBAT

FAULT PROTECTION

IBUS OCP

IBUS RCB

VBUS OVP

VBUS UVLO

VOUT OVP

VDROP OVP

IC Temp

Battery Temp

Watchdog Timer

REGULATION LOOPS

FAN54161

VOREG CV

VBATREG CV

IBATREG CC

IBUSREG CC

GATE DRIVER

CHARGE PUMP

OSCILLATOR

FDMC8321L

VBUS

VOUT

PMID

14

7

VBUS

C_OUT

C_BUS

R_{VBUS_PD}

VBUS OVP

VBUS UVLO

IBUSREG CC

IBUS OCP

OVP_C

VDROP OVP

VDROP Alarm

CHARGE PUMP

GATE DRIVER

VUSB OVP

VOREG CV

VOUT OVP

IBUS RCB

PACK+

Battery

Pack

VUSB UVLO

R_LIMIT

2.4V

VUSB

R_PU

PSNS+

INPUT

VSNSP

VSNSN

TS_BUS

THERMAL

+

PROTECTION

VBATREG CV

CONTROL

R_NTCBUS

FFG1040

PSNS−

2.4V

R_PU

INT_N

SCL

INT_N

VBAT

BATTERY

THERMAL

PROTECTION

Protection

9 Channel

10−Bit ADC

TS_BAT

I²C INTERFACE

LOGIC AND

CONTROL

SCL

System

Host

NTC

SDA

Fuel

RESET_N

ADR

PACK−

Gauge

SRP

SRN

SRP

R_SENSE

IBATREG CC

IC THERMAL

PROTECTION

AGND/SRN

GND

Figure 1. FAN54161, External FET, Switching Charger, Battery Pack with Exposed Cell, and External Fuel Gauge

RECOMMENDED COMPONENTS

Component

Manufacturer

Murata

TDK

Part Number

Value

1.0 mF

Case Size

Rating

25 V

6.3 V

1 W

C

GRM188R61E105K

C1608X5R1E105K

C1608X5R0J226M

MCS1632R010FER

MCS1632R005FER

0603 (1608 metric)

1206 (3216 metric)

BUS

C

(alternative)

1.0 mF

BUS

C

TDK

22 mF

OUT

R

Ohmite

0.01 ( 1%) Ohm

0.005 ( 1%) Ohm

SENSE

R

(alternative)

1 W

SENSE

ORDERING INFORMATION

Part Number

Temperature Range

−40°C to +85°C

Package

Packing Method

FAN54161UCX

2.78 x 3.06 mm, 42−Bump WLCSP

Tape and Reel

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2

FAN54161

Pin Connections and Functional Description

VBUS

VUSB

OVP_C

VOUT

PMID

A1

A2

A3

A4

A5

A6

VBUS

SCL

TS_BUS

VOUT

PMID

B1

B2

B3

B4

B5

B6

SDA

INT_N

VOUT

PMID

VBUS

C1

C2

C3

C4

C5

C6

TS_BAT RESET_N

VOUT

PMID

VBUS

D1

D2

D3

D4

D5

D6

ADR

VOUT

PMID

VBUS

SRN

E1

E2

E3

E4

E5

E6

SRP

GND

VOUT

PMID

VBUS

F6

F1

F2

F3

F4

F5

SNSN

SNSP

VOUT

PMID

VBUS

G1

G2

G3

G4

G5

G6

Figure 2. WLCSP−42 Pin Assignments

Table 1. PIN DESCRIPTIONS

Name

Position

Type

Description

2

ADR

E2

Digital Input I C Slave Device Address Selection Pin

Refer to I2C Interface section for details

ADR logic level must be set before releasing RESET_N high. Recommend connecting this

pin to the appropriate logic level before power is applied (VBUS or VOUT).

GND

F2

C2

Ground

Device Ground

Connect to the ground node in the PCB.

INT_N

Open−Drain Interrupt Output (Active Low)

Digital Output

Pull−up with 100 kW resistor to logic supply voltage. When an un−masked interrupt bit is

set this pin will assert low.

Connect to GND if not used.

RESET_N

D2

Digital Input Reset Input (Active Low)

0 (Logic Low) – IC held in reset condition (lowest power state), switch is open, ADC is

2

disabled, and I C communication is not available.

1 (Logic High) – IC logic allowed to operate, switch closed if SW_EN = 1; ADC enabled if

ADC_EN = 1.

If not used, it is recommended to pull−up to VOUT.

2

SCL

SDA

B1

C1

Digital Input I C Serial Clock Input

Pull−up with a resistor to logic supply voltage.

2

Open−drain I C Serial Data

Digital I/O

Pull−up with a resistor to logic supply voltage.

VBUS

A6, B6, C6, D6, Power Input Switch Input, Device Supply and Input Voltage Sense

E6, F6, G6

Connect to the input power source of system. If an external N−channel MOSFET is used

for protection, connect VBUS to the source of this MOSFET.

VBUS has an internal 100 W pulldown resistor that is active when VBUSPD_EN = 1.

PMID

A5, B5, C5, D5,

E5, F5, G5

Switch Common Source Point

Leave floating. Connect to a floating copper plane to provide an additional thermal relief

path to the PCB.

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3

FAN54161

Table 1. PIN DESCRIPTIONS

Name

Position

Type

Description

VOUT

A3, A4, B3, B4, Power Output Switch Output, Device Supply, and Output Voltage Sense

C3, C4, D3,

Connect to the battery pack.

VOUT will be regulated to a maximum level, relative to GND, as set by the VOREG(TH)

D4, E3, E4, F3,

F4, G3, G4

register value.

SNSN

SNSP

G1

Analog Input Battery Cell Voltage Sense Negative

Connect to the negative side of the cell inside the battery pack through a 1 kW resistor in

series. If the battery pack does not provide access to the negative side of the cell, connect

SNSN physically as close as possible to the negative terminal of the pack.

If the voltage sensed across SNSP and SNSN tries to exceed the threshold

V , the voltage across SNSP and SNSN is regulated to the threshold.

BATREG(TH)

G2

Analog Input Battery Cell Voltage Sense Positive

Connect to the positive side of the cell inside the battery pack through a 1 kW resistor in

series.

If the voltage sensed across SNSP and SNSN tries to exceed the threshold

V , the voltage across SNSP and SNSN is regulated to the threshold.

BATREG(TH)

If the battery pack does not provide access to the positive side of the cell, connect SNSP

to VOUT.

SRN

SRP

E1

F1

B2

D1

A1

Analog Input Battery Current Sense Negative

Connect to the negative side of the sense resistor in series with the cell.

If the current through R

tries to exceed the threshold I , the voltage across

BATREG(TH)

SENSE

SRN and SRP is regulated to the threshold.

Analog Input Battery Current Sense Positive

Connect to the positive side of the sense resistor in series with the cell.

If the current through R

tries to exceed the threshold I , the voltage across

BATREG(TH)

SENSE

SRN and SRP is regulated to the threshold.

TS_BUS

TS_BAT

VUSB

Analog Input Thermistor Input for input connector temperature sense

Connect an NTC thermistor from TS_BUS to GND. Connect a pull−up resistor from

TS_BUS to an external 2.4 V supply.

Connect to GND if not used.

Analog Input Thermistor Input for battery temperature sense

Connect an NTC thermistor from TS_BAT to GND. Connect a pull−up resistor from

TS_BAT to an external 2.4 V supply.

Connect to GND if not used.

Power Input Input Voltage Sense for external VBUS over voltage protection control

Connect this pin to the drain of external N−channel MOSFET (which is also the USB sup-

ply voltage) with a 500 W series resistor, R . The source of the external N−channel

LIMIT

MOSFET must be connected to the VBUS pin. If an external MOSFET is not used, the

VUSB pin must be left floating. Do not connect this pin to GND.

OVP_C

A2

Analog Output Gate Control Output for external VBUS OVP blocking FET

Connect to the gate of external N−channel MOSFET. If an external MOSFET is not used,

the OVP_C pin should be tied to VBUS or float. Do not connect this pin to GND.

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4

FAN54161

Table 2. ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)

Symbol Parameter

Min

−2.0

−0.3

−2.0

−0.3

Typ

Max

+22.0

+7.0

Units

V

BUS

V

OUT

V

USB

Protected Input Supply Voltage, VBUS to GND

Battery Voltage, VOUT to GND

V

Input connector sense pin, R

= 500 W

+32.0

+29.0

+6.0

LIMIT

V

OVP Gate Control Output, OVP_C = VBUS

OVP_C

V

, V

SRN

,

Battery Positive Voltage and Current Sense, SNSP to GND, SRP to GND, SRN

to GND

SNSP SRP

V

Battery Negative Voltage Sense, SNSN to GND

−4.6

−0.3

+6.0

V

SNSN

V

,

Thermistor Voltage Sense Inputs, TS_BUS to GND, TS_BAT to GND

TS_BUS

V

TS_BAT

V

Digital Input and Open Drain Output Pins (SCL, SDA, ADR, RESET_N, INT_N)

Maximum Continuous Switch Current

−0.3

+6.0

7.50

+85

V

A

IOD

I

PASS

T

Operating Free−air Temperature

−40

−65

°C

V

A

T

Maximum Junction Temperature

+150

260

J(MAX)

T

STG

Storage Temperature Range

T

Lead Soldering Temperature, 10 secs

L

ESD

Human−Body Model (HBM−JESD22−A114), VBUS and VUSB

Human−Body Model (HBM−JESD22−A114), All Other Pins

Charged Device Model (CDM−JESD22−C101), All Pins

3000

2000

500

V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. All voltages are referenced to ground, GND, unless otherwise noted.

2. Pins should be protected with external TVS devices when tested for IEC compliance.

Table 3. THERMAL CHARACTERISTICS

Symbol

Parameter

Conditions

Min

Typ

Max

Units

ThetaJA

Junction −to−Ambient Thermal Resistance

JEDEC, 2S2P, No Vias

50

°C/W

NOTES: Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with two−layer 2s2p

boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature T at a

J(max)

given ambient temperature T .

A

Table 4. RECOMMENDED OPERATING RANGES (Note 3)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions

are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or

designing to Absolute Maximum Ratings. The recommended operating conditions assume the following: V = 2.7 V to 4.5 V, V

=

PU

OUT

1.8 V to 4.5 V, T = −40°C to 85°C, unless otherwise noted.

A

Symbol

Parameter

Min

2.66

2.5

Typ

Max

6.4

Units

V

BUS

V

USB

V

OUT

Input Voltage

Input Connector Voltage Sense

Battery Voltage

15

V

2.66

−0.2

1.62

0.1

5.2

V

SNSP

V

SNSN

Battery Positive Voltage Sense

Battery Negative Voltage Sense

Battery Current Sense

5.2

V

+0.2

3.63

2.3

V

, V

SRP SRN

V

2

V

PU

I C External Pull−up Supply Voltage

V

, V

TS_BAT

Thermistor Input Voltage Sense

Operating Free−air temperature

Operating Junction Temperature

V

TS_BUS

T

A

−40

−30

+85

+120

°C

T

J

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

3. All voltages are measured relative to GND.

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5

FAN54161

Table 5. ELECTRICAL CHARACTERISTICS (Notes 4, 5, 6, 7) Unless otherwise specified: according to the circuit in Figure 1;

recommended operating range for T and T ; The Recommended Operating Conditions for DC Electrical Characteristics assume V =

OUT

J

A

2.7 V to 4.5 V and T = −40°C to 85°C, unless otherwise noted. Typical values are at T = 25°C, V

= 3.8 V, V = 1.8 V.

A

OUT

PU

Symbol

SUPPLY CURRENT

Parameter

Conditions

Min

Typ

Max Units

I

Active Mode Current

Switch Closed, RESET_N=HIGH,

=6A, V =0V, [ADC_EN]=0

5

9

mA

ACTIVE

I

PASS

USB

I

VOUT Standby Mode Current

RESET_N=HIGH, [ADC_EN]=0,

=Open

5.5

1.5

10

3.0

STANDBY_ADCOFF

V

BUS

RESET_N=HIGH, [ADC_EN]=0,

=5V

V

BUS

I

VOUT Shutdown Mode Current

VBUS Standby Mode Current

RESET_N=LOW, V

=5V

1.5

10

3.0

25

mA

SHUTDOWN

BUS

=Open

I

RESET_N=HIGH, [ADC_EN]=0,

=5V, V =3.8V

STANDBY_ADCOFF

V

BUS

OUT

RESET_N=HIGH, [ADC_EN]=0,

=5V, V =Open

10

25

mA

V

BUS

OUT

I

VBUS Shutdown Mode Current

VUSB Quiescent Current

RESET_N=LOW, V

=5V, V

=3.8V

3

18

mA

SHUTDOWN

BUS

OUT

=Open

OUT

I

V

USB

=5V

63

100

VUSB

SWITCH CHARACTERISTICS

R

On−Resistance from VBUS to

VOUT

3.0<=V

A

<=4.5V, I =1A,

OUT PASS

11

mW

ON

T = 25°C

R

VBUS Pulldown Resistance

[VBUSPD_EN] = 1

80

100

120

W

VBUS_PD

SWITCH DYNAMIC CHARACTERISTICS

t

Switch Turn_On Time

V

=5V, V =3.8V, [SW_EN]=0 to 1,

OUT

1.7

1.6

ms

ENABLE

BUS

[ADC_EN]=0, RESET_N=HIGH, [IBUS-

REG]=3.5A

V

BUS

=5V, V =3.8V, [SW_EN]=0 to 1,

OUT

[ADC_EN]=1, RESET_N=HIGH, [IBUS-

REG]=3.5A

t

Switch Turn_Off Time

[SW_EN] = 1 to 0

0.4

5.7

ms

DISABLE

t

Time to Isolate VBUS from VOUT

for VBUS OVP

V

BUS

Overdrive = 100 mV above

ms

OFF_BUSOVP

VBUSOVP(th)

t

Time to Isolate VBUS from VOUT VBUS Underdrive = 100 mV below

for VBUS UVLO VBUSUVLO(th)

5.7

ms

OFF_BUSUVLO

t

Time to Isolate VBUS from VOUT (V

−V ) Overdrive = 10 mV above

OFF_VDROPOVP

BUS

OUT

for VDROP OVP

VDROPOVP(TH)

Overdrive = 200 mA above I -

BU

t

Time to Isolate VBUS from VOUT

for IBUS Over Current Fault

I

425

OFF_IBUSOCP

PASS

, no Regulation Mode control

SOCP(TH)

(Note 9)

t

Time to Isolate VBUS from VOUT T > T

1.2

10

ms

OFF_TSHDN

J

SDN(TH)

for Die Over Temperature Fault

t

Time to Isolate VBUS from VOUT (V

− V

) Overdrive = 10 mV above

OFF_RCB

OUT

VRCB(TH)

BUS

for Reverse Current Fault

t

RESET_N Input Pulse Width Low

1200

WL_RESET

4. V

= V + 0.5 V or V

whichever is lower

IH(max)

PU

BAT

5. It is assumed that the SCL and SDA pins are open drain with external pull−ups resistors tied to an external supply V

.

PU

2

6. V and V have been chosen to be fully compliant to I C specification at V = 1.8 V 10%. At 2.25V v V v 3.63 V the V

provides

IH

IL

PU

IL(max)

> 200 mV on noise margin to the required V

of the transmitter.

OL(max)

2

7. I C standard specifies V

for V v 2.0 V to be 0.2 x V

.

OL(max)

PU

8. Guaranteed by design. Not tested in production.

9. Regulation Mode control will reduce t

.

OFF_IBUSOCP

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6

FAN54161

Table 5. ELECTRICAL CHARACTERISTICS (Notes 4, 5, 6, 7) Unless otherwise specified: according to the circuit in Figure 1;

recommended operating range for T and T ; The Recommended Operating Conditions for DC Electrical Characteristics assume V =

OUT

J

A

2.7 V to 4.5 V and T = −40°C to 85°C, unless otherwise noted. Typical values are at T = 25°C, V

= 3.8 V, V = 1.8 V.

A

OUT

PU

Symbol

Parameter

Conditions

Min

Typ

Max Units

SWITCH DYNAMIC CHARACTERISTICS

2

t

2

RESET_N Release to I C Delay

Time

Duration required between rising edge of

RESET_N and first I2C START (Note 8)

120

ms

RL_RESETI C

HARDWARE PROTECTION (Bypass Switch)

V

VBUS OVP Threshold Range

VBUS OVP Threshold Stepsize

VBUS OVP Threshold Accuracy

VBUS OVP Deglitch Time

4.2

6.4

6.5

6.6

V

mV

V

BUSOVP(TH)

25

6.5

4

[VBUSOVP_TH] = 6.5 V

[OVP_DLY]=0

t

ms

V

BUSOVPGLTCH

[OVP_DLY]=1

20

2.9

V

VBUS UVLO Threshold

V

> V

allows the switch to

2.84

2.96

BUSUVLO(TH)

BUS

BUSUVLO(TH)

close

V

VBUS UVLO Hysteresis

Falling

300

4

mV

ms

BUSUVLO(HYS)

t

VBUS UVLO Deglitch Time

VDROP OVP Threshold Range

VDROP OVP Threshold Stepsize

BUSUVLOGLTCH

V

BUS

V

BUS

V

BUS

− V

0

1000

305

mV

DROPOVP(TH)

OUT

5

OUT

VDROP OVP Threshold

Accuracy

, 2.66V < V

OUT

< 4.5 V,

295

300

OUT

[VDROPOVP_TH]=300mV

t

VDROP OVP Deglitch Time

[OVP_DLY]=0

4

ms

VDROPGLTCH

[OVP_DLY]=1

20

V

VDROP Alarm Threshold Range

V

− V

0

1000

115

mV

DROPALM(TH)

BUS

OUT

VDROP Alarm Threshold

Stepsize

5

VDROP Alarm Threshold

Accuracy

V

BUS

− V

, 2.66 V < V < 4.5 V,

OUT

80

100

mV

OUT

[VDROPOVP_TH]=100mV

t

VDROP Alarm Deglitch Time

[OVP_DLY]=0

4

ms

A

VDROPALMGLTCH

[OVP_DLY]=1

20

I

IBUS OCP Threshold Range

IBUS OCP Threshold Stepsize

IBUS OCP Threshold Accuracy

IBUS OCP Deglitch Time

0.5

7.5

BUSOCP(TH)

500

5.00

50

mA

A

2.66V < V

< 4.5V, [IBUSOCP_TH]=5A

4.75

5.25

OUT

t

[IBUSOCP_MODE]=0

ms

IBUSOCPGLTCH

[IBUSOCP_MODE]=1; Deglitch time

before entering Hiccup Mode

8

t

IBUS OCP Hiccup Mode Retry

Time

[IBUSOCP_MODE]=1

80

−100

2.6

100

3

125

+300

3.3

ms

mA

A

HICCUP

I

RCB Threshold

[IRCB]=0, Current from V

to V

,

RCB(TH)

OUT

BUS

V

BUS

≥ 3 V

[IRCB]=1, Current from V

≥ 3 V

OUT

BUS

V

BUS

t

RCB Deglitch Time

8

ms

RCBGLTCH

4. V

= V + 0.5 V or V

whichever is lower

IH(max)

PU

BAT

5. It is assumed that the SCL and SDA pins are open drain with external pull−ups resistors tied to an external supply V

.

PU

2

6. V and V have been chosen to be fully compliant to I C specification at V = 1.8 V 10%. At 2.25V v V v 3.63 V the V

provides

IH

IL

PU

IL(max)

> 200 mV on noise margin to the required V

of the transmitter.

OL(max)

2

7. I C standard specifies V

for V v 2.0 V to be 0.2 x V

.

OL(max)

PU

8. Guaranteed by design. Not tested in production.

9. Regulation Mode control will reduce t

.

OFF_IBUSOCP

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7

FAN54161

Table 5. ELECTRICAL CHARACTERISTICS (Notes 4, 5, 6, 7) Unless otherwise specified: according to the circuit in Figure 1;

recommended operating range for T and T ; The Recommended Operating Conditions for DC Electrical Characteristics assume V =

OUT

J

A

2.7 V to 4.5 V and T = −40°C to 85°C, unless otherwise noted. Typical values are at T = 25°C, V

= 3.8 V, V = 1.8 V.

A

OUT

PU

Symbol

Parameter

Conditions

Min

Typ

Max Units

HARDWARE PROTECTION (Bypass Switch)

T

Thermal Shutdown Threshold

Range

115

145

°C

SDN(TH)

Thermal Shutdown Threshold

Stepsize

10

Thermal Shutdown Threshold

Thermal Shutdown Deglitch Time

VFAIL Short Detect Threshold

3.0V < V

< 5.9V, [TJSHDN]=125°C

125

800

2

°C

ms

V

BUS

t

TSDGLTCH

V

FAIL

Active only when SW_EN=0, ADC_EN=1

Active only when SW_EN=0

1.9

2.2

R

VFAIL

VFAIL Pulldown Resistor (PMID

to GND)

23

kW

t

VFAIL Deglitch Time

VBAT Insert Voltage

4

ms

VFAIL_GLTCH

V

> V ; V rising

BUSUVLO(TH) SNSP

BATINSERT(TH)

2.0

V

BATINSERT(TH)

BUS

above V

indicates a con-

nected battery.

V

VBAT Insert Hysteresis

VOUT OVP Threshold Range

VOUT OVP Threshold

Falling

100

mV

V

BATINSERT(HYS)

V

4.5

5.3

OUTOVP(TH)

[VOUTOVP_TH]=4.7V

Falling

4.55

4.7

100

4

4.85

V

VOUT OVP Hysteresis

VOUT OVP Deglitch Time

mV

ms

OUTOVP(HYS)

t

[VOUTOVP_DLY]=0

[VOUTOVP_DLY]=1

VOUTOVPGLTCH

20

ms

VOUT VOLTAGE REGULATION

V

VOREG Regulation Threshold

Range

4.2

5

V

OREG(TH)

VOREG Regulation Threshold

Stepsize

10

mV

VOREG Regulation Threshold

Accuracy

[VOREG]=4.4V, T = 25°C

−10

+10

5

J

VBAT VOLTAGE REGULATION

V

VBATREG Regulation Threshold

Range

V

− V

4.2

V

BATREG(TH)

SNSP

SNSN

VBATREG Regulation Threshold

Stepsize

10

mV

SNSP

SNSN

VBATREG Regulation Threshold [VBATREG]=4.3V, T = 25°C

Accuracy

−10

+10

J

4. V

= V + 0.5 V or V

whichever is lower

IH(max)

PU

BAT

5. It is assumed that the SCL and SDA pins are open drain with external pull−ups resistors tied to an external supply V

.

PU

2

6. V and V have been chosen to be fully compliant to I C specification at V = 1.8 V 10%. At 2.25V v V v 3.63 V the V

provides

IH

IL

PU

IL(max)

> 200 mV on noise margin to the required V

of the transmitter.

OL(max)

2

7. I C standard specifies V

for V v 2.0 V to be 0.2 x V

.

OL(max)

PU

8. Guaranteed by design. Not tested in production.

9. Regulation Mode control will reduce t

.

OFF_IBUSOCP

www.onsemi.com

8

FAN54161

Table 5. ELECTRICAL CHARACTERISTICS (Notes 4, 5, 6, 7) Unless otherwise specified: according to the circuit in Figure 1;

recommended operating range for T and T ; The Recommended Operating Conditions for DC Electrical Characteristics assume V =

OUT

J

A

2.7 V to 4.5 V and T = −40°C to 85°C, unless otherwise noted. Typical values are at T = 25°C, V

= 3.8 V, V = 1.8 V.

A

OUT

PU

Symbol

Parameter

Conditions

Min

Typ

Max Units

IBAT CURRENT REGULATION

I

IBATREG Regulation Threshold

Range

V

− V

sensed across R

.

0.1

6.35

A

mA

%

BATREG(TH)

SRP

SRN

SENSE

IBATREG Regulation Threshold

Stepsize

50

IBATREG Regulation Threshold

Accuracy

2.5V < V

R

< 4.5V,

−5

+5

OUT

=10mW, [IBATREG]=2A

SENSE

2.5V < V

R

< 4.5V,

%

OUT

=5mW, [IBATREG]=4A

SENSE

IBUS CURRENT REGULATION

I

IBUSREG Regulation Threshold

Range

0.1

6.5

+5

A

mA

%

BUSREG(TH)

IBUSREG Regulation Threshold

Stepsize

50

IBUSREG Regulation Threshold 2.66 < V

Accuracy

< 4.5; [IBUSREG] = 3.5 A

−5

OUT

BATTERY CELL VOLTAGE SENSE INPUTS (VSNSP, VSNSN)

I

SNSP Input Current

SNSN Input Current

2.66 V < V

< 4.5 V

5

1

mA

SNSP

SNSN

SNSP

I

0.0 V < V

< 0.2 V

SNSN

LOGIC LEVELS (SCL, SDA, ADR, INT_N, RESET_N)

V

Input High Voltage Level

Input Low Voltage Level

1.05

−10

−1

V

IH

V

0.4

IL

V

Output Low Voltage, INT_N, SDA

Input current each I/O pin

I

= 3 mA

V

OL

IN

OL

I

V

= 0 V or 5 V

+10

mA

BATTERY CURRENT SENSE INPUTS (VSRP, VSRN)

I

V

SRP

V

SRN

Input Current

0 < V < 0.2

SRP

1

mA

SRP

SRN

I

−0.2 < V

< 0

SRN

WATCH DOG TIMER

t

Watchdog Timer Range

0.5

2

s

WDT

Watchdog Timer Accuracy

All [WDT] Settings

(Note 8)

−10

+10

%

ANALOG TO DIGITAL CONVERTER

RES

INL

DNL

OE

Resolution

10

Bits

LSB

MHz

Integral Non−Linearity

Differential Non−Linearity

Offset Error

1

GE

Gain Error (Full Scale Error)

Conversion Clock

1

f

2.7

3.0

3.3

CONV

4. V

= V + 0.5 V or V

whichever is lower

IH(max)

PU

BAT

5. It is assumed that the SCL and SDA pins are open drain with external pull−ups resistors tied to an external supply V

.

PU

2

6. V and V have been chosen to be fully compliant to I C specification at V = 1.8 V 10%. At 2.25V v V v 3.63 V the V

provides

IH

IL

PU

IL(max)

> 200 mV on noise margin to the required V

of the transmitter.

OL(max)

2

7. I C standard specifies V

for V v 2.0 V to be 0.2 x V

.

OL(max)

PU

8. Guaranteed by design. Not tested in production.

9. Regulation Mode control will reduce t

.

OFF_IBUSOCP

www.onsemi.com

9

FAN54161

Table 5. ELECTRICAL CHARACTERISTICS (Notes 4, 5, 6, 7) Unless otherwise specified: according to the circuit in Figure 1;

recommended operating range for T and T ; The Recommended Operating Conditions for DC Electrical Characteristics assume V =

OUT

J

A

2.7 V to 4.5 V and T = −40°C to 85°C, unless otherwise noted. Typical values are at T = 25°C, V

= 3.8 V, V = 1.8 V.

A

OUT

PU

Symbol

Parameter

Conditions

Min

Typ

Max Units

ANALOG TO DIGITAL CONVERTER

t

Throughput time (Single−shot

conversion)

No Averaging, 1 channel, One−shot con-

version (ADC_RATE = 0, ADC_EN written

from 0 to 1)

47

ms

THR_ONE

8−sample Averaging (AVG_EN=1, SAM-

PLES=0), 1 channel, One−shot conver-

sion (ADC_RATE = 0, ADC_EN written

from 0 to 1)

84

ms

16−sample Averaging (AVG_EN=1, SAM-

PLES=1), 1 channel, One−shot conver-

sion (ADC_RATE = 0, ADC_EN written

from 0 to 1)

127

16−sample Averaging (AVG_EN=1, SAM-

PLES=1), 9 channels, One−shot conver-

sion (ADC_RATE = 0, ADC_EN written

from 0 to 1)

1031

t

Throughput time (Continuous

Conversion)

No Averaging, 1 channel, Continuous

33

70

ms

THR_CONT

conversion (ADC_RATE = 1, ADC_EN=1)

8−sample Averaging (AVG_EN=1, SAM-

PLES=0), 1 channel, Continuous conver-

sion (ADC_RATE = 1, ADC_EN=1)

16−sample Averaging (AVG_EN=1, SAM-

PLES=1), 1 channel, Continuous conver-

sion (ADC_RATE = 1, ADC_EN=1)

113

ms

16−sample Averaging (AVG_EN=1, SAM-

PLES=1), 9 channels, Continuous con-

version (ADC_RATE = 1, ADC_EN=1)

1018

GAIN

Battery Current ADC Gain Range RSENSE = 0

RSENSE = 1

40

20

V/V

IBAT

VBUS

VBUS Channel Full Scale Range Signal sensed at VBUS pin, 7.3 mV per

LSB

0

6.1

5.0

V

ADC

VBAT

VBAT Channel Full Scale Range Signal sensed across and SNSP and

SNSN pins, 5.3 mV per LSB

2.5

V

ADC

VOUT

VOUT Channel Full Scale Range Signal sensed at VOUT, 5.3 mV per LSB

0

5.0

1.0

V

ADC

VDROP

VDROP Channel Full Scale

Range

Signal sensed between VBUS and VOUT

pins, 2.9 mV per LSB

ADC

IBUS

IBUS Channel Full Scale Range

Signal sensed across internal switch,

14.6 mA per LSB

0

−7.0

0

7.0

+7.0

2.4

A

V

s

ADC

IBAT

IBAT Channel Full Scale Range

Signal sensed across SRP and SRN pins,

14.6 mA per LSB

ADC

TBUS_BAT

TBUS and TBAT Channel Full

Scale Range

Signal sensed at TS_BUS and TS_BAT

pins, 2.9 mV per LSB respectively

ADC

t

TBUS and TBAT Temperature

Fault Deglitch Time

Deglitch time to open switch when

0.9

1

1.1

TBUS_TBAT_GLTCH

V

TBUS

V

TBAT

falls below TBUS_TH or

falls below TBAT_TH

TDIE

TDIE Channel Full Scale Range

Signal sensed by internal temperature

sensor, 1°C per LSB

25

150

°C

ADC

4. V

= V + 0.5 V or V

whichever is lower

IH(max)

PU

BAT

5. It is assumed that the SCL and SDA pins are open drain with external pull−ups resistors tied to an external supply V

.

PU

2

6. V and V have been chosen to be fully compliant to I C specification at V = 1.8 V 10%. At 2.25V v V v 3.63 V the V

provides

IH

IL

PU

IL(max)

> 200 mV on noise margin to the required V

of the transmitter.

OL(max)

2

7. I C standard specifies V

for V v 2.0 V to be 0.2 x V

.

OL(max)

PU

8. Guaranteed by design. Not tested in production.

9. Regulation Mode control will reduce t

.

OFF_IBUSOCP

www.onsemi.com

10

FAN54161

Table 5. ELECTRICAL CHARACTERISTICS (Notes 4, 5, 6, 7) Unless otherwise specified: according to the circuit in Figure 1;

recommended operating range for T and T ; The Recommended Operating Conditions for DC Electrical Characteristics assume V =

OUT

J

A

2.7 V to 4.5 V and T = −40°C to 85°C, unless otherwise noted. Typical values are at T = 25°C, V

= 3.8 V, V = 1.8 V.

A

OUT

PU

Symbol

Parameter

Conditions

Min

15

Typ

Max Units

OVP_C CONTROL (External OVP FET Control)

V

VUSB OVP Threshold

VUSB OVP Hysteresis

VUSB UVLO Threshold

V

> V drives OVP_C low

USBOVP(TH)

16.5

1

18

V

USBOVP(TH)

USB

V

Falling

USBOVP(HYS)

USB

V

>V

USB

> V will

USBUVLO(TH)

2.5

2.6

2.7

USBUVLO(TH)

USBOVP(TH)

drive OVP_C high

V

VUSB UVLO Hysteresis

OVP_C Gate Drive Voltage

OVP_C Gate Turn−Off Time

Falling, V

USBUVLO(HYS)

< V

−

200

4.8

0.7

mV

V

USBUVLO(HYS)

USB

USBUVLO(TH)

V

will drive OVP_C low

OVP_C(HI)

V

< V

< V ;

USBOVP(TH)

4.5

5.1

USBUVLO(TH)

USB

measured from OVP_C to VBUS

t

Gate Capacitance =5.2nF; 2V/us V

ms

OFF_USBOVP

USB

ramp rate; Time from V

rising above

USB

V

to external FET open (where

USBOVP(TH)

VBUS stops increasing); V

compara-

USB

tor delay included; FDMC8321L N−Chan-

nel FET

2

I C TIMING SPECIFICATIONS

f

SCL Clock Frequency

Standard Mode

Fast Mode

100

400

kHz

ms

SCL

Fast Mode Plus

Standard Mode

Fast Mode

1000

t

Bus−Free Time Between STOP

and START Conditions

4.7

1.3

0.5

4

BUF

ms

Fast Mode Plus

ms

t

START or Repeated START Hold Standard Mode

Time

ms

HD;STA

Fast Mode

600

260

4.7

1.3

0.5

4

ns

ms

Fast Mode Plus

t

SCL LOW Period

Standard Mode

Fast Mode

LOW

ms

Fast Mode Plus

Standard Mode

Fast Mode

ms

t

SCL HIGH Period

ms

HIGH

600

260

4.7

600

260

250

100

50

ns

ms

Fast Mode−Plus

Standard Mode

Fast Mode

t

Repeated START Setup Time

Data Setup Time

SU;STA

SU;DAT

ns

Fast Mode−Plus

Standard Mode

Fast Mode

t

Fast Mode Plus

4. V

= V + 0.5 V or V

whichever is lower

IH(max)

PU

BAT

5. It is assumed that the SCL and SDA pins are open drain with external pull−ups resistors tied to an external supply V

.

PU

2

6. V and V have been chosen to be fully compliant to I C specification at V = 1.8 V 10%. At 2.25V v V v 3.63 V the V

provides

IH

IL

PU

IL(max)

> 200 mV on noise margin to the required V

of the transmitter.

OL(max)

2

7. I C standard specifies V

for V v 2.0 V to be 0.2 x V

.

OL(max)

PU

8. Guaranteed by design. Not tested in production.

9. Regulation Mode control will reduce t

.

OFF_IBUSOCP

www.onsemi.com

11

FAN54161

Table 5. ELECTRICAL CHARACTERISTICS (Notes 4, 5, 6, 7) Unless otherwise specified: according to the circuit in Figure 1;

recommended operating range for T and T ; The Recommended Operating Conditions for DC Electrical Characteristics assume V =

OUT

J

A

2.7 V to 4.5 V and T = −40°C to 85°C, unless otherwise noted. Typical values are at T = 25°C, V

= 3.8 V, V = 1.8 V.

A

OUT

PU

Symbol

I C TIMING SPECIFICATIONS

t Data Hold Time

Parameter

Conditions

Min

Typ

Max Units

2

Standard Mode

Fast Mode

0

3.45

900

450

1000

300

120

1000

300

120

300

120

ms

ns

ms

ns

pF

ns

HD;DAT

Fast Mode Plus

Standard Mode

Fast Mode

t

SCL Rise Time

20 + 0.1Cb

RCL

RDA

Fast Mode Plus

Standard Mode

Fast Mode

t

SDA Rise Time

Fast Mode Plus

Standard Mode

Fast Mode

t

SDA Fall Time

FDA

Fast Mode Plus

Standard Mode

Fast Mode

t

Stop Condition Setup Time

Capacitive Load for SDA and SCL

4

SU;STO

600

120

Fast Mode Plus

C

400

50

b

t

SP

Pulse width of spikes which must SCL, SDA only

be suppressed by input filter

0

4. V

= V + 0.5 V or V

whichever is lower

IH(max)

PU

BAT

5. It is assumed that the SCL and SDA pins are open drain with external pull−ups resistors tied to an external supply V

.

PU

2

6. V and V have been chosen to be fully compliant to I C specification at V = 1.8 V 10%. At 2.25V v V v 3.63 V the V

provides

IH

IL

PU

IL(max)

> 200 mV on noise margin to the required V

of the transmitter.

OL(max)

2

7. I C standard specifies V

for V v 2.0 V to be 0.2 x V

.

OL(max)

PU

8. Guaranteed by design. Not tested in production.

9. Regulation Mode control will reduce t

.

OFF_IBUSOCP

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

www.onsemi.com

12

FAN54161

Typical Characteristics

Unless otherwise specified: Default register settings, T = 25°C, VOUT = 3.8 V, VPU = 1.8 V.

A

25

20

15

10

5

10

−40 C

+25 C

+85 C

+25 C

+85 C

8

6

4

2

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VOUT(V)

Figure 3. VOUT Standby Current, VBUS=Open,

[ADC_EN]=0, RESET_N=HIGH

Figure 4. VOUT Shutdown Current,

VBUS=Open, RESET_N=LOW

1.4

−40 C

1.2

+25 C

+85 C

1.0

0.8

0.6

0

1

2

3

4

5

6

7

I OUT (A)

Figure 5. On Resistance from VBUS to

VOUT, Normalized to 1.0 A/25°C

Figure 6. Switch Closing, [SW_EN]=0 to

1, TA Configured for 5 V/3 A

Figure 7. Switch Opening, [SW_EN]=1 to

0, TA Configured for 5 V/3 A

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13

FAN54161

Typical Characteristics

Unless otherwise specified: Default register settings, T = 25°C, VOUT = 3.8 V, VPU = 1.8 V.

A

Figure 8. Switch Opening IBUS OCP Fault,

[IBUSOCP]=4A, [IBUSREG]=[IBATREG]=max, TA

Current Limit Raised from 3 A to 5 A

Figure 9. Load Transient Response, [IBATREG]=2A,

[IBUSREG]=3.5A, TA Configured for 5 V/5 A

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14

FAN54161

Functional Specifications

Power−up and Reset (VBUS and VOUT)

Charging Bypass Switch with Regulation Mode

When power is first applied to either VBUS or VOUT, an

internal power−on reset (POR) circuit ensures the default

state of all registers and circuits and keeps the switch in the

OPEN state. Power for all internal logic circuits comes from

the higher of VBUS and VOUT. This allows the FAN54161

Overview

The FAN54161 is designed to be placed in a system that

requires high current charging for a large battery. It is

essentially a high current bypass switch with protection that

provides a path from a charging source (adapter) to the

battery directly through a low resistance path. In order to

ensure safety of the battery as well as the system, the

FAN54161 features multiple hardware protection

mechanisms. Most of these result in the path from the

charging source to the battery being opened. Examples of

these are input over−voltage, over−current through the

switch and reverse current.

Some of the parameters are monitored and regulated such

that they are at or below a programmed threshold. This is

achieved by controlling the gate of the power switch.

However, this mode of operation is only meant to be used

temporarily while the system controller/host reacts to this

and corrects the system configuration to allow the switch to

return to a bypass mode (fully−on state).

2

to be I C programmable even with just one of the supplies

present (VBUS or VOUT).

The RESET_N pin is an active−low reset input. When the

RESET_N pin is asserted low externally, the FAN54161

2

remains in a reset state and does not support I C

communication. The switch is forced OPEN. This

corresponds to the SHUTDOWN state. The RESET_N pin

being low also forces the ADC in the FAN54161 to its

SHUTDOWN state.

In order to properly control and operate the FAN54161, a

valid supply must be present at VBUS or VOUT and the

RESET_N pin must be de−asserted (logic high state).

VUSB Power

The VUSB pin does not affect POR behavior of the

FAN54161 and should be considered a completely

independent power domain with respect to VBUS and

VOUT.

2

Many of the hardware protection mechanisms have I C

programmable thresholds, enable/disable controls,

interrupts with masks and status bits. The product block

diagram (Figure 1) provides an illustrative overview of the

functionality within the FAN54161.

The FAN54161 also utilizes a fully independent charge

pump based gate drive circuit to control an optional external

N−channel MOSFET for an additional level of input

protection from over voltage faults up to 32 V applied at the

USB port.

Hardware Fault Protection

The FAN54161 features hardware safety protection

monitors, some of which can cause the switch to OPEN if

enabled. Other than VBUS UVLO and IC Thermal

Shutdown, each hardware safety protection monitor has an

independently programmable enable bit.

The high current switch is closed by setting SW_EN = 1.

Before the switch closes, though, the IC is checked against

the following safety protection thresholds:

• VBUS UVLO

• VBUS OVP

• VOUT OVP

• VDROP OVP

• Thermal Shutdown

If any of these safety protection monitors are enabled and the

associated fault is triggered, the switch is not allowed to

close and the appropriate interrupt bit is set to report the fault

to the system controller/host. If no faults are triggered when

SW_EN bit is set, the switch is closed.

When the switch is closed, all enabled safety protection

monitors are armed. With the exception of VOREG,

VBATREG, IBATREG, and IBUSREG, if any enabled fault

is triggered, the switch is opened and its appropriate

interrupt bit is set to 1. Refer to Figure 10 for details.

When the switch is closed, if a VOREG, VBATREG,

IBATREG, or IBATREG fault is triggered, the internal logic

drives the gate of the bypass switch such that the current or

voltage does not exceed its regulation threshold.

Additionally, its appropriate interrupt bit is set to 1. It is

Bypass Switch Modes of Operation

Broadly speaking, the FAN54161 has four modes of

bypass switch operation.

1. OFF: This represents a lack of power to the

FAN54161.

2. SHUTDOWN: Valid power is applied to one of

VBUS or VOUT but the RESET_N input is

asserted low. In this state, no communication with

the FAN54161 is possible and the switch is forced

open.

3. STANDBY: Valid power is applied to one of

VBUS or VOUT and the RESET_N input is

de−asserted high. I2C communication is enabled,

but, the switch is not programmed to close.

4. SWITCH ENABLED: As evidenced by the

name, the FAN54161 bypass switch is closed in

this state. From the STANDBY state, when the

SW_EN bit is written with a 1, the FAN54161

enters the SWITCH ENABLED state.

In this state, the switch’s gate is controlled by the

control circuit of the FAN54161 to be either fully

on (bypass mode) or partially on (regulation mode)

based on the parameters being monitored.

www.onsemi.com

15

FAN54161

expected that the host will take action to correct the system

the TBUSOTP and TBATOTP registers) to the ADC’s

converted results of these channels. Therefore, if these fault

protections are enabled, it must be ensured that the ADC is

enabled and programmed to convert this channel.

For additional details on Hardware Fault Protection, refer

to Table 6 and Table 7.

configuration such that the FAN54161’s regulation control

loop can drive the gate of the power switch to make it fully

on again. Refer to Figure 11 for details.

The hardware protections for the VBUS connector and

battery (T_BUS and T_BAT) are implemented through

digital comparisons of a digital threshold (programmed in

FAULT_IRQ (FORCE SW_EN=0)

SW_EN

VOUT

VBUS

+

−

+

−

V_RCB(TH)

IBUSRCB_M

IBUSOCP_M

IBUSRCB_EN

IBUSOCP_EN

V_IBUS

V_IBUSOCP

+

−

V_{BUSUVLO(FALL)}

VBUS

+

−

T_J

+

T_SDN(TH)

−

TSDN_M

INT_N

VBUS

VOUT

V_DROP

+

−

+

−

IRQ

V_DROPOVP(TH)

VDROPOVP_M

VDROPOVP_EN

VBUS

V_BUSOVP(TH)

+

−

VBUSOVP_M

VBUSOVP_EN

WDT 0 ‘00’

Watchdog Expiry

VOUT

+

V_OUTOVP(TH)

−

VOUTOVP_M

VOUTOVP_EN

VDROPALM_EN

VBUS

VOUT

V_DROP

+

−

+

−

V_DROPALM(TH)

VDROPALM_M

Figure 10. Hardware Protection Logic Diagram

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16

FAN54161

Table 6. HARDWARE FAULT PROTECTION ENTRY SUMMARY

Safety

Feature

Safety Mode Deglitch

Time

Safety Mode Entry

Safety Mode Hardware Action

Safety Mode Register Action

V_BUS

V_BUSOVP(TH)

>

4us (OVP_DLY=0)

20us (OVP_DLY=1)

Open Bypass Switch

Pull INT_N low

SW_EN=0

VBUSOVP_INT=1

VBUS OVP

V_BUS

<

Open Bypass Switch

Pull INT_N low

VBUS UVLO

Falling

4us

VBUSINSERT_INT=1

VDROPALM_INT=1

(V_BUSUVLO(TH)− V_BUSUVLO(HYS)

)

4us (OVP_DLY=0)

20us (OVP_DLY=1)

VDROP

Alarm

Pull INT_N low

V_DROP> V_DROPALM(TH)

4us (OVP_DLY=0)

20us (OVP_DLY=1)

Open Bypass Switch

Pull INT_N low

SW_EN=0

VDROPOVP_INT=1

V_DROP> V_DROPOVP(TH)

VDROP OVP

V_{TS_BUS}< T_{BUS_TH}

(digital comparator)

Open Bypass Switch

Pull INT_N low

SW_EN=0

TBUSOTP_INT=1

TS_BUS

Overtemp

1s

V_{TS_BAT}< T_{BAT_TH}

(digital comparator)

Open Bypass Switch

Pull INT_N low

SW_EN=0

TBATOTP_INT=1

TS_BAT

Overtemp

Open Bypass Switch

SW_EN=0

ADC_EN bit does not change state

TSDN_INT=1

Thermal

Shutdown

T_J> T_SDN(TH)

800us

Disable ADC

Pull INT_N low

SW_EN=0

Reset registers to default (except TIMER_INT)

TIMER_INT=1

Open Bypass Switch

Pull INT_N low

Watchdog

Timer

Watchdog Timer Expired

N/A

Open Bypass Switch

Pull INT_N low

SW_EN=0

IBUSOCP_INT=1

50us (IBUSOCP_MODE=0)

1− Open Bypass Switch and enter Hiccup Mode

2− Wait 100ms then close switch

I_BUS> I_BUSOCP(TH)

IBUS OCP

Set SW_EN=0

IBUSOCP_INT=1

(Only after 6 failed Hiccup attempts)

3− If I

< I_BUSOCP(TH)continue charging

BUS

4us (IBUSOCP_MODE=1)

4− If I

> I_BUSOCP(TH)return to top (up to 6 attempts)

BUS

5− If still OCP leave Bypass Switch open

6− Pull INT_N low

Enter Regulation Mode

I_BUS> I_BUSREG(TH)

N/A

Limit I

to I_BUSREG(TH)

IBUSREG_INT=1

IBATREG_INT=1

VOREG_INT=1

IBUSREG

IBATREG

VOREG

BUS

Pull INT_N low

Enter Regulation Mode

((V _SRP− V_SRN) / R_SENSE) >

Limit I

to I_BATREG(TH)

BAT

I_BATREG(TH)

Pull INT_N low

Enter Regulation Mode

Limit V_OUTto V _OREG(TH)

Pull INT_N low

V_OUT> V_OREG(TH)

Enter Regulation Mode

Limit V

− V_SNSNto V_BATREG(TH)

(V_SNSP− V_SNSN) > V _BATREG(TH)

VBATREG_INT=1

VBATREG

VUSB OVP

SNSP

Pull INT_N low

Pull OVP_C low

Pull INT_N low

V_USB> V_USBOVP(TH)

No Deglitch

VUSBOVP_INT=1 (if SW_EN=1 or ADC_EN=1)

VUSBINSERT_INT=1

V_USB

<

Pull OVP_C low

Pull INT_N low

VUSB UVLO

Falling

(V_USBUVLO(TH)− V_USBUVLO(HYS)

)

4us (VOUTOVP_DLY=0)

20us (VOUTOVP_DLY=1)

Open Bypass Switch

Pull INT_N low

SW_EN=0

VOUTOVP_INT =1

V_OUT> V_OUTOVP(TH)

VOUT OVP

IBUS RCB

SW_EN=0

IBUSRCB_INT=1

Open Bypass Switch

Pull INT_N low

Reverse I _BUS> I_RCB(TH)

10us

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17

FAN54161

Table 7. HARDWARE FAULT PROTECTION EXIT (RECOVERY) SUMMARY

Safety

Feature

Safety Mode Exit (Recovery)

Recovery Hardware Action

Recovery Register Action

V_BUS< V _BUSOVP(TH)

Wait for host command

VBUS OVP

switch autorecovers

Pull INT_N low

VBUS UVLO

Rising

V_BUS> V _BUSUVLO(TH)

VBUSINSERT_INT=1

VDROP

Alarm

N/A

No Action

V_DROP< V _DROPOVP(TH)

Wait for host command

VDROP OVP

V_{TS_BUS}> T_{BUS_TH}

(digital comparator)

TS_BUS

Overtemp

V_{TS_BAT}> T_{BAT_TH}

(digital comparator)

TS_BAT

Overtemp

Wait for host command

Wait for host command to close Bypass

Switch; ADC auto recovery if ADC_EN=1

Thermal

Shutdown

T_J< T_SDN(TH)

Watchdog

Timer

SW_EN= 1 starts watchdog

I_BUS< I_BUSOCP(TH)

Wait for host command

Auto recovery after successful Hiccup

Keep SW_EN=1 after successful

Hiccup Mode retry.

Mode retry.

IBUS OCP

I_BUS< I_BUSOCP(TH)

During Hiccup Mode retry

OR

Wait for host command if all 6 Hiccup

retries fail.

OR

Set SW_EN=0 only after 6 failed

Hiccup attempts.

Exit Regulation Mode

Bypass Switch remains closed

I_BUS< I_BUSREG(TH)

((V _SRP− V_SRN) / R_SENSE) < I_BATREG(TH)

V_OUT< V _OREG(TH)

IBUSREG

IBATREG

VOREG

Exit Regulation Mode

Bypass Switch remains closed

Exit Regulation Mode

Bypass Switch remains closed

Exit Regulation Mode

Bypass Switch remains closed

(V _SNSP− V_SNSN) < V _BATREG(TH)

VBATREG

VUSB OVP

Drive OVP_C High

Pull INT_N low

V_USB< (V _USBOVP(TH)− V_USBOVP(HYS)

)

VBUSOVP_INT=1

Drive OVP_C High

Pull INT_N low

VUSB UVLO

Rising

V_USB> V _USBUVLO(TH)

VUSBINSERT_INT=1

VOUT < V _OUTOVP(TH)− V_OUTOVP(HYS)

Wait for host command

VOUT OVP

IBUS RCB

Reverse I_BUS> I_RCB(TH)

VBUS Input Over−Voltage Protection

VBUS Input Under−Voltage Lockout

When the voltage at the VBUS pin exceeds the

programmed V threshold for more than

If the voltage applied to VBUS fails to exceed the

V

threshold after an input plug−in event, the

BUSOVP(TH)

BUSUVLO(TH)

t

, the FAN54161 will:

1. Isolate VBUS from VOUT by opening the bypass

switch

bypass switch will remain open. Setting SW_EN to 1 while

V < V will keep the bypass switch open.

BUS

BUSOVPGLTCH

BUSUVLO(TH)

Once the VBUS voltage exceeds the V

BUSUVLO(TH)

2. Reset SW_EN to 0

threshold, the switch is allowed to close if SW_EN is set to

3. Set the VBUSOVP_INT bit to 1 and pull the

INT_N pin low

1.

From a closed position, the bypass switch will be forced

open if VBUS falls below

V

−

BUSUVLO(TH)

A VBUS OVP fault recovery is not automatic and requires

the host processor to re−enable the switch by programming

SW_EN to 1. The switch will not close again until after

V

. In addition, the V

interrupt

BUSUVLO(HYS)

BUSINSERT_INT

bit will be set, the INT_N pin is pulled low, and the SW_EN

bit will remain set.

If VOUT is available to support ADC operation during a

VBUS UVLO fault, ADC will operate according to the

ADC_EN setting.

VBUS has fallen below V

− V

.

BUSOVP(TH)

BUSOVP(HYS)

Any attempts to write SW_EN to 1 during a VBUS OVP

condition will result in a SW_EN self clear.

The ADC is not affected by this fault and operates

according to the ADC_EN setting.

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18

FAN54161

VDROP Alarm Reporting

While the bypass switch is closed, if the voltage measured

If the TBUSADC value falls below the TBUS_TH

threshold for more than t , the FAN54161

TBUS_TBAT_GLTCH

will:

across the switch (V

−

V

)

exceeds the

,

BUS

OUT

V

threshold for more than t

1. Isolate VBUS from VOUT by opening the bypass

switch

2. Reset SW_EN to 0

3. Set the TBUSOTP_INT bit to 1 and pull the

INT_N pin low

DROPALM(TH)

VDROPALMGLTCH

the FAN54161 sets the VDROPALM_INT bit to 1 and pulls

the INT_N pin low. This alerts the host processor that the

FAN54161 is operating in a condition that may soon trigger

a VDROP OVP fault which would force the switch to open.

This alert feature warns the host processor to reprogram the

Travel Adapter or the FAN54161’s charge parameter

settings to prevent a VDROP OVP fault from triggering.

There is no automatic recovery from this fault, and the host

must program SW_EN to 1 to close the switch again. The

ADC is not affected by this fault and operates according to

the ADC_EN setting.

This digital comparison scheme does not restrict the use

of NTC thermistor type or pullup resistor value. The desired

TBUS_TH threshold can be programmed based on the

external components selected by the system designer.

VDROP Over−Voltage Protection

While the bypass switch is closed, if the voltage measured

across the switch (V

−

V

OUT

)

exceeds the

BUS

V

threshold for more than t

, the

DROPOVP(TH)

VDROPGLTCH

FAN54161 will:

1. Isolate VBUS from VOUT by opening the bypass

switch

2. Reset SW_EN to 0

3. Set the VBUSOVP_INT bit to 1 and pull the

INT_N pin low

Battery Over−Temperature Fault

The FAN54161 can monitor the temperature of the battery

by measuring the battery pack’s thermistor output pin. This

protection prevents bypass charging from continuing if the

battery temperature rises to a dangerous level. A TS_BAT

pull−up resistor tied to an externally supplied reference

If a VDROP OVP fault occurs, the host processor should

reprogram the FAN54161’s charging parameter settings to

prevent a VDROP OVP fault from reoccurring the next time

the bypass switch is closed. Once the VDROP OVP fault is

removed, the host processor must set SW_EN to 1 in order

to close the bypass switch again. The VDROP OVP

protection is disabled by default to allow the switch to close

even if the difference between VBUS and VOUT is greater

than the VDROP OVP threshold. If VDROP OVP

protection is enabled before the switch is closed, care should

be taken to ensure that VBUS−VOUT is less than the

VDROP OVP threshold, otherwise the VDROP OVP

protection will prevent the switch from closing when writing

SW_EN to 1.

voltage (recommended V

= 2.4 V) along with the

EXTREF

battery pack’s NTC thermistor generate a temperature

dependent voltage on the TS_BAT pin. The FAN54161’s

ADC must be enabled to measure and digitally compare the

voltage at TS_BAT to a programmed TBAT_TH threshold.

The ADC’s measurement of the TS_BAT voltage can be

monitored by the TBATADC register. A digital comparison

is made between the TBATADC register contents and the

TBAT_TH threshold.

If the TBATADC value falls below the TBAT_TH

threshold for more than t

will:

, the FAN54161

TBUS_TBAT_GLTCH

1. Isolate VBUS from VOUT by opening the bypass

switch

2. Reset SW_EN to 0

The ADC is not affected by this fault and operates

according to the ADC_EN setting.

3. Set the TBATOTP_INT bit to 1 and pull the

INT_N pin low

Input Connector Over−Temperature Fault

The FAN54161 can monitor the temperature of the input

connector with an external NTC thermistor tied from the

TS_BUS pin to ground. This protection prevents bypass

charging from continuing if the input connector temperature

rises to a dangerous level. A TS_BUS pullup resistor tied to

an externally supplied reference voltage (recommended

There is no automatic recovery from this fault, and the host

must program SW_EN to 1 to close the switch. The ADC is

not affected by this fault and operates according to the

ADC_EN setting.

This digital comparison scheme does not restrict the use

of NTC thermistor type or pullup resistor value. The desired

TBAT_TH threshold can be programmed based on the

external components selected by the system designer.

V

= 2.4 V) along with the NTC thermistor generate

EXTREF

a temperature dependent voltage on the TS_BUS pin. The

FAN54161’s ADC must be enabled to measure and digitally

compare the voltage at TS_BUS to a programmed

TBUS_TH threshold. The ADC’s measurement of the

TS_BUS voltage is monitored by the TBUSADC register. A

digital comparison is made between the TBUSADC register

contents and the TBUS_TH threshold.

Thermal Shutdown Protection

When the FAN54161’s junction temperature exceeds the

thermal shutdown threshold (T

), the IC will:

SDN(TH)

1. Isolate VBUS from VOUT by opening the bypass

switch

2. Reset SW_EN to 0

3. Set the TSDN_INT bit to 1 and pull the INT_N

pin low

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19

FAN54161

4. Disable ADC conversion and ADC reference.

ADC enters standby state, maintains ADC_EN=1

in REG 0x06h[3:2], the new watchdog setting will not take

effect until the next I C read/write transaction.

2

If the host processor fails to clear the watchdog timer and

allows the watchdog timer to expire, the FAN54161 will:

1. Isolate VBUS from VOUT by opening the bypass

switch

There is no automatic recovery from this fault, and the host

must program SW_EN to 1 to close the switch again.

IBUS Over Current Protection

If the input current through the bypass switch exceeds the

2. Reset all registers to their default values

3. Set the TIMER_INT bit to 1 and pull the INT_N

pin low

programmed I

threshold, the bypass switch will

BUSOCP(TH)

be forced open to protect the IC, battery, and system from an

over−current fault condition. The IBUSOCP_MODE

control bit determines the manner in which the bypass

switch will react to an IBUS over−current fault event. The

IC internally monitors the IBUS current through the bypass

switch.

VOUT Over−Voltage Protection

If the voltage applied to the VOUT pin exceeds the

programmed

V

threshold for more than

OUTOVP(TH)

t , the FAN54161 will:

VOUTOVPGLTCH

1. Isolate VBUS from VOUT by opening the bypass

switch

2. Reset SW_EN to 0

3. Set the VOUTOVP_INT bit to 1 and pull the

INT_N pin low

When IBUSOCP_MODE=0 and I

> I

for

BUS

BUSOCP(TH)

more than t , the FAN54161 will:

IBUSOCPGLTCH

1. Isolate VBUS from VOUT by opening the bypass

switch

2. Reset SW_EN to 0

3. Set the IBUSOCP_INT bit to 1 and pulls the

INT_N pin low

4. Rely on the host processor to send a SW_EN=1

command to close the switch again

If a VOUT OVP fault occurs, the host processor should

reprogram the FAN54161’s charge parameter settings to

prevent a VOUT OVP fault from reoccurring the next time

the bypass switch is closed. Once the VOUT OVP fault is

removed, the host processor must set SW_EN to 1 in order

to close the bypass switch again. The switch will not close

When IBUSOCP_MODE=1 and I

> I

for

BUS

BUSOCP(TH)

more than t , the FAN54161 will:

IBUSOCPGLTCH

1. Enter the Hiccup Mode cycle and isolate VBUS

and VOUT by opening the bypass switch

again until after VOUT has fallen below V

−

OUTOVP(TH)

V

.

OUTOVP(HYS)

2. Maintain SW_EN =1 during hiccup mode retry

3. Wait 100 ms, close the bypass switch to check if

the IBUS over−current condition is removed

♦ If the IBUS over−current condition is removed, the

bypass switch will remain closed, keep SW_EN=1,

and exit the Hiccup Mode cycle

The VOUT over−voltage protection feature serves as an

additional layer of protection in case the VOREG CV

regulation loop is not fast enough to respond to a VOUT

over−voltage fault, or if VOREG regulation is disabled.

The ADC is not affected by this fault and operates

according to the ADC_EN setting.

♦ If the IBUS over−current condition remains, the

Hiccup Mode cycle (starting from step 1) is repeated

up to 6 more times

♦ If the IBUS over−current condition remains after 6

attempts, the IBUSOCP_INT interrupt bit is set to 1

and the INT_N pin is pulled low. The bypass switch

is forced open and SW_EN is reset to 0 and the host

processor must set SW_EN=1 to close the switch

again

IBUS Reverse Current Protection

If the reverse current through the bypass switch (from

VOUT to VBUS) rises above the programmed

I

threshold, the bypass switch will be forced open to

RCB(TH)

prevent excessive reverse current flow from the battery back

to the input source. The IRCB control bit sets

the I

reverse current threshold (0 = 100 mA, 1 =

RCB(TH)

3 A). The direction of I

is defined as current flow

RCB(TH)

from VOUT to VBUS. The IC internally monitors the IBUS

current through the bypass switch.

When the current from VOUT to VBUS rises

The ADC is not affected by this fault and operates according

to the ADC_EN setting.

above I

the FAN54161 will:

for more than the t

deglitch time,

RCB(TH)

RCBGLTCH

Watchdog Timer

To prevent unattended charging that may potentially

damage the battery and/or system while the bypass switch is

closed, the FAN54161 uses a watchdog timer as an

additional layer of protection. The WDT control bits set the

watchdog timer period and whether the watchdog timer

protection will be enabled. If enabled, the watchdog timer

starts when SW_EN is programmed to 1. To clear the

watchdog timer, the host processor must execute an I C

read or write command to any of the FAN54161’s I C

registers. When changing the setting of the watchdog timer

1. Isolate VBUS from VOUT by opening the bypass

switch

2. Reset SW_EN to 0

3. Set the IBUSRCB_INT bit to 1 and pull the

INT_N pin low

4. Rely on the host processor to send a SW_EN=1

command to close the switch again

2

The ADC is not affected by this fault and operates according

to the ADC_EN setting.

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20

FAN54161

VFAIL Detection

Regulation Loops

In bypass charging applications, a failure of the bypass

charging switch (however, this is rare) could result in the

travel adapter output being directly connected to the battery

pack which can cause a potentially dangerous system

Figure 11 illustrates the logic that causes the FAN54161

to enter regulation mode.

Either of the following four fault protections being

triggered can cause the switch to operate in regulation mode

as follows:

fault. A V

comparator monitors the voltage at PMID

FAIL

while the bypass switch is open to detect the presence of a

leakage path from VBUS to PMID (when TA is attached) or

VOUT to PMID (when battery is connected) which would

indicate a failure in the bypass charging FET. During VFAIL

1. If the voltage at VOUT exceeds V

, and

OREG(TH)

VOREG_EN=1, the bypass switch will be

regulated such that V

is limited to V

.

OUT

OREG(TH)

2. If the voltage across SNSP and SNSN exceeds

, and VBATREG_EN=1, the bypass

detection, a R

pulldown resistor is connected to PMID

V

BATREG(TH)

FAIL

and a comparator checks if the PMID voltage exceeds the

VFAIL threshold. R will be disconnected from PMID

switch will be regulated such V

is limited to

BAT

V

.

FAIL

BATREG(TH)

anytime the bypass switch is enabled to avoid power

consumption during bypass charging.

3. If I

(sensed as a voltage across SRP and SRN)

BAT

exceeds I

, and IBATREG_EN=1, the

BATREG(TH)

If the detection determines that V

> V

for more

bypass switch will be regulated such that I

is

PMID

FAIL

BAT

than t , the FAN54161 will:

VFAIL_GLTCH

limited to I

.

BATREG(TH)

1. Set the VFAIL_INT bit to 1 and pull the INT_N

pin low

4. If I

(from VBUS to VOUT) exceeds

BUS

I

, and IBUSREG_EN=1, the bypass

BUSREG(TH)

switch will be regulated such that I

is limited

BUS

A VFAIL interrupt alerts the host that damage to the bypass

charging FET has occurred. The host can then alert the

system bypass charging controller to clamp the travel

adapter’s output voltage to the battery pack’s float voltage

to prevent an overcharge of the battery. Additionally, the

host can alert the end user that the portable device is

damaged and should be returned for repair.

If VFAIL_EN=1, VFAIL detection is momentarily

activated when:

to I

.

BUSREG(TH)

It must be noted that the switch essentially becomes more

resistive during regulation mode. This will cause more

power dissipation in the switch and a greater likelihood of

the junction temperature reaching or exceeding the

shutdown threshold T

. Therefore it is imperative for

SDN(TH)

the system host controller to update the system

configuration such that none of the above four monitors are

triggered. This can be done by increasing the thresholds in

the FAN54161 or changing other external system

parameters (ex: adapter voltage or current limit).

1. SW_EN is set from 0 to 1, while ADC_EN=0 and

RESET_N=1. VFAIL detection occurs before the

charge pump gate drive turns on the bypass

charging FET but after the main bandgap reference

is enabled

2. ADC_EN is set from 0 to 1, while SW_EN=0 and

RESET_N=1

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21

FAN54161

VOREG_EN

V_OREG(TH)

VBATREG_EN

V_BATREG(TH)

Switch Regulation

Control

IBATREG_EN

I_BATREG(TH)

IBUSREG_EN

I_BUSREG(TH)

VOREG_EN

VOUT

+

−

V_OREG(TH)

VOREG_M

VBATREG_EN

INT_N

SNSP

SNSN

V_BAT

+

−

+

V_BATREG(TH)

IRQ

−

VBATREG_M

IBATREG_EN

SRP

SRN

I_BAT−SENSE

I_BATREG(TH)

+

−

+

−

IBATREG_M

IBUSREG_EN

I_BUS−SENSE

I_BUSREG(TH)

IBUS Current Monitor

+

−

IBUSREG_M

Figure 11. Switch Regulation Mode Entry Diagram

External N−Channel MOSFET Gate Control (OVP_C)

The FAN54161 utilizes an additional protection scheme

to protect the bypass switch from over voltage faults up to

32 V. Integrating a charge pump based gate control circuit,

the FAN54161 can sense an over voltage fault applied to

the VUSB input pin while controlling an external

N−channel MOSFET to isolate the over voltage fault

condition from the bypass switch’s VBUS input pin. The

VUSB pin serves as the power supply input for the charge

pump gate control and also as the sense pin for an VUSB

over voltage fault. Connect an at least 32 V rated N−channel

MOSFET with its source to VBUS, drain to VUSB, and gate

to OVP_C.

is set in the INT1, INT2 or INT3 register and its

corresponding mask bit is a 0 (unmasked), the INT_N pin is

asserted low. For proper interrupt reporting, the ADC must

be enabled or the switch closed.

Analog to Digital Converter

Feature Summary

The integrated 10−bit Analog−to−Digital Converter in the

FAN54161 comprises the following features:

1. Fully Differential Input high−accuracy SAR ADC

2. Up to 9 channels that can be independently

configured for conversion

(i) Hardware protection based on digitized

result of connector (VBUS) temperature and

Battery temperature

The OVP_C gate control pin will enable the external

N−channel MOSFET when V

< V

or V

<

>

USBUVLO(TH)

USB

V

.

If V

< V

USBOVP(TH)

USB

USBUVLO(TH) USB

3. Single−shot or Continuous conversion

4. Fast throughput

, the OVP_C gate control will disable the

USBOVP(TH)

external N−channel MOSFET and set the appropriate

VUSB fault interrupt.

(i) 54 ms conversion time for a single channel

The OVP_C gate control and VUSB OVP detection

circuits operate completely independent of the bypass

switch and are solely powered by the VUSB input. If an

external N−channel MOSFET is not used, the VUSB pin

must be left floating and the OVP_C pin must be connected

to VBUS (preferred) or can be left floating. This will not

affect bypass switch operation.

without averaging

(ii) 1166ms conversion time for all 9 channels

with 16 samples per channel

5. Configurable averaging

(i) Enable/Disable for all channels

(ii) Programmable options of 8− or 16−sample

average per channel

6. Post−processed Output Format

Interrupt Mechanism

Figures 10 and 11 illustrate the interrupt and mask

architecture that drives the INT_N pin.

The FAN54161 features interrupt flag and interrupt mask

registers that contain interrupt bits for all the fault protection

monitors, in addition to interrupt flags for other events. All

interrupt bits are clear−on−read. When an interrupt flag bit

(i) ADC output format removes the need for

host post−processing

7. Fully configurable through digital I C interface

2

(i) Interrupt based indication of conversion

completion

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22

FAN54161

ADC Power Supply

2. IBAT has special considerations since it measures

current through a sense resistor that is part of the

external application circuit. Depending on the

The ADC operation is primarily focused during charging

when a valid input is present at VBUS. However, the ADC

can operate with a valid supply on VOUT (possibly from the

battery) even without a valid VBUS input. For reliable

operation, the voltage at VBUS or VOUT should be no less

than 3.1 V.

The ADC does not restrict the conversion of the VBUS or

IBUS channels when a valid VBUS is not present. If the

channel is enabled and conversion is started, the ADC will

report the result of whatever the voltage and currents are for

VBUS and IBUS which would typically be zero.

R

sense

value used, RSENSE should be

programmed for the correct ADC reading on

IBAT.

3. T_BUS and T_BAT are meant for measuring

external NTC voltages pulled up externally to

2.4V. However, they can also be used as general

purpose inputs that conform to the same signal

range shown in the table.

4. The accuracy referred to the input is based on error

analysis of the entire signal chain comprising the

pre−scalars and the ADC. Refer to the Electrical

Characteristics table of the ADC for the referenced

parameters.

ADC Channel Summary

Table 8 demonstrates all the possible channels that the

ADC in the FAN54161 can be configured to convert.

1. Every signal is processed through an analog

pre−scalar circuit that converts the incoming signal

range in volts, amps or °C to the ADC input range.

Table 8. ADC CHANNEL SUMMARY

Input Referred Accuracy

Signal Range

(V, A, °C)

LSB Step

(mV, mA, °C)

Channel #

Name

at room temp

0

1

VBUS

VOUT

0.3 to 6.1

0 to 5.0

7.3

5.3

11

14

VBAT

(charging)

2.5 to 5.0

5.3

14

2

VBAT

(discharging)

11

3

4

5

6

7

8

VDROP

IBUS

0 to 1.0

0 to 7.0

2.9

14.6

2.9

6

34

73

12

1

IBAT

−7.0 to +7.0

0 to 2.4

T_BUS

T_BAT

T_DIE

0 to 2.4

2.9

25 to 150

0.067

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23

FAN54161

ADC Configuration

If the ADC is in one−shot conversion mode (ADC_RATE

= 0), the host should issue I C read commands to any of the

results registers (REG 0x13 to 0x23) after the ADC_DONE

interrupt is issued.

2

There are two registers, ADC_CHANNEL and

ADC_CONTROL, which are used to configure and control

the ADC. All 9 channels have independent enable bits which

reside in these registers.

The ADC_CONTROL register and ADC_CHANNEL

register values should not be reprogrammed when the ADC

is performing a conversion.

If the ADC is in continuous conversion mode

2

(ADC_RATE = 1), the host can issue I C read commands to

any of the results registers (REG 0x13 to 0x23) even while

the ADC is performing conversions and storing results in

these registers.

ADC Control

The ADC can be configured to perform a one−shot

conversion or perform continuous conversion by setting the

ADC_RATE bit to 1.

An ADC conversion is initiated by setting the ADC_EN

bit to 1. Once initiated, the ADC will convert the channels

enabled for conversion according to the average mode

selected (programmed by AVG_EN and SAMPLES). The

enabled ADC channels are converted in order (LSB to MSB

of ADC_CHANNEL register), followed by the ICTEMP bit

in the ADC_CONTROL register.

• If the ADC_RATE bit is 0 (one−shot conversion), the

ADC stores the results in the appropriate registers and

sets the ADC_DONE interrupt bit. The ADC_EN bit is

cleared to 0 after the conversion of all channels is

complete.

ADC Based Over−temperature Protection

The two pins TS_BUS and TS_BAT are used to measure

temperature of the VBUS connector and the battery

respectively, by measuring voltage of an external NTC

thermistor. This thermistor has an external pull−up to a 2.4 V

supply. The ADC also converts the signal on these two pins

to 10−bit results and stores them in the registers

TBUS_MSB, TBUS_LSB, TBAT_MSB and TBAT_LSB

respectively. These results are used in the following manner

described to provide hardware protection for

over−temperature of the VBUS connector or battery. The

logic to explain this is illustrated in Figure 12.

• There are two registers to configure a digital

over−temperature threshold called TBUSOTP and

TBATOTP respectively.

• If the ADC_RATE bit is 1 (continuous conversion), the

ADC stores the results in the appropriate registers and

immediately begins a new conversion. In order to stop

conversions, it is recommended to set the ADC_RATE

bit to 0. This will ensure a complete conversion where

the ADC_DONE interrupt bit is set and the ADC_EN

bit is cleared to 0 similar to a normal one−shot

conversion.

• When the voltage measured by the ADC on TS_BUS or

TS_BAT drops below the value in the registers

TBUSOTP or TBATOTP respectively, the

over−temperature hardware protection is triggered.

• If TBUSOTP_EN or TBATOTP_EN bits in the

PROTECT_EN register are set to 1, and in addition, the

corresponding TBUSADC_EN or TBATADC_EN bits

are enabled, then the TBUSOTP or TBATOTP fault

being triggered will result in the switch of the

FAN54161 to be opened.

♦ Writing a 0 to the ADC_EN bit during continuous

conversion is not recommended. This will

immediately stop conversion without completing

even the currently scheduled channel’s conversion.

The ADC_DONE interrupt bit will not be set.

• This also causes the interrupt bit TBUSOTP_INT or

TBATOTP_INT to be set accordingly, and if unmasked,

will assert the INT_N pin low.

Example 1: TBUSOTP_EN = 1 and TBUSADC_EN = 1

If the output of the ADC for the TBUS channel

(TBUS_MSB, TBUS_LSB) drops below the value

programmed in TBUSOTP, the switch will open and

TBUSOTP_INT will be set.

ADC Output Format

Each channel of the ADC has a dedicated pair of registers

(an MSB register and an LSB register) where the input

referred results are stored after a conversion is completed.

Each pair is used to report the ADC’s converted result and

polarity in binary format.

Example 2: TBATOTP_EN = 1 and TBATADC_EN = 0

If the output of the ADC for the TBAT channel

(TBAT_MSB, TBAT_LSB) drops below the value

programmed in TBATOTP, the switch will not open and the

TBATOTP_INT will not be set.

Example 1: if the IBAT current is 5 A, the ADC’s output in

10−bit format is converted back to represent 5 A = 5000 mA

= 0b0000100111000100. This value is stored in the registers

IBAT_MSB and IBAT_LSB.

Although the value in the ADC result registers exceeds that

in the threshold register, since the ADC is not enabled to

convert that channel, the result cannot be trusted and hence

is not allowed to control the switch.

If IBAT is −5 A instead, the final result stored in

0b1000100111000100.

ADC Result Access

The required sequence for reading the results of any ADC

channel is to first read its MSB register followed by its LSB

register.

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24

FAN54161

ADC Output of TS_ BUS is compared

against programmed TBUS OTP

threshold

FAULT_ IRQ

(Force SW_EN=0)

TBUSADC [9:0]

TBUS_TH [6:0]

+

−

TBUSOTP_EN

TBUSADC_EN

TBUSOTP_MASK

INT_N

ADC Output of TS_BAT is compared

against programmed TBAT OTP

threshold

IRQ

TBATADC_EN

TBATADC [9:0]

TBAT_TH [6:0]

+

−

TBATOTP_MASK

TBATOTP_ EN

Figure 12. ADC Monitored Hardware Protection Diagram

2

Bus Timing

I C Interface

Data is transferred when SCL is LOW. Data is clocked in

on the rising edge of SCL. Typically data transitions at or

after the subsequent falling edge of SCL in order to provide

ample setup time for the next data bit to be ready before the

subsequent rising edge of SCL.

Introduction

2

The FAN54161 I C specification is compatible with the

Standard, Fast Mode, Fast Mode+ and High Speed Mode

specifications.

• The FAN54161’s SCL pin is an input and the SDA pin

is an open−drain bi−directional output.

Data change allowed

• The SDA pin pulls the the SDA bus low only when data

is being read out from the FAN54161 or during the

SDA

2

“acknowledge” bit duration of a valid I C transaction.

T_H

• All data is shifted in MSB first (Bit 7).

• The FAN54161 supports single register read and write

transactions as well as multiple register

read transactions.

T_SU

SCL

Figure 13. Data Transfer Timing

Selectable I²C Slave Address

The ADR pin sets the 7−bit I C slave address of the

2

The idle state of the I C bus is SDA and SCL both in the

device. The FAN54161 can be set for three unique slave

addresses. To set the 7−bit slave address to 0x65h, tie the

ADR pin to a valid supply with a 10 kOhm pullup. To set the

slave address to 0x66h, float the ADR pin. To set the slave

address to 0x67h, connect the ADR pin to ground.

high state. A valid transaction begins with a START

condition which occurs when SDA transitions from HIGH

to LOW when SCL remains HIGH.

T_HD;STA

Slave Address

MS Bit

SDA

Note that the ADR pin logic state is checked in order to set

2

the corresponding I C address during power−up from

previous state of no power supply or when the RESET_N pin

is toggled from LOW to HIGH.

SCL

Figure 14. I²C Start Condition

2

Table 9. I C Slave Address when ADR = High (0x65h, 7 bit)

A valid transaction ends with a STOP condition which

occurs when SDA transitions from LOW to HIGH when

SCL remains HIGH.

A6

A5

A4

A3

A2

A1

A0

R/W

1

0

1

0

1

X

Slave Releases Master Drives

t_HD;STO

2

Table 10. I C Slave Address when ADR = Float (0x66h, 7 bit)

ACK(0) or

NACK(1)

A6

A5

A4

A3

A2

A1

A0

R/W

SDA

SCL

1

0

1

0

X

2

Table 11. I C Slave Address when ADR = Low (0x67h, 7 bit)

A6

A5

A4

A3

A2

A1

A0

R/W

Figure 15. I²C Stop Condition

1

0

1

X

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25

FAN54161

A REPEATED START condition is functionally equivalent to a STOP condition followed immediately by a START condition.

Read and Write Transactions

Single Register Write Transaction

The FAN54161 supports the following protocol to write to a single register at a time.

Legend

Master to Slave Slave to Master

Bit Widths

1

7

1

0

1

8

1

8

1

S

Slave Address

A

Reg Addr

A

Data

A

P

R/:W

START

ACK

STOP

Figure 16. Single Register Write Transaction

Single Register Read Transaction

The FAN54161 supports the following protocol to read from a single register at a time.

Legend

Master to Slave Slave to Master

Bit Widths

1

7

1

0

1

8

1

7

1

8

1

S

Slave Address

A

Reg Addr

A

Sr

Slave Address

1

A

Data

nA

P

Addr= Reg Addr

REPEAT

START

ACK

Not ACK

R/:W

STOP

Figure 17. Single Register Read Transaction

Multiple Register Read Transaction

The FAN54161 supports the following protocol to read from multiple registers at a time.

Legend

Master to Slave Slave to Master

Bit Widths

1

7

1

0

1

8

1

7

1

8

1

S

Slave Address

A

Reg Addr

A

Sr

Slave Address

A

Data X

A

Addr= Reg Addr

ACK

REPEAT

START

R/:W

8

1

8

1

8

1

Data X +1

A

Data X+2

A

Data X+3

nA P

Addr= Reg Addr+ 1

Addr= Reg Addr+ 2

Addr= Reg Addr+ 3

Not ACK

Figure 18. Multiple Register Read Transaction

STOP

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26

FAN54161

PCB Layout and Component Placement

• Place via−in−pad on all VBUS and VOUT landing pads

and mirror the top layer copper to the bottom layer for

an additional thermal relief path.

Proper PCB layout and component placement will

provide an optimal thermal relief path for the FAN54161 IC

as well as a low impedance charging path. The VBUS (A6

through G6) and VOUT (A3/A4 through G3/G4) balls, and

the associated charging path, carry the majority of the

charging current when the FAN54161 switch is closed.

Layout recommendations:

• Increase copper weight to greater than 1 oz, if possible.

• Use large as possible copper area for both VBUS and

VOUT planes and ensure that copper floods the landing

pads of all the VBUS and VOUT balls.

♦ Follow the recommended placement for CBUS and

COUT shown in Figure 19.

• Place a floating copper plane on PMID (A5 through

G5) to provide an additional thermal relief path.

♦ Place via−in−pad on all PMID landing pads and

mirror the top layer copper to the bottom layer for an

additional thermal relief path.

Figure 19. VBUS and VOUT Copper Top Layer Routing

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27

FAN54161

2

I C Registers and Bit Descriptions

Register Map

Register

Bit Name

Name

IC INFO

INT1 MASK

INT2 MASK

INT1

Adr

00h

01h

02h

03h

04h

7

6

5

4

3

2

1

0

Reserved

REV

PN

VBUSOVP_M

Reserved

IBUSREG_M

ADCDONE_M

VBATREG_M

IBATREG_M

VDROPOVP_M

IBATREG_INT

VOREG_M

VBUSINSERT_M

VOREG_INT

TBUSOTP_M

VBATINSERT_M

TBUSOTP_INT

TBATOTP_M

TSDN_M

IBUSRCB_M

IBUSOCP_M

IBUSRCB_INT

IBUSOCP_INT

VBUSPD_EN

REG_RST

VDROPALM_M

VBUSOVP_INT

Reserved

IBUSREG_INT VBATREG_INT

TBATOTP_INT

TSDN_INT

TBATOTP_EN

IRCB

INT2

ADCDONE_INT VDROPALM_INT VDROPOVP_INT VBUSINSERT_INT VBATINSERT_INT

PROTECT_EN 05h

VBUSOVP_EN

IBUSREG_EN

VBATREG_EN

RSENSE

IBATREG_EN

SW_EN

VOREG_EN

TBUSOTP_EN

SW_CONTROL 06h VDROPOVP_EN VDROPALM_EN

WDT

ADC_CONTROL 07h

ADC_CHANNEL 08h

ICTEMPADC_EN

VBUSADC_EN

Reserved

ADC_EN

VBATADC_EN

Reserved

ADC_RATE

IBATADC_EN

Reserved

AVG_EN

SAMPLES

IBUSADC_EN

VOUTADC_EN VDROPADC_EN

TBUSADC_EN

IBUSOCP_MODE

TBATADC_EN

OVP_DLY

PROT_DELAY

VBUSOVP

VOREG

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

IBUSOCP_TH

Reserved

VBUSOVP_TH

VOREG

VDROPOVP

VDROP_ALM

VBATREG

IBATREG

VDROPOVP_TH

VDROP_ALM

VBATREG

IBATREG

IBUSREG

Reserved

IBUSREG

TBUSOTP

TBATOTP

Reserved

TBUS_TH

TBAT_TH

VBUS_MSB

VBUS_LSB

IBUS_MSB

IBUS_LSB

VOUT_MSB

VOUT_LSB

VDROP_MSB

VDROP_LSB

VBAT_MSB

VBAT_LSB

IBAT_MSB

IBAT_LSB

Reserved

VBUSADC_MSB

IBUSADC_MSB

VOUTADC_MSB

Reserved

VBUSADC_LSB

Reserved

IBUSADC_LSB

VOUTADC_LSB

Reserved

VDROPADC_MSB

VDROPADC_LSB

VBATADC_LSB

IBATADC_LSB

TBUSADC_LSB

Reserved

VBATADC_MSB

IBATADC_MSB

IBATADC_POL

Reserved

TBUS_MSB

TBUS_LSB

TBAT_MSB

TBAT_LSB

Reserved

TBUSADC_MSB

Reserved

TBATADC_MSB

TBATADC_LSB

ICTEMPADC

ICTEMP_ADC 23h

CONTROL1

CONTROL2

INT3 MASK

INT3

50h

51h

52h

53h

54h

TJSHDN

Reserved

VOUTOVP_DLY

VOUTOVP_EN

VOUTOVP_TH

VOUTOVP_M

VOUTOVP_INT

VFAIL_EN

IBUSRCB_EN

IBUSOCP_EN

Reserved

VOREG_ST

Reserved

VFAIL_M

VUSBOVP_M

VUSBOVP_INT

Reserved

VUSBINSERT_M

VUSBINSERT_INT

VUSBINSERT_ST

TIMER_INT

IBUSREG_ST

VFAIL_INT

STATUS1

VBATREG_ST

IBATREG_ST

VBUSINSERT_ST VBATINSERT_ST

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28

FAN54161

Bit Descriptions

Default values are in bold text. Default values are with V

= 3.8 V and V

= open.

BAT

BUS

IC INFO

Register Address = 00h

Default = 0000 1010

Bit

7

Name

Default

Type

Read

Description

Reserved

REV

0

Reserved. Always reads 0.

6

0

5:3

2:0

001

010

This indicates the revision number of the IC.

This indicates the part number of the IC.

PN

INT1 MASK

Register Address = 01h

Default = 0000 0000

Bit

Name

Default

Type

Description

7

VBUSOVP_M

0

R/W

This is the interrupt mask for a VBUS over voltage fault.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

6

IBUSREG_M

0

R/W

This is the interrupt mask for an IBUS over current regulation event where the switch

operates in regulation mode to limit the input current to the IBUSREG setting.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

5

4

3

2

1

0

VBATREG_M

IBATREG_M

VOREG_M

0

R/W

This is the interrupt mask for the VBAT CV regulation loop.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

This is the interrupt mask for the IBAT CC regulation loop.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

This is the interrupt mask for the VOUT CV regulation loop.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

TBUSOTP_M

TBATOTP_M

IBUSRCB_M

This is the interrupt mask for a T_BUS over temperature fault.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

This is the interrupt mask for a T_BAT over temperature fault.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

This is the interrupt mask for an IBUS reverse current fault.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

INT2 MASK

Register Address = 02h

Default = 0000 0000

Bit

7

Name

Default

Type

Description

Reserved

0

Read Reserved. Always reads 0.

6

ADCDONE_M

R/W

This is the interrupt mask for a completed ADC conversion.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

5

4

3

VDROPALM_M

VDROPOVP_M

VBUSINSERT_M

0

This is the interrupt mask for when VDROP rises above its alarm threshold.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

This is the interrupt mask for when VDROP rises above its OVP threshold.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

This is the interrupt mask for when VBUS rises above V

or falls below

BUSUVLO(TH)

V

− V

.

BUSUVLO(TH)

BUSUVLO(HYS)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

2

VBATINSERT_M

0

R/W

This is the interrupt mask for when V rises above V or falls below

SNSP

BATINSERT(TH)

V

− V

.

BATINSERT(TH)

BATINSERT(HYS)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

1

0

TSDN_M

0

R/W

This is the interrupt mask for an IC thermal shutdown fault.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

IBUSOCP_M

This is the interrupt mask for an IBUS over current event where the IBUSOCP thresh-

old is exceeded.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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29

FAN54161

INT1

Register Address = 03h

Default = 0000 0000

Bit

Name

Default

Type

Description

7

VBUSOVP_INT

0

R/CLR This interrupt bit is set when the VBUS voltage exceeds V

.

BUSOVP(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

6

5

4

3

2

IBUSREG_INT

0

R/CLR This interrupt bit is set when IBUS CC loop operates the switch in regulation mode to

limit I

to I

.

BUS

BUSREG(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VBATREG_INT

IBATREG_INT

VOREG_INT

R/CLR This interrupt bit is set when the VBAT CV loop is operating the switch in regulation

mode to limit (V

−V

SNSN

) to V

.

SNSP

BATREG(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

R/CLR This interrupt bit is set when the IBAT CC loop is operating the switch in regulation

mode to limit I

to I

.

BAT

BATREG(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

R/CLR This interrupt bit is set when the VOUT CV loop is operating the switch in regulation

mode to limit V

to V

.

OUT

OREG(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

TBUSOTP_INT

R/CLR This interrupt bit is set when the temperature of the T_BUS NTC thermistor has ex-

ceeded the T_BUS over temperature threshold. The ADC must have the TBUSOTP

channel active to trigger this interrupt.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

1

0

TBATOTP_INT

IBUSRCB_INT

0

R/CLR This interrupt bit is set when the temperature of the T_BAT NTC thermistor has ex-

ceeded the T_BAT over temperature threshold. The ADC must have the TBATOTP

channel active to trigger this interrupt.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

R/CLR This interrupt bit is set when the current from VOUT to VBUS exceeds I

.

RCB(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

INT2

Register Address = 04h

Default = 0000 0000

Bit

7

Name

Default

Type

Description

Reserved

0

Read

Reserved. Always reads 0.

6

ADCDONE_INT

R/CLR This interrupt bit is set when ADC conversion is complete in one−shot mode only

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

5

4

3

VDROPALM_INT

VDROPOVP_INT

VBUSINSERT_INT

0

R/CLR This interrupt bit is set when the VDROP voltages exceeds V

.

DROPALM(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

R/CLR This interrupt bit is set when the VDROP voltages exceeds V

.

DROPOVP(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

R/CLR This interrupt bit is set when the ADC is enabled and VBUS voltage rises above

V

or falls below V − V . This interrupt is edge

BUSUVLO(TH)

BUSUVLO(HYS)

triggered.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

2

VBATINSERT_INT

0

R/CLR This interrupt bit is set when the ADC is enabled and V rises above V

-

SNSP

BATIN

or falls below V

− V

. This interrupt is edge trig-

SERT(TH)

BATINSERT(TH)

BATINSERT(HYS)

gered.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

1

0

TSDN_INT

0

R/CLR This interrupt bit is set when the die temperature exceeds T

.

SDN(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

IBUSOCP_INT

R/CLR This interrupt bit is set when the IBUS current exceeds I

.

BUSOCP(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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30

FAN54161

PROTECT_EN

Register Address = 05h

Default = 1111 1110

Bit

Name

Default

Type

Description

7

VBUSOVP_EN

IBUSREG_EN

VBATREG_EN

IBATREG_EN

VOREG_EN

1

R/W

A 1 enables VBUS OVP protection.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

6

5

4

3

2

1

0

1

0

R/W

A 1 enables IBUS constant current regulation capability.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables VBAT constant voltage regulation capability.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables IBAT constant current regulation capability.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables VOUT constant voltage regulation capability.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

TBUSOTP_EN

TBATOTP_EN

VBUSPD_EN

A 1 enables T_BUS over temperature protection.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables T_BAT over temperature protection.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables an internal 100 Ohm pulldown resistor on VBUS.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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31

FAN54161

SW_CONTROL

Register Address = 06h

Default = 0010 1000

Description

A 1 enables the VDROP protection circuit. If this protection is enabled, the switch will

Bit

Name

Default

Type

7

VDROPOVP_EN

VDROPALM_EN

RSENSE

0

R/W

open whenever V −V > V for more than t .

BUS

OUT

DROPOVP(TH)

VDROPGLTCH

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

6

5

0

1

R/W

A 1 enables the VDROP alarm circuit. If this alarm is enabled, the IC will flag the host

that V −V has exceeded the V .

BUS

OUT

DROPALM(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

Program this bit according to the value of the external sense resistor across RSP and

RSN.

Code

RSENSE Value

5 mW

0

1

10 mW

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

4

SW_EN

WDT

0

R/W

A 1 enables the switch and hardware protection. This bit will automatically reset to 0

when the switch is opened due to a fault condition other than VBUS UVLO.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

3:2

10

This enables and sets the duration of the watch dog timer. When enabled, the

2

watchdog timer is reset by an I C read or write command to any register of the

FAN54161. A watchdog timer expiry opens the switch and generates an interrupt.

Code

00

WDT Setting

Disabled

0.5 sec

01

10

1.0 sec

11

2.0 sec

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

1

0

IRCB

0

R/W

This bit sets the reverse current blocking protection threshold. The direction of re-

verse current flow through the switch is from VOUT to VBUS.

Code

IRCB Threshold (mA)

0

1

100

3000

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

2

REG_RST

W1CLR Setting this bit will reset all I C control and interrupt register bits (except status) to

their default value. This bit is self−clear.

Code

Action

0

1

No Effect

2

Reset I C control and interrupt bits to default values

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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32

FAN54161

ADC_CONTROL

Register Address = 07h

Default = 1000 0111

Bit

Name

Default

Type

Description

7

ICTEMPADC_EN

1

R/W

A 1 enables the ADC measurement of the IC temperature.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

6

5

4

3

Reserved

ADC_EN

0

Read Reserved. Always reads 0.

R/W

A 1 enables the ADC.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

2

ADC_RATE

1

R/W

This bit controls the conversion mode of the ADC.

Code

ADC Mode

0

1

Single Conversion

Continuous Conversion

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

1

0

AVG_EN

1

R/W

A 1 enables ADC measurement averaging.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

SAMPLES

This bit sets the number of samples used for an ADC conversion if averaging is en-

abled.

Code

# of ADC Averaging Samples

0

1

8

16

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

ADC_CHANNEL

Register Address = 08h

Default = 1111 1111

Bit

Name

Default

Type

Description

7

VBUSADC_EN

1

R/W

A 1 enables ADC measurement of V

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

.

BUS

6

5

4

3

2

IBUSADC_EN

VOUTADC_EN

VDROPADC_EN

VBATADC_EN

IBATADC_EN

A 1 enables ADC measurement of I

.

BUS

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables ADC measurement of V

.

OUT

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables ADC measurement of V

.

DROP

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables ADC measurement of V via V and V

.

SNSN

BAT

SNSP

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables ADC measurement of I

SRN.

through the sense resistor across SRP and

BAT

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

1

0

TBUSADC_EN

TBATADC_EN

1

R/W

A 1 enables ADC measurement of T_BUS.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables ADC measurement of T_BAT.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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33

FAN54161

PROT_DELAY

Register Address = 09h

Default = 1010 0000

Bit

Name

Default

Type

Description

7:4

IBUSOCP_TH

1010

R/W

This sets the IBUS over current protection threshold. When IBUS rises above the IBUS

over protection threshold, the switch will open and an interrupt will be generated.

Code

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

IBUS OCP Threshold (A)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

3

2

1

Reserved

0

Read Reserved. Always reads 0.

IBUSOCP_MODE

R/W

This bit controls the IBUS over current protection mode of operation.

IBUS OCP

Deglitch

Time

IBUS OCP Response After

Over Current Fault

Code

0

Open switch and reset SW_EN = 0

50 ms

8 ms

1

Hiccup Mode (open switch and then at-

tempt to close switch every 100 ms up to

7 times before latching switch open if over

current fault still exists)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

This bit sets the deglitch time of the VBUS and VDROP over voltage protection circuits.

VDROP

0

OVP_DLY

0

R/W

VBUS OVP VDROP OVP

Alarm

Deglitch

Time (ms)

Deglitch

Time (ms)

Deglitch

Time (ms)

Code

0

4

1

20

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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34

FAN54161

VBUSOVP

Name

Register Address = 0Ah

Default = 0011 0100

Bit

7

Default

0

Type

Read

R/W

Description

Reserved

Reserved. Always reads 0.

6:0

VBUSOVP_TH

0110100

This sets the VBUS over voltage protection threshold. When VBUS rises above the

VBUS over protection threshold, the switch will open and an interrupt will be generated.

Code

0000000

0000001

0000010

−

VBUSOVP Threshold (V)

4.200

4.225

4.250

−

0110100

−

5.500

−

1011100 to 1111111

6.500

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VOREG

Register Address = 0Bh

Description

Default = 0001 0100

Bit

7

Name

Reserved

VOREG

Default

0

Type

Read

R/W

Reserved. Always reads 0.

6:0

0010100

This sets the VOREG regulation threshold of the VOUT CV loop. When VOUT rises to

the VOREG threshold, the switch will operate in regulation mode and limit VOUT to the

VOREG threshold.

Code

0000000

0000001

0000010

−

VOREG (V)

4.20

4.21

4.22

−

0010100

−

4.40

−

1001111

1010000 to 1111111

4.99

5.00

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VDROPOVP

Register Address = 0Ch

Description

Default = 0011 1100

Bit

Name

Default

Type

7:0 VDROPOVP_TH 00111100

R/W

This sets the VDROP over voltage protection threshold. When VDROP voltage rises

above the VDROP over voltage protection threshold, the switch will open and an inter-

rupt will be generated.

Code

0000 0000

0000 0001

0000 0010

0000 0011

−

VDROP OVP Threshold (V)

0

5

10

15

−

0011 1100

−

300

−

11000111

1100 1000 to 1111 1111

995

1000

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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35

FAN54161

VDROP_ALM

Register Address = 0Dh

Default = 0001 0100

Bit

Name

Default

Type

Description

7:0

VDROP_ALM

00010100

R/W

This sets the VDROP alarm threshold. When VDROP voltage rises above the VDROP

alarm threshold, an interrupt will be generated.

Code

0000 0000

0000 0001

0000 0010

−

VDROP Alarm Threshold (V)

0

5

10

−

0001 0100

−

100

−

1100 0111

1100 0000 to 1111 1111

995

1000

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VBATREG

Register Address = 0Eh

Description

Default = 0000 1011

Bit

7

Name

Default

0

Type

Read

R/W

Reserved

VBATREG

Reserved. Always reads 0.

This sets the VBATREG regulation threshold of the VBAT CV loop. When V

6:0

0001010

−

SNSP

V

rises to the VBATREG threshold, the switch will operate in regulation mode and

SNSN

limit V

−V

to the VBATREG threshold.

SNSP

SNSN

Code

VBATREG Threshold (V)

0000000

0000001

0000010

−

4.20

4.21

4.22

−

0001010

−

4.3

−

1001111

4.99

1010000 to 1111111

5.00

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

IBATREG

Register Address = 0Fh

Description

Default = 0010 1000

Bit

7

Name

Default

0

Type

Read

R/W

Reserved

IBATREG

Reserved. Always reads 0.

6:0

0101000

This sets the IBATREG regulation threshold of the IBAT CC loop. When the measured

IBAT current rises above the IBATREG threshold, the switch will operate in regula-

tion mode to limit the IBAT current to IBATREG. The IBAT current is sensed using the

SRP and SRN pins with an external R

resistor.

SENSE

Code

0000000

0000001

0000010

0000011

−

IBATREG Threshold (V)

0.10

0.15

−

0101000

−

2.00

−

1111101

1111110

1111111

6.25

6.30

6.35

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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36

FAN54161

IBUSREG

Register Address = 10h

Default = 0100 0110

Bit

Name

Default

Type

Description

7:0

IBUSREG

01000110

R/W

This sets the IBUSREG regulation threshold of the IBUS CC loop. When the measured

IBUS current rises above the IBUSREG threshold, the switch will operate in regula-

tion mode to limit the IBUS current to IBUSREG. The IBUS current is sensed internally

through the switch.

Code

0000 0000

0000 0001

0000 0010

0000 0011

−

IBUSREG Threshold (A)

0.10

0.15

−

0100 0110

−

3.50

−

1000 0000

1000 0001

1000 0010 to 1111 1111

6.40

6.45

6.50

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

TBUSOTP

Register Address = 11h

Description

Default = 0001 1110

Bit

7

Name

Default

0

Type

Read

R/W

Reserved

TBUS_TH

Reserved. Always reads 0.

6:0

0011110

This sets the T_BUS over temperature threshold. When the ADC measurement of the

T_BUS voltage falls below the T_BUS over temperature voltage threshold, the switch

will open and a VBUS connector over−temperature interrupt will be generated. An ex-

ternal NTC thermistor is used to measure the temperature of the VBUS connector.

T_BUS Over Temperature Threshold (V)

Code

0000 0000

0000 0001

0000 0010

−

0.0

0.02

0.04

−

0011110

0.60

−

1110111

2.38

2.40

1111000 to 1111 1111

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

TBATOTP

Register Address = 12h

Description

Default = 0010 0011

Bit

7

Name

Default

0

Type

Read

R/W

Reserved

TBAT_TH

Reserved. Always reads 0.

6:0

0100011

This sets the T_BAT over temperature threshold. When the ADC measurement of the

T_BAT voltage falls below the T_BAT over temperature voltage threshold, the switch

will open and a battery over−temperature interrupt will be generated. An external NTC

thermistor can be used to measure the temperature of the battery.

T_BAT Over Temperature Threshold (V)

Code

0000 0000

0000 0001

0000 0010

−

0.0

0.02

0.04

−

0100011

0.70

−

1110111

2.38

2.40

1111000 to 1111 1111

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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37

FAN54161

VBUS_MSB

Register Address = 13h

Default = 0000 0000

Bit

7

Name

Default

Type

Description

Reserved

0

Read Reserved. Always reads 0.

6

0

5

Reserved

4:0

VBUSADC_MSB

00000

Read VBUSADC_MSB along with VBUSADC_LSB form the 13 bit result of the VBUS volt-

age. When V < 300mV, VBUSADC will report 0V.

BUS

VBUSADC (b)

0000000000000

0000100101100

0000100101101

−

VBUSADC (h)

0000

VBUS (mV)

0 to 299

300

012C

012D

301

−

1011111010011

1011111010100

17D3

6099

6100

17D4

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VBUS_LSB

Register Address = 14h Default = 0000 0000

Bit

Name

Default

Type

Description

7:0

VBUSADC_LSB 00000000

Read

VBUSADC_LSB along with VBUSADC_MSB (REG 13h[4:0]) form the 13 bit result of

the VBUS voltage. When V < 300mV, VBUSADC will report 0V.

BUS

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

IBUS_MSB

Register Address = 15h Default = 0000 0000

Bit

7

Name

Reserved

Default

Type

Description

0

Read Reserved. Always reads 0.

6

Reserved

0

5

Reserved

4:0

IBUSADC_MSB

00000

Read IBUSADC_MSB along with IBUSADC_LSB form the 13 bit result of the IBUS current.

IBUSADC (b)

0000000000000

0000000000001

0000000000010

−

IBUSADC (h)

0000

IBUS (mA)

0

1

0001

0002

2

−

1101101010111

1101101011000

1B57

6999

7000

1B58

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

IBUS_LSB

Register Address = 16h Default = 0000 0000

Bit

Name

Default

Type

Description

7:0

IBUSADC_LSB 00000000

Read

IBUSADC_MSB along with IBUSADC_LSB (REG15h[4:0]) form the 13 bit result of the

IBUS current.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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38

FAN54161

VOUT_MSB

Register Address = 17h

Default = 0000 0000

Bit

7

Name

Default

Type

Description

Reserved

0

Read Reserved. Always reads 0.

6

0

5

Reserved

4:0

VOUTADC_MSB

00000

Read VOUTADC_MSB along with VOUTADC_LSB form the 13 bit result of the VOUT volt-

age.

VOUTADC (b)

0000000000000

0000000000001

0000000000010

−

VOUTADC (h)

0000

VOUT (mV)

0

1

0001

0002

2

−

1001110000111

1001110001000

1387

4999

5000

1388

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VOUT_LSB

Register Address = 18h Default = 0000 0000

Bit

Name

Default

Type

Description

7:0

VOUTADC_LSB 00000000

Read

VOUTADC_LSB along with VOUTADC_MSB (REG17h[4:0]) form the 13 bit result of

the VOUT voltage.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VDROP_MSB

Register Address = 19h

Default = 0000 0000

Bit

7

Name

Default

Type

Description

Reserved

0

Read Reserved. Always reads 0.

6

5

0

4

0

3

0

2

0

1:0 VDROPADC_MSB

00

Read VDROPADC_LSB along with VDROPADC_MSB form the 10 bit result of the VDROP

voltage = V − V

.

OUT

BUS

VDROPADC (b)

0000000000

0000000001

0000000010

−

VDROPADC (h)

VDROP (mV)

0000

0001

0002

−

0

1

2

−

1111100111

1111101000

3E7

3E8

999

1000

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VDROP_LSB

Name Default

7:0 VDROPADC_LSB 00000000

Register Address = 1Ah Default = 0000 0000

Bit

Type

Description

Read VDROPADC_LSB along with VDROPADC_MSB (REG19h[1:0]) form the 10 bit result

of the VDROP voltage = V − V

.

BUS

OUT

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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39

FAN54161

VBAT_MSB

Register Address = 1Bh

Default = 0000 0000

Bit

7

Name

Default

Type

Description

Reserved

0

Read Reserved. Always reads 0.

6

0

5

Reserved

4:0

VBATADC_MSB

00000

Read VBATADC_LSB along with VBATADC_MSB form the 13 bit result of the V

= V

BAT SNSP

− V

.

SNSN

VBATADC (b)

0000000000000

0000000000001

0000000000010

−

VBATADC (h)

0000

VBAT (mV)

0

1

0001

0002

2

−

1001110000111

1001110001000

1387

4999

5000

1388

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VBAT_LSB

Register Address = 1Ch Default = 0000 0000

Bit

Name

Default

Type

Description

7:0

VBATADC_LSB 00000000

Read

VBATADC_LSB along with VBATADC_MSB (REG1B[4:0]) form the 13 bit result of the

V

= V − V

.

BAT

SNSP

SNSN

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

IBAT_MSB

Register Address = 1Dh Default = 0000 0000

Bit

Name

Default

Type

Description

7

IBATADC_POL

0

Read Polarity of IBAT_ADC result.

0 − positive (+)

1 − negative (−)

6

5

Reserved

0

Read Reserved. Always reads 0.

4:0

IBATADC_MSB

00000

Read IBATADC_MSB along with IBATADC_LSB form the 13 bit ADC measurement of the

IBAT current measured through R

across SRP and SRN pins.

SENSE

IBUSADC (b)

0000000000000

0000000000001

0000000000010

−

IBUSADC (h)

0000

IBUS (mA)

0

1

0001

0002

2

−

1101101010111

1101101011000

1387

6999

7000

1388

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

IBAT_LSB

Register Address = 1Eh Default = 0000 0000

Bit

Name

Default

Type

Description

7:0

IBATADC_LSB

00000000

Read IBATADC_LSB along with IBATADC_MSB (REG1Dh[4:0]) form the 13 bit ADC mea-

surement of the IBAT current measured through R across SRP and SRN pins.

SENSE

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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40

FAN54161

TBUS_MSB

Register Address = 1Fh

Default = 0000 0000

Bit

7

Name

Default

Type

Description

Reserved

0

Read Reserved. Always reads 0.

6

5

Reserved

0

4

Reserved

0

3:0

TBUSADC_MSB

0000

Read TBUSADC_MSB along with TBUSADC_LSB form the raw bit ADC measurement of

the TS_BUS voltage formed by the external NTC thermistor network used to sense

the temperature of the input connector. A 2.4V external reference is recommended.

TBUSADC (b)

0000000000000

0000000000001

0000000000010

−

TBUSADC (h)

TBUS (mV)

0000

0001

0002

−

0

1

2

−

100101011111

100101100000

95F

960

2399

2400

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

TBUS_LSB

Register Address = 20h Default = 0000 0000

Bit

Name

Default

Type

Description

7:0

TBUSADC_LSB 00000000

Read TBUSADC_LSB along with TBUSADC_MSB (REG1Fh[3:0]) form the 12 bit result of

the TS_BUS voltage formed by the external NTC thermistor network used to sense

the temperature of the input connector. A 2.4V external reference is recommended.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

TBAT_MSB

Register Address = 21h

Default = 0000 0000

Bit

7

Name

Reserved

Default

Type

Description

0

Read Reserved. Always reads 0.

6

Reserved

5

Reserved

0

4

Reserved

0

3:0

TBATADC_MSB

0000

Read TBATADC_MSB along with TBATADC_LSB form the 12 bit result of the TS_BAT volt-

age formed by the external NTC thermistor network used to sense the temperature of

the battery. A 2.4V external reference is recommended.

TBATADC (b)

0000000000000

0000000000001

0000000000010

−

TBATADC (h)

TBAT (mV)

0000

0001

0002

−

0

1

2

−

100101011111

100101100000

95F

960

2399

2400

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

TBAT_LSB

Register Address = 22h Default = 0000 0000

Bit

Name

Default

Type

Description

7:0

TBATADC_LSB

00000000

Read TBATADC_LSB along with TBATADC_MSB (reg21h[3:0]) form the 12 bit result of the

TS_BAT voltage formed by the external NTC thermistor network used to sense the

temperature of the battery. A 2.4V external reference is recommended.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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41

FAN54161

ICTEMP_LSB

Register Address = 23h

Default = 0000 0000

Bit

Name

Default

Type

Description

7:0

ICTEMPADC

00000000

Read ICTEMPADC forms the 8 bit result of the IC’s internal die temperature sensor.

ICTEMPADC (b)

00000000

−

ICTEMPADC (h)

ICTEMP (5C)

0

−

00011001

00011010

00011011

−

19

1A

1B

−

25

26

27

−

10010101

10010110

95

96

149

150

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

CONTROL1

Register Address = 50h Default = 0100 0011

Bit

Name

Default

Type

Description

7:6

TJSHDN

01

R/W

TJSHDN programs the thermal shutdown threshold.

Junction

Temperature

Threshold (5C)

Code

00

01

10

11

115

125

135

145

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

5

4

Reserved

0

Read

R/W

Reserved

VOUTOVP_DLY

This bit sets the deglitch time of the VOUT over voltage protection circuit.

VOUT OVP

Deglitch Time (mS)

Code

00

4

01

20

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

3

2

VOUTOVP_EN

VFAIL_EN

0

R/W

A 1 enables the VOUT OVP protection circuit. If enabled and VOUT > VOUTOVP, the

switch is forced open.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 enables a detection mechanism that senses if the bypass switch is permanently

shorted.

RESET_N falling; REG_RST=1; Watchdog Timer Expiry

1

0

IBUSRCB_EN

IBUSOCP_EN

1

R/W

A 1 (default setting) enables IBUS reverse current blocking protection.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 (default setting) enables the IBUS over current protection circuit that is set by a

programmable IBUSOCP threshold.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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42

FAN54161

CONTROL2

Register Address = 51h

Default = 0001 0100

Bit

7

Name

Default

0

Type

Read Reserved. Always reads 0.

Description

Reserved

6:0

VOUTOVP_TH

0010100

R/W

This sets the VOUT OVP threshold. When VOUT rises above its OVP threshold, the

switch will open.

VOUT OVP

Threshold (V)

Code

0000000

0000001

0000010

−

4.50

4.51

4.52

−

0010100

−

4.70

−

1001111

1010000 to 1111111

5.29

5.30

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

INT3 MASK

Register Address = 52h Default = 0000 0001

Bit

7

Name

Reserved

VOUTOVP_M

Default

Type

Description

0

Read Reserved. Always reads 0.

6

5

4

3

R/W

A 1 sets the interrupt mask for a VOUT OVP fault.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

2

1

0

VFAIL_M

0

1

A 1 sets the interrupt mask for a VFAIL fault.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VUSBOVP_M

VUSBINSERT_M

A 1 sets the interrupt mask for a VUSBOVP fault.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

A 1 (default setting) sets the interrupt mask for a VUSB insertion or removal event.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

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43

FAN54161

INT3

Register Address = 53h

Default = 0000 0000

Bit

7

Name

Default

Type

Read

Description

Reserved

0

Reserved. Always reads 0.

6

5

4

TIMER_INT

VOUTOVP_INT

VFAIL_INT

R/CLR This interrupt is set when the watchdog timer has expired.

Reset condition: RESET_N falling; REG_RST=1

3

2

0

R/CLR This interrupt is set when VOUT exceeds V

.

OUTOVP(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

R/CLR This interrupt is set when the common source voltage of the bypass switch is above

the V

threshold when the switch is open (SW_EN=0). A “1” would indicate that

FAIL

the bypass switch has failed and the host processor should flag the user to service

the device.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

1

0

VUSBOVP_INT

0

R/CLR This interrupt is set when V

exceeds the V

threshold.

USB

USBOVP

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

R/CLR This interrupt is set when V rises above V or falls below V -

USBU

VUSBINSERT_INT

USB

USBUVLO(TH)

− V

. When an external OVP blocking FET is not used, the

VLO(TH)

USBUVLO(HYS)

floating VUSB pin can still exceed the V

threshold during a VBUS OVP

USBUVLO(TH)

event causing a false VUSBINSERT interrupt. It is recommended to mask this bit

when no external FET is used to prevent the INT pin from pulling low due to a VBUS

OVP event. Masking this bit does not prevent it from being set, so this bit should be

ignored when an external OVP blocking FET is not used.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

STATUS1

Name

Register Address = 54h

Default = 0000 0100

Bit

Default

Type

Description

7

VOREG_ST

0

Read A 1 indicates that the VOREG CV regulation loop is active.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

6

5

4

3

VBATREG_ST

IBATREG_ST

0

Read A 1 indicates that the VBATREG CV regulation loop is active

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

Read A 1 indicates that the IBATREG CC regulation loop is active.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

IBUSREG_ST

Read A 1 indicates that the IBUSREG CC regulation loop is active.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

VBUSINSERT_ST

Read A 1 indicates that V

is above V . When the switch is open (SW_EN=0)

BUSUVLO(TH)

BUS

and the ADC is disabled (ADC_EN=0), this bit is latched to 0 regardless if there is a

valid source on VBUS.

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

2

VBATINSERT_ST

1

Read A 1 indicates that V

is above V

.

SNSP

BATINSERT(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

1

0

Reserved

0

Read Reserved. Always reads 0.

VUSBINSERT_ST

Read A 1 indicates that V

is above V

.

USB

USBUVLO(TH)

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com

44

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP42 2.78x3.06x0.65

CASE 567TY

ISSUE O

DATE 31 MAR 2017

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON13337G

WLCSP42 2.78x3.06x0.65

PAGE 1 OF 1

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型号：	FAN54161UCX
厂家：	ONSEMI
描述：	Battery Charge Controller, Direct, 6 A, with Advanced Safety Monitoring 电池监控
文件：	总46页 (文件大小：1157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN54161UCX [ONSEMI]

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