FAN4868UC33X [ONSEMI]
3 MHz, Synchronous Regulator;
| 型号： | FAN4868UC33X |
| 厂家： | 
ONSEMI |
| 描述： | 3 MHz, Synchronous Regulator |
| 文件： | 总12页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAN4868
3 MHz, Synchronous
TinyBoost) Regulator
Description
The FAN4868 is a low−power boost regulator designed to provide a
regulated 3.3 V output from a single cell Lithium or Li−Ion battery.
Output voltage options are fixed at 3.3 V with a guaranteed maximum
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SCALE 4:1
load current of 200 mA at V = 2.3 V and 300 mA at V = 3.3 V.
IN
IN
Input current in Shutdown Mode is less than 1 μA, which maximizes
battery life.
Light−load PFM operation is automatic and “glitch−free”. The
regulator maintains output regulation at no−load with as low as 37 μA
quiescent current.
The combination of built−in power transistors, synchronous
rectification, and low supply current make the FAN4868 ideal for
battery powered applications.
WLCSP6 0.88 x 1.23 x 0.458
CASE 567VM
The FAN4868 is available in 6−bump 0.4 mm pitch Wafer−Level
Chip Scale Package (WLCSP).
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Features
• Operates with Few External Components:
1 μH Inductor and 0402 Case Size Input and Output Capacitors
• Input Voltage Range from 2.3 V to 3.2 V
TYPICAL APPLICATION
V
IN
• Fixed 3.3 V Output Voltage Options
C
2.2 μF
IN
• Maximum Load Current >150 mA at V = 2.3 V
IN
• Maximum Load Current 300 mA at V = 2.7 V, V
= 3.3 V
IN
OUT
VIN
GND
VOUT
FB
A1 A2
• Up to 92% Efficient
L1
SW
EN
• Low Operating Quiescent Current
• True Load Disconnect During Shutdown
B2
C2
B1
C1
1 μH
C
OUT
• Variable On−time Pulse Frequency Modulation (PFM) with
Light−Load Power−Saving Mode
4.7 μF
• Internal Synchronous Rectifier
(No External Diode Needed)
• Thermal Shutdown and Overload Protection
• 6−Bump WLCSP, 0.4 mm Pitch
Applications
• Powering 3.3 V Core Rails
• PDAs, Portable Media Players
• Cell Phones, Smart Phones, Portable Instruments
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
October, 2018 − Rev. 3
FAN4868/D
FAN4868
Table 1. ORDERING INFORMATION
Part Number
Operating Temperature Range
Package
WLCSP, 0.4 mm Pitch
Packing Method
FAN4868UC33X
−40°C to 85°C
Tape and Reel
BLOCK DIAGRAMS
Q3
L1
SW
VOUT
Q2
VIN
V
IN
Q1
Synchronous
Rectifier
C
IN
Control
GND
EN
FB
ModulatorLogic
andControl
C
OUT
Figure 1. IC Block Diagram
PIN CONFIGURATIONS
A1
A2
B2
C2
A2
B2
A1
B1
VIN
SW
EN
GND
GND
VOUT
FB
VIN
SW
EN
B1
C1
VOUT
FB
C2 C1
Figure 2. WLCSP (Top View)
Figure 3. WLCSP (Bottom View)
Table 2. PIN DEFINITIONS
Pin #
WLCSP
A1
Name
VIN
Description
Input Voltage. Connect to Li−Ion battery input power source and input capacitor (C
Switching Node. Connect to inductor
)
IN
B1
SW
C1
EN
Enable. When this pin is HIGH, the circuit is enabled. This pin should not be left floating
Feedback. Output voltage sense point for V . Connect to output capacitor (C
C2
FB
)
OUT
OUT
B2
VOUT
GND
Output Voltage. This pin is both the output voltage terminal as well as an IC bias supply
A2
Ground. Power and signal ground reference for the IC. All voltages are measured with
respect to this pin
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2
FAN4868
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
−0.3
–2
Max.
Units
5.5
V
IN
VIN Pin
V
6
V
OUT
VOUT Pin
FB Pin
V
V
V
–2
6
V
FB
−0.3
−1.0
−0.3
5.5
6.5
5.5
V
SW
SW Node
DC
Transient: 10 ns, 3 MHz
EN Pin
V
V
EN
ESD
Electrostatic Discharge Protection Level
Human Body Model per JESD22−A114
2
1
kV
Charged Device Model per
JESD22−C101
T
Junction Temperature
–40
–65
+150
+150
+260
°C
°C
°C
J
T
Storage Temperature
STG
T
L
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
Max.
3.2
Units
V
V
IN
Supply Voltage
Output Current
3.3 V
2.3
OUT
I
200
mA
°C
OUT
T
A
Ambient Temperature
Junction Temperature
–40
–40
+85
+125
T
J
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 5. THERMAL PROPERTIES
Symbol
Parameter
Typical
Units
θ
JA
Junction−to−Ambient Thermal Resistance
WLCSP
130
°C/W
1. Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p boards
in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature T at a given ambient
J(max)
temperate T .
A
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3
FAN4868
Table 6. ELECTRICAL SPECIFICATIONS
Minimum and maximum values are at V = V = 2.3 V to 4.5 V (2.5 to 3.2 V for 3.3 V
option), T = −40°C to +85°C; circuit of
A
IN
EN
IN
OUT
Typical Application, unless otherwise noted. Typical values are at T = 25°C, and V = V = 2.7 V for V
= 3.3 V.
A
IN
EN
OUT
Symbol
Parameter
Input Current 3.3 V
Conditions
Min
Typ
Max
65
Units
I
IN
V
Quiescent: V = 2.7 V, I
= 0, EN = V
IN
50
0.5
10
μA
IN
OUT
IN
OUT
Shutdown: EN = 0, V = 2.7 V
1.5
IN
I
V
OUT
Leakage Current
V
= 0, EN = 0, V ≥ 3 V
nA
μA
V
LK_OUT
OUT
IN
I
V
to V Reverse Leakage
V
= 3.3 V, V = 3.0 V, EN = 0
2.5
2.3
LK_RVSR
OUT
IN
OUT
IN
V
Under−Voltage Lockout
V
IN
Rising
2.2
UVLO
UVLO_HYS
V
Under−Voltage Lockout
190
mV
Hysteresis
V
Enable HIGH Voltage
Enable LOW Voltage
1.05
3.17
V
V
ENH
V
0.4
ENL
I
Enable Input Leakage Current
0.01
3.33
1.00
3.41
μA
V
LK_EN
V
OUT
Output Voltage
Accuracy
3.3 V
V
IN
from 2.5 V to 3.2 V, I
≤ 200 mA
OUT
OUT
(Note 2)
v
Reference Accuracy
Off Time
Referred to V
= 3.3 V
3.280
240
250
300
650
3.330
290
3.380
350
V
ref
OUT
t
V
IN
= 2.7 V, V
= 3.3 V, I = 200 mA
OUT
ns
OFF
OUT
OUT
I
Maximum Output
3.3 V
V
= 2.5 V
= 2.7 V
mA
OUT
IN
IN
Current
(Note 2)
V
I
SW Peak Current
Limit
3.3 V
3.3 V
V
V
= 2.7 V, V
> V
< V
800
700
950
750
mA
mA
SW
OUT
IN
OUT
IN
I
SS
Soft−Start Input
Peak Current
Limit
= 2.7 V, V
OUT
IN
OUT
IN
(Note 3)
t
SS
Soft−Start Time
3.3 V
V
IN
= 2.7 V, I = 200 mA
OUT
250
μs
OUT
(Note 4)
R
N−Channel Boost Switch
P−Channel Sync Rectifier
Thermal Shutdown
V
V
= 3.6 V
= 3.6 V
= 10 mA
300
400
150
30
mΩ
DS(ON)
IN
IN
T
I
°C
°C
TSD
LOAD
T
Thermal Shutdown Hysteresis
TSD_HYS
2. I
from 0 to I
; also includes load transient response. VOUT measured from mid−point of output voltage ripple.
LOAD
OUT
Effective capacitance of C
> 1.5 μF.
OUT
3. Guaranteed by design and characterization; not tested in production.
4. Elapsed time from rising EN until regulated V
.
OUT
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4
FAN4868
3.3 V
TYPICAL CHARACTERISTICS
OUT
Unless otherwise specified; circuit per Typical Application, 3.0 V , and T = 25°C.
IN
A
100
95
90
85
80
75
98
95
92
89
86
83
2.5 Vin
2.7 Vin
3.0 Vin
3.2 Vin
−40°C
+25°C
+85°C
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Load Current (mA)
Load Current (mA)
Figure 4. Efficiency vs. VIN
Figure 5. Efficiency vs. Temperature, 3.0 VIN
40
20
40
20
0
2.5 Vin
2.7 Vin
3.0 Vin
3.2 Vin
−40°C
+25°C
+85°C
0
−20
−40
−20
−40
−60
−80
−60
−80
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Load Current (mA)
Load Current (mA)
Figure 6. Line and Load Regulation
Figure 7. Load Regulation vs. Temperature,
3.0 VIN
55
50
45
40
35
30
700
600
500
400
300
200
−40°C
−40°C
+25°C
+85°C
+25°C
+85°C
2.0
2.3
2.6
2.9
3.2
3.5
2.0
2.3
2.6
2.9
3.2
3.5
Input Voltage(V)
Input Voltage(V)
Figure 8. Quiescent Current
Figure 9. Maximum DC Load Current
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FAN4868
3.3 V
TYPICAL CHARACTERISTICS (continued)
OUT
Unless otherwise specified; circuit per Typical Application, 3.0 V , and T = 25°C.
IN
A
Figure 10. Output Ripple, 10 mA PFM Load
Figure 11. Output Ripple, 200 mA PWM Load
Figure 12. Startup, No Load
Figure 13. Startup, 22 ꢀ Load
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FAN4868
FUNCTIONAL DESCRIPTION
Circuit Description
PFM Mode
If V > V when the minimum off−time has ended,
The FAN4868 is a synchronous boost regulator, typically
operating at 3 MHz in Continuous Conduction Mode
(CCM), which occurs at moderate to heavy load current and
OUT
REF
the regulator enters PFM Mode. Boost pulses are inhibited
until V < V . The minimum on−time is increased to
OUT
REF
low V voltages.
enable the output to pump up sufficiently with each PFM
boost pulse. Therefore, the regulator behaves like a constant
on−time regulator, with the bottom of its output voltage
ripple at 5.05 V in PFM Mode.
IN
At light−load currents, the converter switches
automatically to power−saving PFM Mode. The regulator
automatically and smoothly transitions between
quasi−fixed−frequency continuous conduction PWM Mode
and variable−frequency PFM Mode to maintain the highest
possible efficiency over the full range of load current and
input voltage.
Table 7. OPERATING STATES
Mode
LIN
Description
Linear Startup
Boost Soft−Start
Invoked When:
> V
V
IN
OUT
PWM Mode Regulation
The FAN4868 uses a minimum on−time and computed
minimum off−time to regulate V . The regulator achieves
excellent transient response by employing current mode
modulation. This technique causes the regulator output to
exhibit a load line. During PWM Mode, the output voltage
drops slightly as the input current rises. With a constant V ,
this appears as a constant output resistance.
SS
V
< V
OUT
OUT
REG
Boost Operating
Mode
BST
V
= V
OUT
REG
Shutdown and Startup
If EN is LOW, all bias circuits are off and the regulator is
in Shutdown Mode. During shutdown, true load disconnect
IN
between battery and load prevents current flow from V to
IN
The “droop” caused by the output resistance when a load
is applied allows the regulator to respond smoothly to load
transients with negligible overshoot.
V , as well as reverse flow from V to V .
OUT OUT IN
LIN State
When EN rises, if V > UVLO, the regulator first
IN
700
attempts to bring V
within about 1V of V by using the
OUT
IN
V
V
OUT
OUT
3.3
5.0
internal fixed current source from V (I ). The current
IN LIN1
600
500
400
300
200
100
is limited to about 630 mA during LIN1 Mode.
If V
reaches V −1V during LIN1 Mode, the SS state
OUT
IN
is initiated. Otherwise, LIN1 times out after 16 clock counts
and the LIN2 Mode is entered.
In LIN2 Mode, the current source is incremented to
850 mA. If V
fails to reach V −1 V after 64 clock
OUT
IN
counts, a fault condition is declared.
SS State
Upon the successful completion of the LIN state (V
>
OUT
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
− 1 V), the regulator begins switching with boost pulses
IN
Input Voltage (V)
current limited to about 50% of nominal level, incrementing
to full scale over a period of 32 clock counts.
If the output fails to achieve 90% of its set point within 96
clock counts at full−scale current limit, a fault condition is
declared.
Figure 14. Output Resistance (ROUT
)
When the regulator is in PWM CCM Mode and the target
OUT
V
= 5.05 V, V
is a function of I and can be
OUT
LOAD
computed as:
BST State
This is the normal operating mode of the regulator. The
VOUT + 5.05 * ROUT ILOAD
(eq. 1)
regulator uses a minimum t −minimum t modulation
OFF
ON
For example, at V = 3.3 V, and I
= 200 mA, V
OUT
IN
LOAD
scheme. Minimum t
is proportional to V / V
,
OFF
IN
OUT
drops to:
which keeps the regulator’s switching frequency reasonably
constant in CCM. t is proportional to V and is
(eq. 1A)
VOUT + 5.05 * 0.38 0.2 + 4.974 V
ON(MIN)
IN
higher if the inductor current reaches 0 before t
during the prior cycle.
OFF(MIN)
At V = 2.3 V, and I
= 200 mA, V
drops to:
IN
LOAD
OUT
VOUT + 5.05 * 0.68 0.2 + 4.914 V
(eq. 1B)
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FAN4868
To ensure that V
does not pump significantly above
The V −dependent LIN Mode charging current is
OUT
IN
the regulation point, the boost switch remains off as long as
FB > V
illustrated in Figure 17.
.
REF
Fault State
The regulator enters the FAULT state under any of the
following conditions:
• V
fails to achieve the voltage required to advance
from LIN state to SS state
OUT
• V
fails to achieve the voltage required to advance
from SS state to BST state
OUT
• Sustained (32 CLK counts) pulse−by−pulse current
limit during the BST state
• The regulator moves from BST to LIN state due to a
short circuit or output overload (V
< V −1 V)
IN
OUT
Once a fault is triggered, the regulator stops switching and
Figure 17. LIN Mode Current vs. VIN
presents a high−impedance path between V and V
.
IN
OUT
After waiting 480 CLK counts, a restart is attempted.
Over−Temperature Protection (OTP)
Soft−Start and Fault Timing
The soft−start timing for each state, and the fault times, are
determined by the fault clock, whose period is inversely
The regulator shuts down when the thermal shutdown
threshold is reached. Restart, with soft−start, occurs when
the IC has cooled by about 30°C.
proportional to V . This allows the regulator more time to
IN
Over−Current Protection (OCP)
During Boost Mode, the FAN4868 employs
charge larger values of C
when V is lower. With higher
OUT
IN
a
V , this also reduces power delivered to V
during each
IN
OUT
cycle−by−cycle peak current limit to protect switching
elements. Sustained current limit, for 32 consecutive fault
clock counts, initiates a fault condition.
cycle in current limit.
0 V
VOUT
During an overload condition, as V
collapses to
OUT
16
64
480
approximately V -1 V, the synchronous rectifier is
IN
ILIN2
ILIN1
immediately switched off and a fault condition is declared.
Automatic restart occurs once the overload/short is
removed and the fault timer completes counting.
0
8
EN
Figure 15. Fault Response into Short Circuit
The fault clock period as a function of V is shown in
IN
Figure 16.
Figure 16. Fault Clock Period vs. VIN
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FAN4868
APPLICATION INFORMATION
External Component Selection
Table 8 shows the recommended external components for
the FAN4868:
C
varies with manufacturer, dielectric material, case
EFF
size, and temperature. Some manufacturers may be able to
provide an X5R capacitor in 0402 case size that retains C
EFF
> 1.5 μF with 5 V bias; others may not. If this C
be economically obtained and 0402 case size is required, the
IC can work with the 0402 capacitor as long as the minimum
cannot
EFF
Table 8. EXTERNAL COMPONENTS
REF
Description
Manufacturer
L1
1.0 μH, 0.8 A,
190 mΩ, 0805
Murata
LQM21PN1R0MC0,
or equivalent
V
IN
is restricted to > 2.7 V.
For best performance, a 10 V−rated 0603 output capacitor
is recommended (Kemet C0603C475K8PAC, or
equivalent). Since it retains greater C under bias and over
C
2.2 μF, 6.3 V, X5R, 0402 Murata
GRM155R60J225M
IN
EFF
temperature, output ripple can is reduced and transient
capability enhanced.
TDK C1005X5R0J225M
C
4.7 μF, 10 V, X5R, 0603
Kemet
C0603C475K8PAC
OUT
Output Voltage Ripple
(Note 5)
Output voltage ripple is inversely proportional to C
.
OUT
TDK C1608X5R1A475K
During t , when the boost switch is on, all load current is
ON
5. A 6.3 V−rated 0603 capacitor may be used for C
, such as
OUT
supplied by C
.
OUT
Murata GRM188R60J225M. All datasheet parameters are valid
with the 6.3 V−rated capacitor. Due to DC bias effects, the 10 V
capacitor offers a performance enhancement; particularly output
ripple and transient response, without any size increase.
lLOAD
COUT
VRIPPLE(P*P) + tON
(eq. 2)
(eq. 3)
(eq. 4)
and
Output Capacitance (C
Stability
)
OUT
VIN
VOUT
tON + tSW D + tSW (1 *
)
Therefore:
The effective capacitance (C ) of small, high−value,
EFF
ceramic capacitors decrease as their bias voltage increases,
as shown in Figure 18.
ILOAD
COUT
VIN
VOUT
VRIPPLE(P*P) + tSW (1 *
)
Where:
1
fSW
tSW
+
(eq. 5)
As can be seen from Equation 4, the maximum V
RIPPLE
occurs when V is minimum and I
is maximum.
IN
LOAD
Startup
Input current limiting is in effect during soft−start, which
limits the current available to charge C . If the output
OUT
fails to achieve regulation within the time period described
in the soft−start section above; a FAULT occurs, causing the
circuit to shut down, then restart after a significant time
period. If C
is a very high value, the circuit may not start
OUT
on the first attempt, but eventually achieves regulation if no
load is present. If a high−current load and high capacitance
are both present during soft−start, the circuit may fail to
achieve regulation and continually attempt soft−start, only
Figure 18. CEFF for 4.7 ꢁ F, 0603, X5R, 6.3 V
(Murata GRM188R60J475K)
to have C
state.
discharged by the load when in the FAULT
OUT
FAN4868 is guaranteed for stable operation with the
minimum value of C
(C ) outlined in Table 9.
EFF(MIN)
EFF
The circuit can start with higher values of C
under full
OUT
load if V is higher, since:
IN
Table 9. MINIMUM CEFF REQUIRED FOR STABILITY
Operating Conditions
I
VIN
VOUT
IOUT + (ILIM(PK)
*
RIPPLE)
(eq. 6)
2
Generally, the limitation occurs in BST Mode.
The FAN4868 starts on the first pass (without triggering
a FAULT) under the following conditions for C
V
(V)
I
(mA)
C
(ꢁF)
IN
LOAD
EFF(MIN)
2.3 to 4.5
2.7 to 4.5
2.3 to 4.5
0 to 200
0 to 200
0 to 150
1.5
:
EFF(MAX)
1.0
1.0
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FAN4868
The FAN4868 includes a circuit to detect a missing or
defective D1 by comparing V to FB. If V – FB >
about 0.7 V, the IC shuts down. The IC remains shut down
Table 10. MAXIMUM CEFF FOR FIRST−PASS
OUT
OUT
STARTUP
Operating Conditions
until V
< UVLO and V < UVLO + 0.7 or EN is
OUT
IN
R
(ꢀ)
LOAD(MIN)
toggled.
3.3 V
V
IN
(V)
C
(ꢁF)
OUT
EFF(MAX)
C
OUT2
may be necessary to preserve load transient
> 2.3
> 2.7
> 2.7
16
16
20
10
response when the Schottky is used. When a load is applied
at the FB pin, the forward voltage of the D1 rapidly increases
before the regulator can respond or the inductor current can
change. This causes an immediate drop of up to 300 mV,
15
22
depending on D1’s characteristics if C
supplies instantaneous current to the load while the regulator
adjusts the inductor current. A value of at least half of the
is absent. C
OUT2
OUT2
C
values shown in Table 10 typically apply to the
EFF
lowest V . The presence of higher V enhances ability to
start into larger C
IN
IN
at full load.
EFF
minimum value of C
should be used for C
. C
OUT
OUT2 OUT2
needs to withstand the maximum voltage at the FB pin as the
TVS is clamping.
The maximum DC output current available is reduced
with this circuit, due to the additional dissipation of D1.
Transient Protection
To protect against external voltage transients caused by
ESD discharge events, or improper external connections,
some applications employ an external transient voltage
suppressor (TVS) and Schottky diode (D1 in Figure 19).
LAYOUT GUIDELINE
C
2.2 μF
IN
V
IN
C
OUT
4.7 μF
D1
L1
1 μH
VIN
SW
EN
GND
VOUT
FB
A1 A2
Connector
B2
C2
B1
C1
C
OUT2
Figure 19. FAN4868 with External
Transient Protection
The TVS is designed to clamp the FB line (system V
)
OUT
to +10 V or –2 V during external transient events. The
Schottky diode protects the output devices from the positive
excursion. The FB pin can tolerate up to 14 V of positive
excursion, while both the FB and VOUT pins can tolerate
negative voltages.
Figure 20. WLCSP Suggested Layout (Top View)
Tinyboost is registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP6 0.88x1.23x0.458
CASE 567VM
ISSUE O
SCALE 4:1
DATE 28 NOV 2017
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DOCUMENT NUMBER:
DESCRIPTION:
98AON79926G
WLCSP6 0.88x1.23x0.458
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