FAN3213TMX [ONSEMI]
TTL 输入,双反向输出,峰值 5A 汲电流,5A 源电流,低压侧门极驱动器;型号: | FAN3213TMX |
厂家: | ONSEMI |
描述: | TTL 输入,双反向输出,峰值 5A 汲电流,5A 源电流,低压侧门极驱动器 驱动 光电二极管 接口集成电路 驱动器 |
文件: | 总17页 (文件大小:1084K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Dual-4 A, High-Speed,
Low-Side Gate Drivers
FAN3213, FAN3214
Description
The FAN3213 and FAN3214 dual 4 A gate drivers are designed to
drive N−channel enhancement−mode MOSFETs in low−side
switching applications by providing high peak current pulses during
the short switching intervals. They are both available with TTL input
thresholds. Internal circuitry provides an under−voltage lockout
function by holding the output LOW until the supply voltage is within
the operating range. In addition, the drivers feature matched internal
propagation delays between A and B channels for applications
requiring dual gate drives with critical timing, such as synchronous
rectifiers. This also enables connecting two drivers in parallel to
effectively double the current capability driving a single MOSFET.
The FAN3213/14 drivers incorporate MillerDrivet architecture for
the final output stage. This bipolar−MOSFET combination provides
high current during the Miller plateau stage of the MOSFET
turn−on/turn−off process to minimize switching loss, while providing
rail−to−rail voltage swing and reverse current capability.
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8
1
SOIC8
CASE 751EB
MARKING DIAGRAM
8
321xT
ALYWG
G
The FAN3213 offers two inverting drivers and the FAN3214 offers
two non−inverting drivers. Both are offered in a standard 8−pin SOIC
package.
1
A
L
YW
G
= Assembly Location
= Wafer Lot
= Assembly Start Week
= Pb−Free Package
Features
• Industry−Standard Pin Out
• 4.5 to 18 V Operating Range
(Note: Microdot may be in either location)
• 5 A Peak Sink/Source at V = 12 V
DD
• 4.3 A Sink/2.8 A Source at V
• TTL Input Thresholds
= 6 V
OUT
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of
this data sheet.
• Two Versions of Dual Independent Drivers:
♦ Dual Inverting (FAN3213)
♦ Dual Non−Inverting (FAN3214)
• Internal Resistors Turn Driver Off if No Inputs
• Miller Drive Technology
• 12 ns/9 ns Typical Rise/Fall Times with 2.2 nF Load
• Typical Propagation Delay Under 20 ns Matched within 1 ns to
the Other Channel
• Double Current Capability by Paralleling Channels
• Standard SOIC−8 Package
• Rated from –40°C to +125°C Ambient
• These are Pb−Free Devices
Applications
• Switch−Mode Power Supplies
• High−Efficiency MOSFET Switching
• Synchronous Rectifier Circuits
• DC−to−DC Converters
• Motor Control
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
April, 2020 − Rev. 3
FAN3214/D
FAN3213, FAN3214
PIN CONFIGURATIONS
NC
1
8
NC
1
8
NC
NC
2
3
4
7
6
5
OUTA
VDD
2
3
4
7
6
5
OUTA
VDD
INA
GND
INB
A
INA
GND
INB
A
OUTB
OUTB
B
B
FAN3213
FAN3214
Figure 1. Pin Configurations
PACKAGE OUTLINES
1
2
3
4
8
7
6
5
Figure 2. SOIC−8 (Top View)
THERMAL CHARACTERISTICS (Note 1)
Q
JL
Q
JT
Q
JA
Y
JB
Y
JT
(Note 2)
(Note 3)
(Note 4)
(Note 5)
(Note 6)
Package
Unit
8−Pin Small Outline Integrated Circuit (SOIC)
38
29
87
41
2.3
°C/W
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (Q ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)
JL
that are typically soldered to a PCB.
3. Theta_JT (Q ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform
JT
temperature by a top−side heatsink.
4. Theta_JA (Q ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given
JA
is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51−2, JESD51−5, and JESD51−7,
as appropriate.
5. Psi_JB (Y ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application
JB
circuit board reference point for the thermal environment defined in Note 4. For the MLP−8 package, the board reference is defined as the
PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC−8 package, the board reference
is defined as the PCB copper adjacent to pin 6.
6. Psi_JT (Y ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of
JT
the top of the package for the thermal environment defined in Note 4.
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FAN3213, FAN3214
PIN DEFINITIONS
Pin
1
Name
NC
Description
No Connect. This pin can be grounded or left floating.
Input to Channel A.
2
INA
3
GND
INB
Ground. Common ground reference for input and output circuits.
Input to Channel B.
4
5
OUTB
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and V is above
DD
UVLO threshold.
5
6
7
OUTB
VDD
Gate Drive Output B: Held LOW unless required input(s) are present and V is above UVLO threshold.
DD
Supply Voltage. Provides power to the IC.
OUTA
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V is above
DD
UVLO threshold.
7
8
OUTA
NC
Gate Drive Output A: Held LOW unless required input(s) are present and V is above UVLO threshold.
DD
No Connect. This pin can be grounded or left floating.
NC
1
8
NC
1
8
NC
NC
2
3
4
7
6
5
OUTA
VDD
2
3
4
7
6
5
OUTA
VDD
INA
GND
INB
A
INA
GND
INB
A
OUTB
OUTB
B
B
FAN3213
FAN3214
Figure 3. Pin Configurations (Repeated)
OUTPUT LOGIC
FAN3213 (x = A or B)
FAN3214 (x = A or B)
INx
0
OUTx
INx
0 (Note 7)
1
OUTx
1
0
0
1
1 (Note 7)
7. Default input signal if no external connection is made.
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FAN3213, FAN3214
BLOCK DIAGRAMS
NC
1
2
8
NC
INA
7
6
OUTA
VDD
100 kW
100 kW
UVLO
GND
INB
3
4
VDD_OK
5
OUTB
100 kW
100 kW
Figure 4. FAN3213 Block Diagram
NC
1
8
NC
INA
2
3
7
6
OUTA
VDD
100 kW
100 kW
UVLO
GND
INB
VDD_OK
4
5
OUTB
100 kW
100 kW
Figure 5. FAN3214 Block Diagram
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4
FAN3213, FAN3214
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
Max
Unit
V
V
DD
VDD to GND
20.0
V
INA and INB to GND
OUTA and OUTB to GND
GND − 0.3
GND − 0.3
−
V
V
+ 0.3
V
IN
DD
DD
V
OUT
+ 0.3
V
T
Lead Soldering Temperature (10 Seconds)
Junction Temperature
+260
°C
°C
°C
L
T
−55
+150
+150
J
T
STG
Storage Temperature
−65
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
DD
Supply Voltage Range
18.0
V
IN
Input Voltage INA and INB
V
DD
V
T
A
Operating Ambient Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to +125°C unless otherwise noted. Currents are defined as
DD
J
positive into the device and negative out of the device.)
Symbol
SUPPLY
Parameter
Test Condition
Min
Typ
Max
Unit
V
Operating Range
4.5
−
−
18.0
0.95
4.3
V
mA
V
DD
I
Supply Current, Inputs Not Connected
Turn−On Voltage
0.70
3.9
3.7
DD
V
ON
INA = V , INB = 0 V
3.5
3.3
DD
V
OFF
Turn−Off Voltage
INA = V , INB = 0 V
4.1
V
DD
INPUTS
V
INx Logic Low Threshold
INx Logic High Threshold
Non−Inverting Input Current
Inverting Input Current
0.8
−
1.2
1.6
−
−
V
V
IL_T
V
IH_T
2.0
175
1.5
0.8
I
I
IN from 0 to V
IN from 0 to V
−1.5
−175
0.2
mA
mA
V
IN+
DD
−
IN−
DD
V
HYS_T
TTL Logic Hysteresis Voltage
0.4
OUTPUTS
I
OUT Current, Mid−Voltage, Sinking (Note 8)
OUT Current, Mid−Voltage, Sourcing (Note 8)
OUTx at V / 2,
LOAD
−
−
4.3
−
−
A
A
SINK
DD
C
= 0.22 mF, f = 1 kHz
I
OUTx at V / 2,
−2.8
SOURCE
DD
C
C
C
= 0.22 mF, f = 1 kHz
= 0.22 mF, f = 1 kHz
= 0.22 mF, f = 1 kHz
LOAD
LOAD
LOAD
I
OUT Current, Peak, Sinking (Note 8)
OUT Current, Peak, Sourcing (Note 8)
Output Reverse Current Withstand (Note 8)
Propagation Matching Between Channels
−
−
−
−
5
−5
500
2
−
−
−
4
A
A
PK_SINK
I
PK_SOURCE
I
mA
ns
RVS
T
INA = INB, OUTA and OUTB at
50% Point
DEL.MATCH
t
Output Rise Time (Note 9)
C
= 2200 pF
LOAD
−
12
20
ns
RISE
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FAN3213, FAN3214
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to +125°C unless otherwise noted. Currents are defined as
DD
J
positive into the device and negative out of the device.) (continued)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OUTPUTS
t
Output Fall Time (Note 9)
Output Propagation Delay, TTL Inputs (Note 9)
C
= 2200 pF
LOAD
−
9
17
29
ns
ns
FALL
t
t
0–5 V , 1 V/ns Slew Rate
9
17
D1, D2
IN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Not tested in production.
9. See Timing Diagrams of Figure 6 and Figure 7.
TIMING DIAGRAMS
90%
90%
Output
Output
10%
10%
V
INH
V
Input
INH
Input
V
INL
V
INL
t
D2
t
D1
t
D2
t
D1
t
t
RISE
t
t
FALL
FALL
RISE
Figure 6. Non−Inverting
Figure 7. Inverting
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FAN3213, FAN3214
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted)
A
DD
Figure 8. IDD (Static) vs. Supply Voltage (Note 10)
Figure 9. IDD (Static) vs. Supply Voltage (Note 10)
Figure 10. IDD (No−Load) vs. Frequency
Figure 11. IDD (No−Load) vs. Frequency
Figure 12. Input Thresholds vs. Supply Voltage
Figure 13. Input Thresholds vs. Supply Voltage
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FAN3213, FAN3214
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted) (continued)
A
DD
Figure 14. UVLO Thresholds vs. Temperature
Figure 15. Propagation Delay vs. Supply Voltage
Figure 16. Propagation Delay vs. Supply Voltage
Figure 17. Propagation Delay vs. Supply Voltage
Figure 18. Propagation Delay vs. Supply Voltage
Figure 19. Fall Time vs. Supply Voltage
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FAN3213, FAN3214
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted) (continued)
A
DD
Figure 20. Rise Time vs. Supply Voltage
Figure 21. Rise and Fall Time vs. Temperature
Figure 22. Rise / Fall Waveforms with 2.2 nF Load
Figure 23. Rise / Fall Waveforms with 10 nF Load
Figure 24. Quasi−Static Source Current with
Figure 25. Quasi−Static Sink Current with
V
DD = 12 V (Note 11)
VDD = 12 V (Note 11)
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FAN3213, FAN3214
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted) (continued)
A
DD
Figure 26. Quasi−Static Source Current with
Figure 27. Quasi−Static Sink Current with
V
DD = 8 V (Note 11)
VDD = 8 V (Note 11)
10.For any inverting inputs pulled low, non−inverting inputs pulled high, or outputs driven high; static I increases by the current flowing
DD
through the corresponding pull−up/down resistor show n in Figure 4 and Figure 5.
11. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current−measurement loop.
TEST CIRCUIT
VDD
470 mF
Al. El.
4.7 mF
ceramic
Current Probe
LACROY AP015
IOUT
VOUT
IN
1 kHz
1 mF
ceramic
CLOAD
0.22 mF
Figure 28. Quasi−Static IOUT / VOUT Test Circuit
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FAN3213, FAN3214
APPLICATIONS INFORMATION
V DD
Input Thresholds
The FAN3213 and the FAN3214 drivers consist of two
identical channels that may be used independent ly at rated
current or connected in parallel to double the individual
current capacity.
The input thresholds meet industry−standard TTL−logic
thresholds independent of the V
voltage, and there is
DD
a hysteresis voltage of approximately 0.4 V. These levels
permit the inputs to be driven from a range of input logic
signal levels for which a voltage over 2 V is considered logic
HIGH. The driving signal for the TTL inputs should have
fast rising and falling edges with a slew rate of 6 V/ms or
faster, so a rise time from 0 to 3.3 V should be 550 ns or less.
With reduced slew rate, circuit noise could cause the driver
input voltage to exceed the hysteresis voltage and re−trigger
the driver input, causing erratic operation.
Input
stage
V OUT
Static Supply Current
In the I
(static) typical performance characteristics
DD
Figure 29. Miller Drive Output Architecture
show n in Figure 8 and Figure 9, each curve is produced with
both inputs floating and both outputs LOW to indicate the
lowest static I current. For other states, additional current
flows through the 100 kW resistors on the inputs and outputs
show n in the block diagram of each part (see Figure 4 and
Under−Voltage Lockout (UVLO)
DD
The FAN321x startup logic is optimized to drive
ground−referenced N−channel MOSFETs with an
under−voltage lockout (UVLO) function to ensure that the
Figure 5). In these cases, the actual static I current is the
value obtained from the curves plus this additional current.
DD
IC starts up in an orderly fashion. When V is rising, yet
DD
below the 3.9 V operational level, this circuit holds the
output LOW, regardless of the status of the input pins. After
the part is active, the supply voltage must drop 0.2 V before
the part shuts down. This hysteresis helps prevent chatter
MillerDrive Gate Drive Technology
FAN3213 and FAN3214 gate drivers incorporate the
Miller Drive architecture show n in Figure x28. For the
output stage, a combination of bipolar and MOS devices
provide large currents over a wide range of supply voltage
and temperature variations. The bipolar devices carry the
bulk of the current as OUT swings between 1/3 to 2/3 V
and the MOS devices pull the output to the HIGH or LOW
rail.
The purpose of the Miller Drive architecture is to speed up
switching by providing high current during the Miller
plateau region when the gate−drain capacitance of the
MOSFET is being charged or discharged as part of the
turn−on/turn−off process.
For applications with zero voltage switching during the
MOSFET turn−on or turn−off interval, the driver supplies
high peak current for fast switching even though the Miller
plateau is not present. This situation of ten occurs in
synchronous rectifier applications because the body diode is
generally conducting before the MOSFET is switched ON.
when low V supply voltages have noise from the power
DD
switching. This configuration is not suitable for driving
high−side P−channel MOSFETs because the low output
voltage of the driver would turn the P−channel MOSFET on
DD
with V below 3.9 V.
DD
VDD Bypass Capacitor Guidelines
To enable this IC to turn a device ON quickly, a local
high−frequency bypass capacitor, C , with low ESR and
BYP
ESL should be connected between the VDD and GND pins
with minimal trace length. This capacitor is in addition to
bulk electrolytic capacitance of 10 mF to 47 mF commonly
found on driver and controller bias circuits.
A typical criterion for choosing the value of C
is to
BYP
keep the ripple voltage on the V supply to ≤5%. This is
DD
often achieved with a value ≥20 times the equivalent load
capacitance C
, defined here as Q
/V . Ceramic
GATE DD
EQV
capacitors of 0.1 mF to 1 mF or larger are common choices,
as are dielectrics, such as X5R and X7R, with good
temperature characteristics and high pulse current
capability.
The output pin slew rate is determined by V voltage and
DD
the load on the output. It is not user adjustable, but a series
resistor can be added if a slower rise or fall time at the
MOSFET gate is needed.
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FAN3213, FAN3214
VDD
VDS
If circuit noise affects normal operation, the value of C
BYP
may be increased, to 50−100 times the C , or CBYP may
EQV
be split into two capacitors. One should be a larger value,
based on equivalent load capacitance, and the other a smaller
value, such as 1−10 nF mounted closest to the VDD and
GND pins to carry the higher−frequency components of the
current pulses. The bypass capacitor must provide the pulsed
current from both of the driver channels and, if the drivers
are switching simultaneously, the combined peak current
CBYP
FAN321x
PWM
sourced from the C
a single channel is switching.
would be twice as large as when
BYP
Figure 30. Current Path for MOSFET Turn−On
Layout and Connection Guidelines
Figure 31 shows the current path when the gate driver
turns the MOSFET OFF. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn−off times, the resistance and
inductance in this path should be minimized.
The FAN3213 and FAN3214 gate drivers incorporate
fast−reacting input circuits, short propagation delays, and
powerful output stages capable of delivering current peaks
over 4 A to facilitate voltage transition times from under
10 ns to over 150 ns. The following layout and connection
guidelines are strongly recommended:
VDD
VDS
• Keep high−current output and power ground paths
separate from logic input signals and signal ground paths.
This is especially critical for TTL−level logic thresholds
at driver input pins.
CBYP
FAN321x
• Keep the driver as close to the load as possible to
minimize the length of high−current traces. This reduces
the series inductance to improve high−speed switching,
while reducing the loop area that can radiate EMI to the
driver inputs and surrounding circuitry.
PWM
Figure 31. Current Path for MOSFET Turn−Off
• If the inputs to a channel are not externally connected, the
internal 100 kW resistors indicated on block diagrams
command a low output. In noisy environments, it may be
necessary to tie inputs of an unused channel to VDD or
GND using short traces to prevent noise from causing
spurious output switching.
• Many high−speed power circuits can be susceptible to
noise injected from their own output or other external
sources, possibly causing output re−triggering. These
effects can be obvious if the circuit is tested in breadboard
or non−optimal circuit layouts with long input or output
leads. For best results, make connections to all pins as
short and direct as possible.
Operational Waveforms
At power−up, the driver output remains LOW until the
V
DD
voltage reaches the turn−on threshold. The magnitude
of the OUT pulses rises with V until steady−state V is
DD
DD
reached. The non−inverting operation illustrated in
Figure 32 shows that the output remains LOW until the
UVLO threshold is reached, then the output is in−phase with
the input.
VDD
Turn−on threshold
• FAN3213 and FAN3214 are pin−compatible with many
other industry−standard drivers.
• The turn−on and turn−off current paths should be
minimized, as discussed in the following section.
IN−
Figure 30 shows the pulsed gate drive current path when
the gate driver is supplying gate charge to turn the MOSFET
on. The current is supplied from the local bypass capacitor,
IN+
C , and flows through the driver to the MOSFET gate and
BYP
to ground. To reach the high peak currents possible, the
resistance and inductance in the path should be minimized.
OUT
The localized C
acts to contain the high peak current
BYP
pulses within this driver−MOSFET circuit , preventing them
from disturbing the sensitive analog circuitry in the PWM
controller.
Figure 32. Non−Inverting Startup Waveforms
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12
FAN3213, FAN3214
The inverting configuration of startup waveforms are
consumption under dynamic operating conditions,
shown in Figure 33. With IN+ tied to V and the input
including pin pull−up/pull−down resistors. The internal
DD
signal applied to IN–, the OUT pulses are inverted with
current consumption (I ) can be estimated using
DYNAMIC
respect to the input. At power−up, the inverted output
the graphs in Figure 10 of the Typical Performance
remains LOW until the V voltage reaches the turn−on
Characteristics to determine the current I
drawn
DD
DYNAMIC
threshold, then it follows the input with inverted phase.
from V under actual operating conditions:
DD
PDYMANIC + IDYNAMIC @ VDD @ n
(eq. 3)
where n is the number of driver ICs in use. Note that n is
usually be one IC even if the IC has two channels, unless
two or more driver ICs are in parallel to drive a large load.
VDD
Turn−on threshold
Once the power dissipated in the driver is determined, the
driver junction rise with respect to circuit board can be
evaluated using the following thermal equation, assuming
IN−
y
was determined for a similar thermal design (heat
JB
sinking and air flow):
IN+
TJ + PTOTAL @ YJB ) TB
(eq. 4)
(VDD
)
where:
T = driver junction temperature;
J
y
JB
= (psi) thermal characterization parameter relating
temperature rise to total power dissipation; and
= board temperature in location as defined in the
OUT
T
B
Thermal Characteristics table.
To give a numerical example, assume for a 12 V VDD
(Vibas) system, the synchronous rectifier switches of
Figure 33. Inverting Startup Waveforms
Figure 34 have a total gate charge of 60 nC at V = 7 V.
GS
Thermal Guidelines
Therefore, two devices in parallel would have 120 nC gate
charge. At a switching frequency of 300 kHz, the total
power dissipation is:
Gate drivers used to switch MOSFETs and IGBTs at high
frequencies can dissipate significant amounts of power. It is
important to determine the driver power dissipation and the
resulting junction temperature in the application to ensure
that the part is operating within acceptable temperature
limits.
(eq. 5)
(eq. 6)
(eq. 7)
PGATE + 120 nC @ 7 V @ 300 kHz @ 2 + 0.504 W
PDYNAMIC + 3.0 mA @ 12 V @ 1 + 0.036 W
PTOTAL + 0.540 W
The total power dissipation in a gate driver is the sum of
The SOIC−8 has
a
junction−to−board thermal
two components, P
and P
:
GATE
PTOTAL + PGATE ) PDYNAMIC
DYNAMIC
characterization parameter of y = 42°C/W. In a system
JB
(eq. 1)
application, the localized temperature around the device is
a function of the layout and construction of the PCB along
with airflow across the surfaces. To ensure reliable
operation, the maximum junction temperature of the device
must be prevented from exceeding the maximum rating of
P
GATE
(Gate Driving Loss): The most significant power
loss results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the
switching frequency. The power dissipation that results
from driving a MOSFET at a specified gate−source
150°C; with 80% derating, T would be limited to 120°C.
J
Rearranging Equation 4 determines the board temperature
voltage, V , with gate charge, Q , at switching
GS
G
required to maintain the junction temperature below 120°C:
frequency, f , is determined by:
SW
TB,MAX + TJ * PTOTAL @ YJB
PGATE + QG @ VGS @ fSW @ n
(eq. 8)
(eq. 2)
where n is the number of driver channels in use (1 or 2).
TB,MAX + 120°C * 0.54 W @ 42°CńW + 97°C
(eq. 9)
P
(Dynamic Pre−Drive/Shoot−through
DYNAMIC
Current): A power loss resulting from internal current
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FAN3213, FAN3214
TYPICAL APPLICATION DIAGRAMS
VIN
VOUT
PWM
1
2
3
4
8
FAN3214
7
8
7
6
5
1
2
3
4
6
Vbias
Timing/
Isolation
A
5
GND
VDD
FAN3214
B
Figure 34. High−Current Forward Converter
Figure 35. Center−Tapped Bridge Output with
with Synchronous Rectification
Synchronous Rectifiers
VIN
QC
QA
QD
QB
FAN3214
PWM−A
FAN3225C
SR−1
Secondary
Phase Shift
Controller
PWM−B
PWM−C
SR−2
PWM−D
Figure 36. Secondary Controlled Full Bridge with Current Doubler Output,
Synchronous Rectifiers (Simplified)
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14
FAN3213, FAN3214
ORDERING INFORMATION
Part Number
†
Logic
Input Threshold
TTL
Package
Shipping
FAN3213TMX
FAN3214TMX
Dual Inverting Channels
SOIC−8
2,500 / Tape & Reel
Dual Non−Inverting Channels
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Table 1. RELATED PRODUCTS
Gate Drive
(Note 12)
(Sink/Src)
Type
Part Number
FAN3111C
FAN3111E
Input Threshold
Logic
Package
Single 1 A
Single 1 A
+1.1 A / −0.9 A
+1.1 A / −0.9 A
CMOS
Single Channel of Dual−Input/Single−Output
SOT23−5, MLP6
SOT23−5, MLP6
External (Note 13) Single Non−Inverting Channel with External
Reference
Single 2 A
Single 2 A
Single 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
FAN3100C
FAN3100T
FAN3180
+2.5 A / −1.8 A
+2.5 A / −1.8 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
CMOS
TTL
Single Channel of Two−Input/One−Output
Single Channel of Two−Input/One−Output
Single Non−Inverting Channel + 3.3−V LDO
Dual Inverting Channels
SOT23−5, MLP6
SOT23−5, MLP6
SOT23−5
TTL
FAN3216T
FAN3217T
FAN3226C
FAN3226T
FAN3227C
FAN3227T
FAN3228C
TTL
SOIC8
TTL
Dual Non−Inverting Channels
SOIC8
CMOS
TTL
Dual Inverting Channels + Dual Enable
Dual Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
CMOS
TTL
CMOS
Dual Channels of Two−Input/One−Output,
Pin Config.1
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
FAN3228T
FAN3229C
FAN3229T
FAN3268T
FAN3278T
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
TTL
CMOS
TTL
Dual Channels of Two−Input/One−Output,
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8
Pin Config.1
Dual Channels of Two−Input/One−Output,
Pin Config.2
Dual Channels of Two−Input/One−Output,
Pin Config.2
TTL
20 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
TTL
30 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
SOIC8
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Single 9 A
Single 9 A
Single 9 A
Single 9 A
Dual 12 A
Dual 12 A
FAN3213T
FAN3214T
FAN3223C
FAN3223T
FAN3224C
FAN3224T
FAN3225C
FAN3225T
FAN3121C
FAN3121T
FAN3122C
FAN3122T
FAN3240
+2.5 A / −1.8 A
+2.5 A / −1.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
+12.0 A
TTL
TTL
Dual Inverting Channels
SOIC8
Dual Non−Inverting Channels
SOIC8
CMOS
TTL
Dual Inverting Channels + Dual Enable
Dual Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Channels of Two−Input/One−Output
Dual Channels of Two−Input/One−Output
Single Inverting Channel + Enable
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8
CMOS
TTL
CMOS
TTL
CMOS
TTL
Single Inverting Channel + Enable
CMOS
TTL
Single Non−Inverting Channel + Enable
Single Non−Inverting Channel + Enable
Dual−Coil Relay Driver, Timing Config. 0
Dual−Coil Relay Driver, Timing Config. 1
TTL
FAN3241
+12.0 A
TTL
SOIC8
12.Typical currents with OUTx at 6 V and V = 12 V.
DD
13.Thresholds proportional to an externally supplied reference voltage.
MillerDrive is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13735G
SOIC8
PAGE 1 OF 1
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