FAN3122TM1X-F085 [ONSEMI]
单 9 A 高速，低压侧门极驱动器;
| 型号： | FAN3122TM1X-F085 |
| 厂家： | 
ONSEMI |
| 描述： | 单 9 A 高速，低压侧门极驱动器 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总20页 (文件大小：1815K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Single 9-A High-Speed,
Low-Side Gate Driver
FAN3121, FAN3122
Description
The FAN3121 and FAN3122 MOSFET drivers are designed to drive
N−channel enhancement MOSFETs in low−side switching
applications by providing high peak current pulses. The drivers are
available with either TTL input thresholds (FAN312xT) or
VDD−proportional CMOS input thresholds (FAN312xC). Internal
circuitry provides an under−voltage lockout function by holding the
output low until the supply voltage is within the operating range.
FAN312x drivers incorporate the MillerDrive™ architecture for the
final output stage. This bipolar / MOSFET combination provides the
highest peak current during the Miller plateau stage of the MOSFET
turn−on / turn−off process.
The FAN3121 and FAN3122 drivers implement an enable function
on pin 3 (EN), previously unused in the industry−standard pin−out.
The pin is internally pulled up to VDD for active HIGH logic and can be
left open for standard operation.
The AEC−Q100 automotive−qualified versions are available in
8−lead SOIC packages with and without exposed pad.
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8
8
SOIC8
CASE 751EB
1
1
SOIC−8 EP
CASE 751AC
MARKING DIAGRAM
8
XXXXX
AYWWG
G
Features
• Industry−Standard Pin−out with Enable Input
• 4.5−V to 18−V Operating Range
• 11.4 A Peak Sink at VDD = 12 V
1
SOIC8, SOIC−8 EP
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• 9.7−A Sink / 7.1−A Source at VOUT = 6 V
• Inverting Configuration (FAN3121) and
• Non−Inverting Configuration (FAN3122)
• Internal Resistors Turn Driver Off if No Inputs
• 23−ns / 19−ns Typical Rise/Fall Times (10 nF Load)
• 18 ns to 23 ns Typical Propagation Delay Time
• Choice of TTL or CMOS Input Thresholds
• MillerDrive Technology
• 8−Lead SOIC Package (Pb−Free Finish) with Exposed Pad Option
• Rated from –40°C to +125°C
• Automotive Qualified to AEC−Q100
• These are Pb−Free Devices
(Note: Microdot may be in either location)
*This information is generic. Please refer to device
data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of
this data sheet.
Applications
• Synchronous Rectifier Circuits
• High−Efficiency MOSFET Switching
• Switch−Mode Power Supplies
• DC−to−DC Converters
• Motor Control
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
April, 2020 − Rev. 0
FAN3121−F085/D
FAN3121, FAN3122
AUTOMOTIVE−QUALIFIED SYSTEMS PIN CONFIGURATIONS
VDD
IN
VDD
OUT
VDD
IN
VDD
OUT
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
EN
EN
OUT
GND
OUT
GND
GND
GND
Figure 1. FAN3121 Pin Configuration
Figure 2. FAN3122 Pin Configuration
PACKAGE OUTLINES
1
2
3
4
8
1
2
3
4
8
7
6
5
7
6
5
Figure 3. SOIC−8 (Top View)
Figure 4. SOIC−8−EP (Top View)
THERMAL CHARACTERISTICS (Note 1)
Q
JL
Q
JT
Q
JA
Y
JB
Y
JT
(Note 2)
(Note 3)
(Note 4)
(Note 5)
(Note 6)
Package
Unit
°C/W
°C/W
8−Pin Small Outline Integrated Circuit (SOIC)
38
29
87
41
2.3
7
8−Pin Small Outline Integrated Circuit with Exposed Pad (SOIC−EP)
5.1
75
40
5.1
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (Q ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)
JL
that are typically soldered to a PCB.
3. Theta_JT (Q ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform
JT
temperature by a top−side heatsink.
4. Theta_JA (Q ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given
JA
is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51−2, JESD51−5, and JESD51−7,
as appropriate.
5. Psi_JB (Y ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application
JB
circuit board reference point for the thermal environment defined in Note 4. For the SOIC−8−EP package, the board reference is defined
as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC−8 package, the board reference
is defined as the PCB copper adjacent to pin 6.
6. Psi_JT (Y ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of
JT
the top of the package for the thermal environment defined in Note 4.
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2
FAN3121, FAN3122
PIN DEFINITIONS
FAN3121 FAN3122 Name
Description
3
3
EN
Enable Input. Pull pin LOW to inhibit driver. EN has logic thresholds for both TTL and CMOS IN
thresholds.
4, 5
2
4, 5
2
GND Ground. Common ground reference for input and output circuits.
IN
Input.
Gate Drive Output. Held LOW unless required input is present and V is above the UVLO threshold.
6, 7
OUT
OUT
DD
6, 7
1, 8
Gate Drive Output (inverted from the input). Held LOW unless required input is present and V is
above the UVLO threshold.
DD
1, 8
V
DD
Supply Voltage. Provides power to the IC.
P1
Thermal Pad (SOIC−8−EP only). Exposed metal on the bottom of the package; it is recommended to
connect externally on the PCB the Exposed Pad together with the Ground. NOT suitable for carrying
current.
VDD
IN
VDD
VDD
IN
VDD
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
OUT
OUT
GND
OUT
OUT
GND
EN
EN
GND
GND
Figure 5. FAN3121 Pin Assignments (Repeated)
Figure 6. FAN3122 Pin Assignments (Repeated)
OUTPUT LOGIC
FAN3121
FAN3122
EN
IN
OUT
EN
IN
OUT
0
0
0
0
1
0
0
0 (Note 7)
0
0
0
1
0
1 (Note 7)
0
0
1
0 (Note 7)
1
1 (Note 7)
1 (Note 7)
1 (Note 7)
1 (Note 7)
1 (Note 7)
7. Default input signal if no external connection is made.
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3
FAN3121, FAN3122
BLOCK DIAGRAM
VDD
1
2
8
VDD
Inverting
(FAN3121)
100 kW
UVLO
VDD_OK
IN
OUT (FAN3121)
OUT (FAN3122)
7
6
100k
OUT (FAN3121)
OUT (FAN3122)
Non−Inverting
(FAN3122)
100 kW
VDD
100 kW
EN
3
4
5
GND
GND
Figure 7. Block Diagram
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
Max
Unit
V
V
V
to GND
20.0
DD
EN
DD
V
EN to GND
IN to GND
GND − 0.3
GND − 0.3
GND − 0.3
−
V
V
V
+ 0.3
+ 0.3
+ 0.3
V
DD
DD
DD
V
V
IN
V
OUT
OUT to GND
V
T
Lead Soldering Temperature (10 Seconds)
Junction Temperature
+260
°C
°C
°C
L
T
−55
+150
+150
J
T
STG
Storage Temperature
−65
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
Supply Voltage Range
Enable Voltage EN
Input Voltage IN
18.0
DD
EN
V
V
DD
V
DD
V
V
IN
0
V
T
A
Operating Ambient Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
FAN3121, FAN3122
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to +125°C unless otherwise noted. Currents are defined as
DD
J
positive into the device and negative out of the device.)
Symbol
SUPPLY
Parameter
Test Condition
Min
Typ
Max
Unit
V
Operating Range
4.5
−
−
18.0
1.00
0.85
4.3
V
DD
DD
I
Supply Current, Inputs / EN Not Connected
TTL
CMOS (Note 8)
0.65
0.58
4.0
mA
−
V
ON
Device Turn−On Voltage (UVLO)
Device Turn−Off Voltage (UVLO)
3.5
3.25
V
V
V
OFF
3.75
4.15
INPUTS (TTL, FAN312XT) (Note 9)
V
INx Logic Low Threshold
INx Logic High Threshold
TTL Logic Hysteresis Voltage
Non−inverting Input Current
Non−inverting Input Current
Inverting Input Current
0.8
−
1.0
1.7
0.70
−
−
V
V
IL_T
IH_T
V
2.0
V
HYS_T
0.40
−1.5
90
0.85
1.5
V
I
I
I
I
IN = 0 V
IN = V
mA
mA
mA
mA
INx_T
INx_T
INx_T
INx_T
120
−120
−
175
−90
1.5
DD
IN = 0 V
IN = V
−175
−1.5
Inverting Input Current
DD
INPUTS (CMOS, FAN312xC) (Note 9)
V
INx Logic Low Threshold
INx Logic High Threshold
CMOS Logic Hysteresis Voltage
Non−Inverting Input Current
Non−Inverting Input Current
Inverting Input Current
30
−
38
55
−
%V
%V
%V
IL_C
IH_C
DD
DD
DD
V
70
V
I
12
17
24
HYS_C
INx_C
INx_C
INx_C
INx_C
IN = 0 V
IN = V
−1.5
90
−
1.5
175
−90
1.5
mA
I
120
−120
−
mA
mA
mA
DD
I
IN = 0 V
IN = V
−175
−1.5
I
Inverting Input Current
DD
ENABLE (FAN3121, FAN3122)
V
Enable Logic Low Threshold
EN from 5 V to 0 V
EN from 0 V to 5 V
1.2
1.8
0.20
68
6
1.6
2.2
0.60
100
17
2.0
2.6
0.85
134
35
V
V
ENL
ENH
V
Enable Logic High Threshold
V
HYS_T
TTL Logic Hysteresis Voltage
Enable Pull−up Resistance
V
R
kW
ns
ns
PU
t
t
, t
Propagation Delay, CMOS EN (Note 10)
Propagation Delay, TTL EN (Note 10)
D1 D2
, t
8
22
34
D1 D2
OUTPUTS
I
OUT Current, Mid−Voltage, Sinking (Note 11)
OUT at V / 2, C
= 1.0 mF,
= 1.0 mF,
−
−
9.7
7.1
−
−
A
A
SINK
DD
LOAD
f = 1 kHz
I
OUT Current, Mid−Voltage, Sourcing (Note 11)
OUT at V / 2, C
SOURCE
DD
LOAD
f = 1 kHz
I
OUT Current, Peak, Sinking (Note 11)
OUT Current, Peak, Sourcing (Note 11)
Output Reverse Current Withstand (Note 11)
Output Rise Time (Note 10) CMOS Inputs
Output Fall Time (Note 10) CMOS Inputs
Output Rise Time (Note 10) TTL Inputs
Output Fall Time (Note 10) TTL Inputs
Output Propagation Delay, CMOS Inputs
C
C
= 1.0 mF, f = 1 kHz
= 1.0 mF, f = 1 kHz
−
−
11.4
10.6
−
−
A
A
PK_SINK
LOAD
LOAD
I
−
PK_SOURCE
I
1500
−
−
mA
ns
ns
ns
ns
ns
RVS
t
t
t
t
C
C
C
C
= 10 nF
= 10 nF
= 10 nF
= 10 nF
23
31
27
36
28
35
RISE
FALL
RISE
FALL
LOAD
LOAD
LOAD
LOAD
−
19
−
23
−
19
t
t
0 – 12 V , 1 V/ns Slew Rate
6
18
D1, D2
IN
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5
FAN3121, FAN3122
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to +125°C unless otherwise noted. Currents are defined as
DD
J
positive into the device and negative out of the device.) (continued)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OUTPUTS
t
t
Output Propagation Delay, TTL Inputs (Note 10)
High Level Output Voltage
0 – 5 V , 1 V/ns Slew Rate
9
−
−
23
15
10
36
35
25
ns
D1, D2
IN
V
V
OH
= V – V , I = –1 mA
OUT OUT
mV
mV
OH
DD
V
Low Level Output Voltage
IOUT = 1 mA
OL
8. Lower supply current due to inactive TTL circuitry.
9. EN inputs have modified TTL thresholds; refer to the ENABLE section.
10.See Timing Diagrams of Figure 8 and Figure 9.
11. Not tested in production.
TIMING DIAGRAMS
Input
or
Enable
V
Input
or
Enable
IH
V
IH
V
IL
VIL
tD1
tD2
tD1
tD2
tRISE
tFALL
tFALL
tRISE
90%
10%
90%
10%
Output
Output
Figure 8. Non−Inverting
Figure 9. Inverting
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted)
Figure 10. IDD (Static) vs. Supply Voltage (Note 12)
Figure 11. IDD (Static) vs. Supply Voltage (Note 12)
Figure 12. IDD (No−Load) vs. Frequency
Figure 13. IDD (No−Load) vs. Frequency
Figure 14. IDD (10 nF Load) vs. Frequency
Figure 15. IDD (10 nF Load) vs. Frequency
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
Figure 16. IDD (Static) vs. Temperature (Note 12)
Figure 18. Input Thresholds vs. Supply Voltage
Figure 20. Input Thresholds % vs. Supply Voltage
Figure 17. IDD (Static) vs. Temperature (Note 12)
Figure 19. Input Thresholds vs. Supply Voltage
Figure 21. Enable Thresholds vs. Supply Voltage
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
Figure 22. CMOS Input Thresholds vs. Temperature
Figure 23. TTL Input Thresholds vs. Temperature
Figure 24. TTL Input Thresholds vs. Temperature
Figure 25. UVLO Thresholds vs. Temperature
Figure 26. UVLO Hysteresis vs. Temperature
Figure 27. Propagation Delay vs. Supply Voltage
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
Figure 28. Propagation Delay vs. Supply Voltage
Figure 29. Propagation Delay vs. Supply Voltage
Figure 31. Propagation Delay vs. Supply Voltage
Figure 33. Propagation Delays vs. Temperature
Figure 30. Propagation Delay vs. Supply Voltage
Figure 32. Propagation Delays vs. Temperature
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
Figure 34. Propagation Delays vs. Temperature
Figure 36. Propagation Delays vs. Temperature
Figure 38. Rise Time vs. Supply Voltage
Figure 35. Propagation Delays vs. Temperature
Figure 37. Fall Time vs. Supply Voltage
Figure 39. Rise and Fall Time vs. Temperature
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
Figure 40. Rise / Fall Waveforms with 10 nF Load
Figure 41. Quasi−Static Source Current with
DD = 12 V (Note 13)
V
Figure 42. Quasi−Static Sink Current with
Figure 43. Quasi−Static Source Current with
V
DD = 12 V (Note 13)
VDD = 8 V (Note 13)
VDD
470 mF
Al. El.
(2) x 4.7 μF
ceramic
Current Probe
LACROU AP015
FAN3121/22
IOUT
IN
1 kHz
1 mF
ceramic
CLOAD
1 mF
VOUT
Figure 44. Quasi−Static Sink Current with
DD = 8 V (Note 13)
Figure 45. Quasi−Static IOUT / VOUT Test Circuit
V
12.For any inverting inputs pulled LOW, non−inverting inputs pulled HIGH, or outputs driven HIGH; static I increases by the current flowing
DD
through the corresponding pull−up/down resistor, shown in Figure 7.
13.The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current−measurement loop.
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FAN3121, FAN3122
APPLICATIONS INFORMATION
The FAN3121 and FAN3122 family offers versions in
either TTL or CMOS input configuration. In the FAN3121T
and FAN3122T, the input thresholds meet
industry−standard TTL−logic thresholds independent of the
voltage, and there is a hysteresis voltage of
The purpose of the Miller Drive architecture is to speed up
switching by providing high current during the Miller
plateau region when the gate−drain capacitance of the
MOSFET is being charged or discharged as part of the
turn−on / turn−off process.
V
DD
approximately 0.7 V. These levels permit the inputs to be
driven from a range of input logic signal levels for which a
voltage over 2 V is considered logic HIGH. The driving
signal for the TTL inputs should have fast rising and falling
edges with a slew rate of 6 V/ms or faster, so the rise time
from 0 to 3.3 V should be 550 ns or less.
For applications with zero voltage switching during the
MOSFET turn−on or turn−off interval, the driver supplies
high peak current for fast switching, even though the Miller
plateau is not present. This situation often occurs in
synchronous rectifier applications because the body diode is
generally conducting before the MOSFET is switched on.
The FAN3121 and FAN3122 output can be enabled or
disabled using the EN pin with a very rapid response time.
If EN is not externally connected, an internal pull−up
resistor enables the driver by default. The EN pin has logic
thresholds for parts with either TTL or CMOS IN thresholds.
In the FAN3121C and FAN3122C, the logic input
The output pin slew rate is determined by V voltage and
DD
the load on the output. It is not user adjustable, but a series
resistor can be added if a slower rise or fall time at the
MOSFET gate is needed.
V DD
thresholds are dependent on the V level and, with V of
DD
DD
12 V, the logic rising edge threshold is approximately 55%
of V and the input falling edge threshold is approximately
DD
38% of V . The CMOS input configuration offers a
DD
hysteresis voltage of approximately 17% of V . The
DD
CMOS inputs can be used with relatively slow edges
(approaching DC) if good decoupling and bypass techniques
are incorporated in the system design to prevent noise from
violating the input voltage hysteresis window. This allows
setting precise timing intervals by fitting an R−C circuit
between the controlling signal and the IN pin of the driver.
The slow rising edge at the IN pin of the driver introduces
a delay between the controlling signal and the OUT pin of
the driver.
Input
stage
V OUT
Static Supply Current
In the I (static) Typical Performance Characteristics,
DD
the curves are produced with all inputs / enables floating
Figure 46. Miller Drive Output Architecture
(OUT is LOW) and indicates the lowest static I current
DD
for the tested configuration. For other states, additional
current flows through the 100 kW resistors on the inputs and
outputs, as shown in the block diagram (see Figure 7). In
Under−Voltage Lockout (UVLO)
The FAN312x startup logic is optimized to drive
ground−referenced N−channel MOSFETs with an
under−voltage lockout (UVLO) function to ensure that the
these cases, the actual static I current is the value obtained
DD
from the curves, plus this additional current.
IC starts in an orderly fashion. When V
is rising, yet
DD
below the 4.0 V operational level, this circuit holds the
output low, regardless of the status of the input pins. After
the part is active, the supply voltage must drop 0.25 V before
the part shuts down. This hysteresis helps prevent chatter
MillerDrive Gate−Drive Technology
FAN312x gate drivers incorporate the MillerDrive
architecture shown in Figure 46. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the bulk of
when low V supply voltages have noise from the power
DD
switching. This configuration is not suitable for driving
high−side P−channel MOSFETs because the low output
voltage of the driver would turn the P−channel MOSFET on
the current as OUT swings between 1/3 to 2/3 V and the
MOS devices pull the output to the HIGH or LOW rail.
DD
with V below 4.0 V.
DD
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FAN3121, FAN3122
VDD
VDS
VDD Bypassing and Layout Considerations
The FAN3121 and FAN3122 are available in either 8−lead
SOIC or SOIC8−EP packages. In either package, the V
DD
CBYP
pins 1 and 8 and the GND pins 4 and 5 should be connected
together on the PCB.
FAN3121/2
In typical FAN312x gate−driver applications,
high−current pulses are needed to charge and discharge the
gate of a power MOSFET in time intervals of 50 ns or less.
A bypass capacitor with low ESR and ESL should be
PWM
connected directly between the V
and GND pins to
DD
provide these large current pulses without causing
unacceptable ripple on the V supply. To meet these
requirements in a small size, a ceramic capacitor of 1 mF or
larger is typically used, with a dielectric material such as
X7R, to limit the change in capacitance over the temperature
and / or voltage application ranges.
Figure 47 shows the pulsed gate drive current path when
the gate driver is supplying gate charge to turn the MOSFET
on. The current is supplied from the local bypass capacitor
Figure 48. Current Path for MOSFET Turn−Off
DD
Operational Waveforms
At power up, the FAN3121 inverting driver shown in
Figure 49 holds the output LOW until the V
voltage
DD
reaches the UVLO turn−on threshold, as indicated in
Figure 50. This facilitates proper startup control of low−side
N−channel MOSFETs.
VDD
C
BYP
and flows through the driver to the MOSFET gate and
to ground. To reach the high peak currents possible with the
FAN312x family, the resistance and inductance in the path
IN
OUT
should be minimized. The localized C
acts to contain the
BYP
high peak current pulses within this driver−MOSFET
circuit, preventing them from disturbing the sensitive analog
circuitry in the PWM controller.
Figure 49. Inverting Configuration
VDD
VDS
The OUT pulses’ magnitude follows V magnitude with
DD
the output polarity inverted from the input until steady−state
V
DD
is reached.
CBYP
FAN3121/2
VDD
Turn−on threshold
PWM
IN−
Figure 47. Current Path for MOSFET Turn−On
Figure 48 shows the path the current takes when the gate
driver turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn−off times, the resistance and
inductance in this path should be minimized.
IN+
(VDD
)
OUT
Figure 50. Inverting Startup Waveforms
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14
FAN3121, FAN3122
PGATE + QG @ VGS @ fSW
At power up, the FAN3122 non−inverting driver, shown
(eq. 2)
in Figure 51, holds the output LOW until the V voltage
DD
Dynamic Pre−drive / Shoot−through Current: A power
loss resulting from internal current consumption under
dynamic operating conditions, including pin pull−up /
pull−down resistors, can be obtained using graphs in
Typical Performance Characteristics to determine the
reaches the UVLO turn−on threshold, as indicated in
Figure 52. The OUT pulses magnitude follow V
DD
magnitude until steady−state V is reached.
DD
VDD
current I
drawn from V
under actual
DYNAMIC
DD
operating conditions:
IN
OUT
PDYMANIC + IDYNAMIC @ VDD
(eq. 3)
Once the power dissipated in the driver is determined, the
driver junction rise with respect to circuit board can be
evaluated using the following thermal equation, assuming
Figure 51. Non−Inverting Driver
y
was determined for a similar thermal design (heat
JB
sinking and air flow):
TJ + PTOTAL @ YJB ) TB
VDD
(eq. 4)
Turn−on threshold
where:
T = driver junction temperature;
J
y
JB
= (psi) thermal characterization parameter relating
IN−
temperature rise to total power dissipation; and
= board temperature in location as defined in the
T
B
Thermal Characteristics table.
In a full−bridge synchronous rectifier application, shown
in Figure 53, each FAN3122 drives a parallel combination
of two high−current MOSFETs, (such as FDMS8660S). The
typical gate charge for each SR MOSFET is 70 nC with
IN+
V
GS
= V = 9 V. At a switching frequency of 300 kHz, the
DD
total power dissipation is:
OUT
PGATE + 2 @ 70 nC @ 9 V @ 300 kHz + 0.378 W
(eq. 5)
(eq. 6)
(eq. 7)
PDYNAMIC + 2 mA @ 9 V + 18 mW
PTOTAL + 0.396 W
Figure 52. Non−Inverting Startup Waveforms
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at high
frequencies can dissipate significant amounts of power. It is
important to determine the driver power dissipation and the
resulting junction temperature in the application to ensure
that the part is operating within acceptable temperature
limits.
The SOIC−8 has
a
junction−to−board thermal
characterization parameter of y = 42°C/W. In a system
application, the localized temperature around the device is
a function of the layout and construction of the PCB along
with airflow across the surfaces. To ensure reliable
operation, the maximum junction temperature of the device
must be prevented from exceeding the maximum rating of
150°C; with 80% derating, T would be limited to 120°C.
Rearranging Equation 4 determines the board temperature
required to maintain the junction temperature below 120°C:
JB
The total power dissipation in a gate driver is the sum of
J
two components, P
and P
:
GATE
PTOTAL + PGATE ) PDYNAMIC
DYNAMIC
(eq. 1)
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit time)
to switch the load MOSFET on and off at the switching
frequency. The power dissipation that results from driving
TB,MAX + TJ * PTOTAL @ YJB
(eq. 8)
TB,MAX + 120°C * 0.396 W @ 42°CńW + 104°C
(eq. 9)
Consider tradeoffs between reducing overall circuit size
with junction temperature reduction for increased
reliability.
a MOSFET at a specified gate−source voltage, V , with
GS
gate charge, Q , at switching frequency, f , is
G
SW
determined by:
www.onsemi.com
15
FAN3121, FAN3122
Typical Application Diagrams
VOUT
VIN
B2
B1
A2
A1
BIAS
FAN3122
SR EN
FAN3122
From A2
From A1
1
2
3
4
8
1
8
7
6
5
VDD
IN
VDD
VDD
VDD
2
7
6
5
OUT
OUT
OUT
OUT
IN
SR EN
3
EN
EN
4
PGND
AGND
PGND
AGND
Figure 53. Full−Bridge Synchronous Rectification
VOUT
VIN
PWM
VBIAS
FAN3121
1
2
3
4
8
7
6
5
VDD
IN
VDD
P1
(AGND)
OUT
SR Enable
Active HIGH
EN
OUT
AGND
PGND
Figure 54. Hybrid Synchronous Rectification in a Forward Converter
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16
FAN3121, FAN3122
ORDERING INFORMATION
Part Number
†
Logic
Input Threshold
Package
SOIC−8
Shipping
Inverting Channels +
Enable
CMOS
TTL
2.500 / Tape & Reel
2.500 / Tape & Reel
2.500 / Tape & Reel
2.500 / Tape & Reel
2.500 / Tape & Reel
FAN3121CMX-F085
FAN3121TMX-F085
FAN3122CMX−F085
FAN3122TMX−F085
FAN3122TM1X−F085
SOIC−8
Non−Inverting
Channels + Enable
CMOS
TTL
SOIC−8
SOIC−8
SOIC−8−EP
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Table 1. RELATED PRODUCTS
Gate Drive
(Note 14) (Sink/Src)
Package
(Note 16)
Part Number
FAN3216T
FAN3217T
FAN3226C
FAN3226T
FAN3227C
FAN3227T
FAN3228C
FAN3228T
FAN3229C
FAN3229T
FAN3268T
Type
Input Threshold
TTL
Logic
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2A
Dual 2 A
Dual 2 A
Dual 2 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
Dual Inverting Channels
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
TTL
Dual Non−Inverting Channels
CMOS
TTL
Dual Inverting Channels + Dual Enable
Dual Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Channels of Two−Input / One−Output
Dual Channels of Two−Input / One−Output
Dual Channels of Two−Input / One−Output
Dual Channels of Two−Input / One−Output
CMOS
TTL
CMOS
TTL
CMOS
TTL
TTL
20 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
FAN3223C
FAN3213T
FAN3214T
FAN3223T
FAN3224C
FAN3224T
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
CMOS
TTL
Dual Inverting Channels + Dual Enable
Dual Inverting Channels
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
TTL
Dual Non−Inverting Channels
TTL
Dual Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
CMOS
TTL
SOIC8,
SOIC8−EP
FAN3225C
FAN3225T
Dual 4 A
Dual 4 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
CMOS
TTL
Dual Channels of Two−Input / One−Output
Dual Channels of Two−Input / One−Output
Single Inverting Channel + Enable
SOIC8
SOIC8
SOIC8
SOIC8
SOIC8
FAN3121C Single 9 A
FAN3121T Single 9 A
FAN3122C Single 9 A
FAN3122T Single 9 A
CMOS
TTL
Single Inverting Channel + Enable
CMOS
TTL
Single Non−Inverting Channel + Enable
Single Non−Inverting Channel + Enable
SOIC8,
SOIC8−EP
14.Typical currents with OUT at 6 V and V = 12 V.
DD
15.Thresholds proportional to an externally supplied reference voltage.
16.Automotive−qualified F085 versions are offered in SOIC8 packages, some in SOIC−8−EP package
www.onsemi.com
17
FAN3121, FAN3122
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
www.onsemi.com
18
FAN3121, FAN3122
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE D
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