FAN251030MNTXG_技术文档

DATA SHEET

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Synchronous Buck

Regulator with PMBusE,

35 A

WQFN34 5x7, 0.5P

CASE 510CL

FAN251030

MARKING DIAGRAM

Description

The FAN251030 is a highly efficient synchronous buck regulator

with digital interface, capable of operating with an input range from

4.5 V to 18 V and supporting up to 35 A load currents.

The FAN2510xx utilizes a fixed−frequency voltage−mode control

architecture to provide a synchronized constant switching frequency

while ensuring fast transient response.

$Y

FAN25

1030

AWLYYWWG

FAN251030

= Specific Device Code

Switching frequency and over−current protection can be

programmed to provide a flexible solution for various applications.

Output over−voltage, under−voltage, over−current, and thermal

shutdown protections help prevent damage to the device during fault

conditions.

$Y

A

WL

YY

WW

G

= onsemi Logo

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Designator

Features

• VIN Range: 4.5 V to 18 V

• Output Accuracy: 0.7% at 3.3 V

• PMBUS1.3.1 Compatible

ORDERING INFORMATION

See detailed ordering and shipping information on page 49 of

this data sheet.

• Accurate Voltage, Current and Thermal Telemetry Reporting

• High Efficiency: Over 96% Peak

• Continuous Output Current: 35 A

• Internal Linear Bias Regulator

• Output Voltage Range: 0.5 V to 5.5 V

• Adjustable Frequency: 200 kHz to 1.8 MHz

• Programmable Soft−Start

• Low Shutdown Current

• Internal Boot Diode

• Thermal Shutdown

• This Device is Pb−Free, Halogen Free/BFR Free, and is RoHS

Compliant

Typical Applications

• Server and Desktop Computers, Notebooks, Gaming

• Telecommunications

• High Density Power Solutions

1

Publication Order Number:

March, 2023 − Rev. 8

FAN251030MN/D

FAN251030

V_IN

0

CIN

0.1

μF

2.2

μF

0.1

μF

VIN PVIN

BOOT

VCC

PGOOD

EN

PVCC

0.1

μF

PH

V_OUT

L

SALRT

SCL

SW

PMBus

FAN2510xx

VOUT+

COUT

SDA

VOUT−

SYNC

VSET

VDIFF

ADDR

GND PGND GL GH COMP

FB

Figure 1. Application Circuit

GND

AGND

SYNC

VIN

VCC

PVCC

BOOT

PVIN

I_HS

I_LS

Current

Monitoring

SYNC

Oscillator

Freq

LDO

GH

PH

VIN

Feed−forward

VCC

I_HS

I_MON

ILIM

Ramp Generator

Ramp

BOOT

UVLO

Sleep Mode/

UVLO

EN

FB

EN

Logic core

PWM

Comparator

VCC

E/A

Level Shift

PWM

Control

SW

Bandgap

Diff Amp

DAC

ILIM

V_REF

Freq

PVCC

Deadtime

Control

VIn

VDIFF

I_MON

Vdiff

V_REF

I_LS

Logic core

PGND

Temp Sensor

ILIM

VSEN− VSEN+

COMP

SDA SCL SALERT ADDR VSET PG

GL

Figure 2. Block Diagram

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2

FAN251030

PIN CONNECTIONS

PGND

33

PGND

SW

31

PVIN

34

32

30

29 SW

SW

PVIN

1

2

3

SW

28

27

26

SW

PVIN

SW

GL

25

24

23

22

21

20

GL

PH

GH

PVCC

VIN

4

5

6

7

8

9

BOOT

GND

VCC

EN

PGND

FB

SCL

COMP

19 SDA

10

11

13

14

15

16

17

18

12

VSET GND SYNC SALRT

VDIFF

VSEN− VSEN+ PG ADDR

Figure 3. Pin Assignment, Top Transparent View (5x7 mm, 0.5 mm Pin Pitch)

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3

FAN251030

PIN FUNCTION DESCRIPTION

Pad/Pin

Name

Type

Description

1, 2, 3, 34

PVIN

Power

Power Input for the Power stage (High−side MOSFET Drain Connection).

Apply Vin voltage always with Vcc capacitor

4

5

6

PH

GH

Power

I/O

Return connection for the boot capacitor, internally connected to SW

High−side MOSFET gate monitor (do not connect anything to this pin)

BOOT

Power

Supply for high−side MOSFET gate driver. A capacitor from BOOT to PH

supplies the charge to turn on the N−channel high−side MOSFET. During the

freewheeling interval (low−side MOSFET on), the high−side capacitor is

recharged by an internal diode connected to PVCC

7, 16

8

GND

FB

Ground

I/O

Analog Ground

Inverting input to the voltage error amplifier

Output of the voltage error amplifier

I/O

9

COMP

VDIFF

VSEN−

VSEN+

PG

I/O

10

11

12

13

14

Output of the VOUT sensing differential amplifier

Negative Input of the VOUT sensing differential amplifier

Positive Input of the VOUT sensing differential amplifier

Power GOOD; open−drain output indicating VOUT is within set limits

I/O

ADDR

I/O

PMBUS address programming pin. Use a resistor (with up to 1% tolerance)

to set the address

15

VSET

I/O

VOUT pre−setting pin. Use a resistor (with up to 1% tolerance) to pre−set

the output voltage (PMBUScommand can override)

17

18

19

20

21

22

SYNC

SALRT

SDA

I/O

Synchronization input or output

PMBUSAlert pin

I/O

PMBUSData pin

SCL

I/O

PMBUS Clock pin

EN

I/O

Enable input (and PMBUSControl pin)

VCC

Power

Output of the linear regulator; Supply pin for the controller. Can NOT be

separated from PVCC. The capacitor should be always connected to this pin

23

24

VIN

Power

Power input to the linear regulator; also used in the modulator for input

voltage feed−forward. Must always be connected even if the LDO is not used

PVCC

Directly supplies power for the low−side gate driver and boot diode. This pin

and VCC can NOT be separated, or connected to the external power supply

25

GL

I/O

Low−side MOSFET gate monitor (do not connect anything to this pin)

26−31

SW

Power

Switching Node; Internally Connected to the High−side MOSFET Source and

Low−side MOSFET Drain

32, 33

PGND

Ground

Power Ground (Low−side MOSFET Source Connection),

internally connected to GND

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4

FAN251030

MAXIMUM RATINGS

All voltages with respect to GND, unless otherwise specified.

Rating (Note 1)

Symbol

Value

Unit

V

Input Voltage Range

BOOT voltage range:

referenced to GND (Note 2)

V , V

PVIN IN

−0.3 to 25

referenced to PVCC

V

BOOT

−0.3 to 26

−0.3 to 30

−0.3 to 6

V

referenced to PVCC, < 20 ns

referenced to SW, PH

referenced to PGND

−0.3 to 30

SW voltage range:

referenced to PGND

referenced to PGND, <10 ns

V

, V

−1 to 25

−5 to 28

V

SW PH

High−Side MOSFET Gate voltage range: referenced to SW, PH

V

−0.3 to 6

GH

referenced to PGND

−0.3 to 30

Low−Side MOSFET Gate voltage range:

Driver Supply Input voltage range

Controller Supply Input voltage range

Output Voltage Sense voltage range

Differential Amplifier Output voltage range

Error Amplifier Input voltage range

Error Amplifier Output voltage range

SYNC voltage range

referenced to PGND

V

−0.3 to 6

150

V

GL

V

PVCC

V

VCC

V

, V

V

SEN+

SEN−

V

DIFF

V

FB

V

COMP

V

SYNC

V

Power Good Output voltage range

Enable Input voltage range

V

PG

V

EN

Vout Setting Input voltage range

PMBUSData pin voltage range

PMBUSClock input voltage range

PMBUSAlert Output voltage range

PMBUSAddress Input voltage range

Maximum Junction Temperature

Storage Temperature Range

V

VSET

V

SDA

V

SCL

V

SALERT

V

ADDR

V

T

°C

J(max)

T

STG

−55 to 150

260

Lead Temperature Soldering Reflow (Note 3)

T

SLD

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

2. PGND is internally connected to GND.

3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

THERMAL CHARACTERISTICS

Rating

Thermal Resistance, Junction−to−Air (Note 4)

Thermal Reference, Junction−to− Case (Note 4)

Symbol

Value

14.6

1.5

Unit

°C/W

R

q

JA

R

Y

JC

4. Values are based on onsemi Evaluation Board of 2 oz copper thickness, No airflow and FR4 PCB substrate.

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5

FAN251030

RECOMMENDED OPERATING RANGE

Rating

Input Voltage

Symbol

Min

4.5

0.5

Max

18

Unit

V

in

Output Voltage

V

5.5

V

out

Continuous Output Current

I

0

35

A

Adjustable Output Voltage

EN Pin Voltage

V

0.5

0

5.5

5

V

out

V

EN

Junction Temperature

T

J

−40

125

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

ELECTRICAL CHARACTERISTICS

V

IN

= 12 V, V = 3.3 V, for typical values T = 25°C, for min/max values T = T = −40°C to 125°C; unless otherwise specified.

OUT A A J

Parameter

Test Conditions

Symbol

Min

Max

Unit

Typical

SUPPLY CURRENT

−

Quiescent Current

EN Low, not switching

I

2.8

mA

VIN,Q

LINEAR REGULATOR

Regulator Output Voltage

Regulator Current Limit

Regulator Drop Out Voltage

INTERNAL MOSFET RDS−ON (Note 5)

High Side MOSFET

V

4.75

60

−

5

−

5.25

−

V

mA

V

REG

Not for external use

I

REG

I

= 40 mA, V = 5 V

V

DROPOUT

0.3

LDO

IN

V

GS

= 5 V

−

2.8

1.3

mW

HS−RDSON

LS−RDSON

Low Side MOSFET

DIFFERENTIAL AMPLIFIER

−

V

Pin Input Impedance

R

100

kW

SEN+

G = 1

G = 0.5

G = 0.25

−

V

SEN−

50

66

78

SEN−

−

Output Sinking current capability

Output Sourcing current capability

Closed−Loop Bandwidth (Note 5)

Closed−Loop Gain

I

3

mA

DIFF(sink)

I

DIFF(source)

−

BW

2

MHz

V / V

DIFF

G = 1, for V

≤ 1.99

−

1

0.5

0.25

−

OUT

G = 0.5 for 1.99 ≤ V

≤ 3.99

−

OUT

G = 0.25, for V

≥ 3.99

−

OUT

Closed−Loop Accuracy

G = 1, V

= 600 mV, no load

V

err

−1

−0.7

1

%

OUT

G = 0.5, V

= 3.3 V, no load

−

1

OUT

G = 0.5, V

no load

= 3.3 V, 25°C,

−

0.7

G = 0.25, V

= 5 V, no load

−1

−

1

OUT

REFERENCE, V

SETTING AND MARGINING

OUT

FB Pin Voltage Accuracy

0°C ≤ T ≤ 125°C,

V

REF

%

J

V

FB

= 0.6 V, 1.65 V

−

V

Setting Range (Note 5)

V

0.5

−

5.5

−

V

mV

V

OUT

OUT,RNG

Setting and Margin Step (Note 5)

V

TM,S

1.953

3.1

OUT

−

Margin Low Default Value

V

MGL

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6

FAN251030

ELECTRICAL CHARACTERISTICS (continued)

V

IN

= 12 V, V = 3.3 V, for typical values T = 25°C, for min/max values T = T = −40°C to 125°C; unless otherwise specified.

OUT A A J

Parameter

REFERENCE, V SETTING AND MARGINING

Test Conditions

Symbol

Min

Max

Unit

Typical

OUT

−

3.4

−

Margin Low Default Value Range (Note 5)

Margin High Default Value

V

0.5

−

5.5

−

V

MGL

MGH

V

k

Margin High Default Value Range (Note 5)

Default Transition Rate

0.5

−

5.5

−

V

0.203

−

mV/ms

%

TRAN

Transition Rate Range (Note 5)

k

0.203

9.375

TRAN,RNG

10

Transition Rate Accuracy

OSCILLATOR

k

−

TRAN,ACC

Default Switching Frequency

F

540

200

600

660

kHz

SW

−

Switching Frequency Setting Range

(Note 5)

F

1800

SW,RNG

200 ≤ F

≤ 1200 kHz

−

Switching Frequency Step Size (Note 5)

F

50

100

−

kHz

%

SW

SW,ST

1200 < F

≤ 1800 kHz

SW

Switching Frequency Accuracy

FREQUENCY SYNCHRONIZATION

SYNC Input Logic HIGH

F

−10

10

SW,ACC

−

0.8

−

V

2

V

SYNC_IN_H

−

SYNC Input Logic LOW

V

SYNC_IN_L

Input HIGH Level Pulse Width

Input LOW Level Pulse Width

Synchronize Frequency (Note 5)

t

135

150

80

ns

%

HIGH_IN_MIN

−

t

LOW_IN_MIN

Percentage of the oscillator

frequency

F

120

SYNC

Transition Delay before Synchronizing to

SYNC frequency

In Number of oscillator Clock

Cycles per 2 ms time period

−

Cycles

t

64

SYNC_DL

SYNC Pin Pull down Resistance

SYNC Output Driver Pull−up Resistance

SYNC Output Driver Pull−down Resistance

SYNC Output Duty Cycle

R

100

10

12

45

−

kW

W

SYNC_PD

R

−

SYNCDRPU

SYNCDRPD

W

D

−

%

SYNC_OUT

SYNC Pin Lead Capacitance

V

OUT

= 0 V (Note 5)

C

200

pF

L_SYNC

RAMP AND PWM MODULATOR

PWM Modulator Feed−forward(Vin) Gain,

IN

k

−

10

−

PWM

V

/DV

RAMP

PWM Minimum ON Time

PWM Minimum OFF Time

ERROR AMPLIFIER

t

30

50

70

ns

ON_MIN

t

100

150

200

OFF_MIN

−

Unity Gain Bandwidth (Note 5)

DC Gain (Note 5)

G

5

78

2

10

100

10

9

MHz

dB

BW

V

FB

= 0.6 V

G

COMP Source Current

COMP Sink Current

I

mA

COMP_SRC

I

2

COMP_SNK

SOFT−START (Low side FET turns ON after V

Default TON−Rise

> 300 mV)

OUT

−

t

5

ms

SST

−

TON−Rise Range (Note 5)

t

1

20

SST,RNG

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7

FAN251030

ELECTRICAL CHARACTERISTICS (continued)

V

= 12 V, V

= 3.3 V, for typical values T = 25°C, for min/max values T = T = −40°C to 125°C; unless otherwise specified.

IN

OUT

A

J

Parameter

Test Conditions

Symbol

Min

Max

Unit

Typical

SOFT−START (Low side FET turns ON after V

> 300 mV)

OUT

−

1

−

1

−

0

−

0

−

10

−

Default TON Delay

t

1

−

ms

ONDLY

t

ONDLY,RNG

TON Delay Range (Note 5)

Default TOFF−Fall

t

5

SSP

SSP,RNG

−

TOFF−Fall Range (Note 5)

t

20

−

Default TOFF Delay

t

1

OFFDLY

OFFDLY,RNG

−

TOFF Delay Range (Note 5)

Default TON MAX FAULT LIMIT

TON MAX FAULT LIMIT Range (Note 5)

CYCLE−BY−CYCLE CURRENT LIMIT

t

10

−

t

12

−

maxFLT

t

50

maxFLT,RNG

−

t

50

ns

High−Side Current Limit Blanking Time

(Note 5)

LIMPKBLNK

−

2

−

62

15

−

I

54

−

A

Peak (High−Side) Current Limit Default

Peak (High−Side) Current Limit Range

LIMPK

I

LIMPK,RNG

−

I

= 40 A

I

−15

−

%

ns

Peak (High−Side) Current Limit Accuracy

LIMPK

LIMPK,ACC

t

60

Low− Side Current Limit Blanking Time

(Note 5)

LIMNEGBLNK

−

I

14

A

Negative (Low−Side) Current Limit Default

LIMNEG

−

I

10

24

Negative (Low−Side) Current Limit Range

AVERAGE OUTPUT CURRENT

Output Current Warning

LIMNEG,RNG

−

1

−

1

0

−

32

−

A

Output Current Warning Range (Note 5)

Output Current Fault

64

−

45

−

A

Output Current Fault Range (Note 5)

64

10

A

Average Fault Response Time Range

(Note 5)

−

ms

ENABLE

Enable Threshold

EN voltage rising

EN voltage falling

V

1.12

1.00

−

1.22

1.105

115

1.32

V

EN

Disable Threshold

V

DIS

1.195

Hysteresis

V

R

−

mV

kW

EN,HYS

−

EN Pin Internal Pull−down Resistor

EN Pin Internal Clamp Resistance

VCC UVLO

R

900

EN

V

EN

= 5 V

−

250

ENCLMP

−

3.58

−

VCC UVLO Enable Threshold

VCC UVLO Disable Threshold

VCC UVLO Hysteresis

INPUT VOLTAGE PROTECTIONS

Default VIN Turn−on Threshold

VIN Turn−on Threshold Range

VIN Turn−on Threshold Accuracy

VCC voltage rising

VCC voltage falling

V

4

4.35

−

V

CC,EN

CC,DIS

CCHYS

V

3.8

175

V

−

mV

−

3

−

10.5

8

V

IN

rising

V

6

−

V

ON

V

ON,RNG

V

−8

%

ON,ACC

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8

FAN251030

ELECTRICAL CHARACTERISTICS (continued)

V

IN

= 12 V, V = 3.3 V, for typical values T = 25°C, for min/max values T = T = −40°C to 125°C; unless otherwise specified.

OUT A A J

Parameter

Test Conditions

Symbol

Min

Max

Unit

Typical

INPUT VOLTAGE PROTECTIONS

Default VIN Turn−off Threshold

VIN Turn−off Threshold Range

−

2.5

−10

−

10

8

V

falling

V

5.5

−

V

IN

OFF

V

OFF,RNG

−

VIN Turn−off Threshold Accuracy

Default VIN Overvoltage Threshold

VIN Overvoltage Threshold Range

VIN Overvoltage Threshold Accuracy

V

%

V

OFF,ACC

V

IN

rising

V

20

−

INOV

INOV,RNG

V

18

−8

24

5

V

−

V

%

INOV,ACC

OUTPUT VOLTAGE PROTECTIONS (as a percentage of V

)

OUT

−

Default VOUT Overvoltage Threshold

V

OUT

rising

V

116

%

OOV

V

110

−

124

VOUT Overvoltage Threshold Setting

Range

OOV,RNG

−

2

108

−

%

VOUT Overvoltage Threshold Setting Step

Default VOUT Warning Threshold

V

rising

falling

V

OWRN

OUT

V

106

−

116

−

VOUT Warning Threshold Setting Range

VOUT Overvoltage Threshold Setting Step

Default VOUT Under−voltage Threshold

OWRN,RNG

2

−

V

OUV

75

−

OUT

VOUT Under−voltage Threshold Setting

Range

V

55

90

OUV,RNG

VOUT Under−voltage Threshold Setting

Step

−

5

−

%

OUTPUT POWER GOOD (AS A PERCENTAGE OF V

)

OUT

−

84

−2

−

98

2

Default PG Asserting Threshold

PG Asserting Threshold Range (Note 5)

PG Asserting Threshold Accuracy

Default PG de−asserting Threshold

PG De−asserting Threshold Range

PG De−asserting Threshold Accuracy

PG Leakage Current

V

rising

V

90

−

%

OUT

PGON

V

PGON,RNG

−

V

%

PGON,ACC

−

V

OUT

falling

V

84

−

%

PGOF

V

82

−2

−

96

2

%

PGOF,RNG

−

V

%

PGOF,ACC

−

I

1

mA

ms

mV

PG,LEAK

−

PG De−glitch Filter Duration

PG Rising Delay

t

5

PG_FLT

−

560

10

6

−

PG Falling Delay

−

PG Output Low Voltage

V

−

12

V

PG

= 70% V

= −1 mA

,

PG_L

OUT

OUTREF

I

INTERNAL BOOTSTRAP DIODE

Forward Voltage

−

2.9

−

I = 10 mA

V

0.3

−

V

F

FBOOT

Bootstrap Voltage UVLO

V

falling

rising

V

3.2

BOOT

BTUV

−

Bootstrap Voltage UVLO Hysteresis

THERMAL PROTECTION

V

0.35

BTUVHYS

−

80

−

160

−

Default Thermal Fault Threshold

Thermal Fault Threshold Setting Range

Default Thermal Warning Threshold

T rising

T

140

−

°C

J

OFF

T

OFF,RNG

T rising

J

T

OFF

115

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9

FAN251030

ELECTRICAL CHARACTERISTICS (continued)

V

IN

= 12 V, V = 3.3 V, for typical values T = 25°C, for min/max values T = T = −40°C to 125°C; unless otherwise specified.

OUT A A J

Parameter

Test Conditions

Symbol

Min

Max

Unit

Typical

THERMAL PROTECTION

−

Thermal Warning Threshold Range

Thermal Shutdown Threshold Umbrella

Thermal Shutdown Hysteresis

TELEMETRY REPORTING

Telemetry Refresh Time Interval (Note 5)

VIN Voltage Accuracy

T

70

−

150

−

°C

OFF,RNG

T rising

T

160

15

J

SHDN

SHDN,HYS

T

−

−5

−2

−

5

2

−

t

900

−

ms

%

telemetry

EN = 0

V

IN,ACC

OUT,ACC

G = 1, VSET = AGND

−

VOUT Voltage Accuracy

V

10

Output Current Accuracy

I

= 6 A to 35 A

= 600 kHz,

I

OUT

Input Current Accuracy

F

For I

−

SW

= 6 A to 35 A

OUT

−

Temperature Accuracy (Note 5)

PMBUSINTERFACE (Note 5)

Pin Capacitance (SCL, SDA)

0°C − 125°C

T

ACC

−5

5

°C

−

10

400

−

pF

kHz

ms

PMBUS Operating Frequency Range

10

1.3

−

Bus Free Time between START and Stop

Hold Time after Repeated START

Repeated START Setup Time

−

0.6

0

ms

−

ns

Data Hold Time (receive & transmit modes)

Data Setup Time

−

100

25

−

ns

−

Detect Clock Low Timeout

35

10

ms

−

Cumulative Clock Low Master Extend Time

−

25

Cumulative Clock Low Slave Extend Time

Clock Low Time

−

1.3

−

Clock High Time

0.6

−

50

120

−

ms

ns

V

−

SCL/SDA Fall Time

−

SCL/SDA Rise Time

1.95

−

SCL/SDA High/Rising Threshold

SCL/SDA Low/Falling Threshold

SCL/SDA Threshold Hysteresis

Noise Spike Suppression Time

−

0.8

−

V

−

0.6

−

V

0

50

ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low

J

A

duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

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10

FAN251030

TYPICAL PERFORMANCE CHARACTERISTICS

V

IN

= 12 V, V

= 3.3 V, F = 600 kHz, L = 1 mH (Note 6), C

= 1000 mF, T = 25°C, unless otherwise indicated.

OUT

sw

OUT

A

100

95

90

85

80

75

0.6

0.4

0.2

0.0

5.0 VOUT

3.3 VOUT

1.8 VOUT

1.2 VOUT

1.0 VOUT

0.8 VOUT

−0.2

5.0 VOUT

3.3 VOUT

−0.4

1.8 VOUT

1.0 VOUT

−0.6

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

Load Current (A)

Figure 4. Efficiency

Figure 5. Load Regulation

FAN251030, Fsw=600kHz

12Vin, 3.3Vout

40

35

30

25

20

15

10

5

5.0 VOUT

3.3 VOUT

1.0 VOUT

Iout=35A, No Airflow

1 hour soak time

Max Temp = 98.5C

EVB=2oz copper

0

25

45

65

85

105

125

Ambient Temperature, T (°C)

A

Figure 6. Thermal Safe Operating Area,

No Airflow, PCB: 2 oz. Cu

Figure 7. Thermal Image, No Airflow, I_OUT= 35 A

Figure 8. 5 msec Start−Up, No Load

Figure 9. 5 msec Start−Up with 50% Pre−Bias

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11

FAN251030

Figure 10. Load Transient 0−15 A, 10 A/ms

Figure 11. Load Transient 15−30 A, 10 A/ms

6. Tests conducted using L = 1.0 mH (Pulse PA4343.102NLT)

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12

FAN251030

Table 1. PMBUS^TMADDRESS SETTING

ADDR Resistor

APPLICATION INFORMATION

The FAN2510xx is a high−efficiency synchronous buck

converter with integrated controller, driver and two power

MOSFETs. It can operate over a 4.5 V to 18 V input voltage

range, and delivers up to 35 A continuous load current.

FAN2510xx uses a voltage mode PWM control scheme

with input voltage feed−forward feature for wide input

voltage range. A differential amplifier monitors the output

voltage and feeds the high bandwidth error amplifier that

generates the control signal for the pulse width modulation

block. By adjusting the external compensation network, the

system performance can be optimized based on the

application parameters. The Low−Side FET turns ON after

Value (kW)

0 (short)

0.845

1.3

PMBUS Address (h)

Offset Address (h)

−

0F

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

−

Base+00

Base+01

Base+02

Base+03

Base+04

Base+05

Base+06

Base+07

Base+08

Base+09

Base+0A

Base+0B

Base+0C

Base+0D

0F

1.78

2.32

2.87

3.48

4.12

4.75

V

OUT

> 300 mV.

5.49

The switching frequency is set by PMBUSprogramming

6.19

and can be synchronized to an external clock signal.

The high−side MOSFET current is sensed for the peak

current limiting function and the output voltage is reduced

in current limiting condition. Other protection functions

include over temperature warning and shut−down, output

voltage under− and over−voltage protections and warning,

output over−current warning, and input over−voltage (all

adjustable by PMBUS).

6.98

7.87

8.87

10

≥12.4

V_OUTVoltage Pre−set

A resistor between the VSET pin and GND (with up to 1%

tolerance) sets the output voltage without having to program

it through PMBUS. It offers 15 different values (see table 2

At the beginning of each switching cycle, the clock signal

initiates a PWM signal to turn on the high−side MOSFET,

and at the same time, the ramp signal starts to rise up. A reset

pulse is generated by the comparator when the ramp signal

intercepts the COMP signal. This reset pulse turns off the

high−side MOSFET and turns on the low−side MOSFET

until the next clock cycle comes. If the current limit is hit, the

high− side MOSFET is turned off until the next PWM signal

(cycle by cycle current limit protection). When certain fault

conditions are met, the device can enter a protection mode

(hiccup or latch−off) to further protect itself.

for details). The V

setting can be overridden through

OUT

PMBUS programming. The V

Voltage Pre−set feature

OUT

can be enabled/disabled using MFR MODE (C8h) bit 0,

which is enabled (0) by default.

Table 2. V_OUTPRESET SETTING

VSET Resistor

Value (kW)

V

OUT

preset value (V)

Short

0.6

0.9

0.95

1

PMBUSAddress

0.845

A resistor between the ADDR pin and GND (with up to

1% tolerance) sets the PMBUS offset address, enabling

14 different possible addresses (see Table 1 for details). The

offset address is added to an adjustable base address with

PMBUS. The base section is programmable through MTP.

1.3

1.78

2.32

2.87

1.05

1.2

1.25

1.5

1.8

2.1

2.5

3.3

5

3.48

4.12

4.75

5.49

6.19

6.98

7.87

8.87

10 & greater value

0.8

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13

FAN251030

Output Over−current Protection

Output Voltage Monitoring and Protection

The FAN2510xx monitors the current in both the

high−side and low−side MOSFETs, and offers several

different sets of protections and warning:

The FAN2510xx monitors the output voltage and offers

several different sets of protections and warnings:

Under−voltage Protection

High−side FET Positive Cycle−by−cycle Peak Current

Limit with Programmable Delay and Response

• Limits the peak current in the high−side FET at each

cycle to a level adjustable between 2 A and 62 A (using

the IOUT_OC_FAULT_LIMIT command)

• The duration during which it is allowed to run in

cycle−by− cycle current limitation before going into

fault protection mode is adjustable from 0 to 10ms

(using the IOUT_OC_FAULT_RESPONSE command)

• The fault protection mode is programmable, and can be

chosen between “ignore without VOUT UVLO”,

“ignore with VOUT UVLO”, “1−second hiccup” or

“latch−off” (using the IOUT_OC_FAULT_RESPONSE

command)

• An additional limit equal to 130% of the level set by

IOUT_OC_FAULT_LIMIT immediately terminates

switching if reached. This fault can be ignored: the

FAN2510xx is latched off if

• The threshold is adjustable as a percentage of the

regulated output voltage, between 55% and 90% (using

the PCT_VOUT_LIMIT command)

• The amount of filtering is adjustable (between 5µs and

10µs) and the fault response is programmable (between

“ignore”, “1−second hiccup” or “latch−off”) using the

VOUT_UV_FAULT_RESPONSE command

Under−voltage Warning

• Based on the output voltage measured by the telemetry

• The threshold is adjustable between 0.1 V and 5.5 V

(using the VOUT_UV_WARN_LIMIT command)

Over−voltage Protection

• The threshold is adjustable as a percentage of the

regulated output voltage, between 110% and 124%

(using the PCT_VOUT_LIMIT command)

• The amount of filtering is adjustable (between 5µs and

10 ms) and the fault response is programmable (between

“ignore”, “1−second hiccup” or “latch−off”) using the

VOUT_OV_FAULT_RESPONSE command

IOUT_OC_FAULT_RESPONSE is “latch−off”,

otherwise a 1−second hiccup is applied.

Average Output Current Fault with Programmable Delay

and Response

Over−voltage Warning

• Switching stops when V

goes above this warning

OUT

• Based on the output current measured by the telemetry

threshold, and resumes when back in regulation

• The threshold is adjustable as a percentage of the

regulated output voltage, between 106% and 116%

(using the PCT_VOUT_LIMIT command), and should

be always set to the less than over−voltage protection

threshold

• Does not limit the cycle−by−cycle current

• The threshold is adjustable between 1 A and 50 A

(using the IOUT_AVG_FAULT_LIMIT command)

• The duration during which the FAN2510xx is allowed

to run above the threshold before going into fault

protection mode is adjustable from 0 to 10ms (using the

IOUT_AVG_FAULT_RESPONSE command)

• The fault protection mode is programmable, and can be

chosen between “ignore”, “1−second hiccup” or

“latch−off”

• The behavior can be changed to turn on the low−side

FET to actively pull V

down (by using

OUT

MFR_MODE_SETTINGS).

Power GOOD Signal and Pin

• The PGOOD signal is held low during soft−start and

soft−shutdown.

• The power good signal is high whenever V

regulation, after the end of soft−start

(using the IOUT_AVG_FAULT_RESPONSE

command)

is in

OUT

Average Output Current Warning

• Based on the output current measured by the telemetry

• The rising threshold is adjustable as a percentage of the

regulated output voltage, between 84% and 98% (using

the PCT_VOUT_PGOOD command)

• The threshold is adjustable between 1 A and 64 A

(using the IOUT_OC_WARN_LIMIT command)

• The falling threshold is adjustable as a percentage of

the regulated output voltage, between 82% and 96%

(using the PCT_VOUT_ PGOOD command)

Low−side FET Negative Cycle−by−cycle Current Limit

• Limits the negative low−side FET peak current at each

cycle to a level adjustable between 10 A and 24 A

(using the IOUT_UC_FAULT_LIMIT command)

• The power Good signal also goes low when V

above the over−voltage protection threshold

is

OUT

Output Voltage Margining

FAN2510xx can be set for output voltage margin by

applying positive (margin_high) or negative (margin_low)

offset commands during operation.

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14

FAN251030

Scale loop changes and back to back margining for the

VIN_ON command). For less than 4.5 V, down to 3 V,

output changes are not supported in FAN2510xx. New offset

can be applied long enough until the previous margining is

completed. In the same scale loop, the big output voltage

changes with the highest slew rate is not recommended if

OVP option is enabled during the margining.

external V should be used.

CC

Turn−off Threshold

The FAN2510xx shuts down if VIN is below this

threshold, adjustable between 4 V and 10 V (using the

VIN_OFF command). For less than 4 V, down to 3 V,

Input SYNC Function

external V should be used.

CC

Two parts can be synchronized from an input source as

master/slave with 0° (in phase) or 180° (out phase) phase

shift. When device acts as master, it sends out a 45% duty

cycle clock through SYNC pin with rising edge sync’d with

its own switching cycle. Slave device switching node’s

rising edge lags behind either SYNC CLK’s rising edge (in

phase) or falling edge (out of phase) by 200 ns.

The slave is synchronized to SYNC CLK after it’s

validated over 64 clock cycles. Then, SYNC_CLK is

compared to the internal clock. If outside the 20%

frequency window when compared to the internal clock, the

device exits slave mode and relies on its internal clock rate.

Refer to INTERLEAVE (Reg37h) section for additional

setting details.

Temperature Monitoring and Protection

The FAN2510xx monitors its die temperature and offers

several different sets of protections and warnings:

Over−temperature Protection

• Based on the temperature measured by the telemetry

• The threshold is adjustable between 80°C and 160°C

(using the OT_FAULT_LIMIT command)

• The fault protection mode is programmable, and can be

chosen between “ignore”, “recovery”, “1−second

hiccup” or “latch−off”

(using the OT_FAULT_RESPONSE command)

• In case the die temperature reaches T

(based on

SHDN

the analog sensor reading), the FAN2510xx

immediately shuts of (including the LDO regulator),

even if the fault response is set to “ignore”

Input Voltage Monitoring and Protection

The FAN2510xx monitors the input voltage and offers

several different sets of protections and warnings:

Over−temperature Warning

• Based on the temperature measured by the telemetry

• The threshold is adjustable between 70°C and 150°C

(using the OT_WARN_LIMIT command)

Over−voltage protection

• The threshold is adjustable between 18 V and 24 V

(using the VIN_OV_FAULT_LIMIT command)

• The amount of filtering is adjustable (between 5 ms and

10 ms) and the fault response is programmable (between

“ignore”, “recovery”, “1−second hiccup” or

“latch−off”) using the VIN_OV_FAULT_RESPONSE

command

Protection Summary

The FAN2510xx includes various protection features,

with different behaviors and options. See Table 3 for a

summary, and dedicated sections for more details about each

one.

Turn−on Threshold

The FAN2510xx only starts switching if VIN is above this

threshold, adjustable between 4.5 V and 10.5 V (using the

www.onsemi.com

15

FAN251030

Table 3. SUMMARY OF PROTECTION FUNCTIONS

Protection name

Adjustability

Default Behavior

Options

HS FET and LS FET both turn off un- HS FET turns off but LS FET turns

til back in regulation on until back in regulation

Output overvoltage warning

PMBUS

Switching stops, then enters protec- Ignore, hiccup or latch−off; delay

Output overvoltage fault

Output under−voltage fault

Input overvoltage fault

PMBUS

tion mode

Switching stops, then enters protec- Ignore, hiccup or latch−off; delay

tion mode

Switching stops until back in range

Ignore, resume when back in range,

hiccup or latch−off

Input under−voltage

VCC under−voltage

BOOT under−voltage

PMBUS

no

Switching stops, part is reset

HS FET turns off, LS FET turns on

no

regularly to refresh V

fault clears

, until the

BOOT

Average output current fault

Peak HS FET current fault

PMBUS

Switching stops, then enters

protection mode

Ignore, hiccup or latch−off; delay

Cycle−by−cycle current limit, enters Ignore, hiccup or latch−off; delay

protection mode after delay

Peak HS FET current extreme fault

Peak negative LS FET current fault

Switch node fault

PMBUS

no

Enters protection mode

Ignore, hiccup or latch−off

no

Cycle−by−cycle current limit

Switching stops, then enters

protection mode

Trim option to change to latch off

Over temperature Fault

Ignore, resume when back in range

PMBUS

no

Switching stops until back in range

or latch−off

Umbrella Thermal shutdown

Switching stops and VCC LDO turns no

off, until back in range

Start−up fault (VOUT UV not met at

the end of timer)

PMBUS

Switching stops, then enters

protection mode

Ignore, hiccup or latch−off

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16

FAN251030

Telemetry

The FAN2510xx constantly measures its input voltage,

input current, output voltage, output current and die

temperature and reports it in dedicated PMBUS registers.

Each measured value is refreshed every 900 ms.

400 kHz bus timing requirements. Communication over the

PMBUS interface supports Packet Error Checking (PEC). If

the master provides the clock pulses for the PEC byte, PED

is used. If the additional clock pulses are not present before

a STOP, the PEC is not used. PMBUS has several transaction

formats. The formats that are supported in FAN2510xx are

listed below:

20

15

10

5

PMBUS Send Byte

The send byte transaction is used to send a simple

command to the device. A send byte transaction transfers a

command with no data. The CLEAR_FAULTS command

that clears the current fault flags present in the system is an

example of such a command. A start bit, followed by the

7−bit slave address and finished by a write bit (0−value) to

indicate a write make up the first stage of the transaction. If

the slave ACKs the address, then the host sends the 8−bit

command followed by a stop condition. The format is given

below.

0

−5

−10

−15

−20

0

5

10

15

20

25

30

35

Load Current (A)

Figure 12. Typical I_OUTTelemetry Accuracy

PMBUS General Description

The PMBUS specification can be found at

www.pmbus.org. FAN2510xx support both the 100 kHz and

PMBUS Send Byte

1

7

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE

A

P

PMBUS Write Byte

transaction. Similar to the send byte transaction above, the

series of start bit, 7−bit slave address with write bit

(0−value), command byte, and finally the 8−bit data byte.

The format is given below.

The write byte transaction is used to send single byte data

to the chip. The OPERATION command that configures the

operation of the device is an example of this type of

PMBUS Write Byte

1

7

1

8

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE

A

DATA_BYTE

A

P

PMBUS Write Word

command, the only difference is that after the third

acknowledge (the low data byte) the high byte is sent in

addition.

The write word transaction is used to send a single word

of data (two bytes) to the chip. The TON_DELAY command

is an example of such a transaction. Similar to the write byte

PMBUS Write Word

1

7

1

8

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE

A

DATA_BYTE LOW

A

DATA_BYTE HIGH

A

P

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17

FAN251030

PMBUS Read Byte

following that is the address and read bit send the signal to

the device to return data for the specified command code.

The slave responds by transmitting the byte value requested.

The read byte starts out like a normal I2C write transaction

by sending the address and the write bit. The second byte

contains the command code, then a repeated start is sent, and

PMBUS Read Byte

1

7

1

8

1

7

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE

A

Sr

SLAVE ADDRESS

Rd

A

DATA BYTE

N

P

PMBUS Read Word

repeated start is sent, and following that is the address and

read bit signaling the device to return data for the specified

command code. The slave responds by transmitting the

value requested low byte first and high byte last.

The read word transaction also starts out like a normal I 2C

write transaction by sending the address and the write bit.

The second byte contains the command code, then a

PMBUS Read Word

1

7

1

8

1

7

1

8

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE

A

Sr

SLAVE ADDRESS

RD

A

DATA BYTE

A

DATA BYTE HIGH

N

P

PMBUS Block Write

the message. FAN2510xx allows only 1 byte. The byte count

field can only have the value 01, followed by the one byte of

data.

The Block Write begins with a slave address and a write

condition. After the command code the host issues a byte

count which describes how many more bytes will follow in

PMBUS Block Write

1

7

1

8

1

8

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE

A

BYTE COUNT = 1

A

DATA BYTE

A

P

PMBUS Block Read

preceding the STOP condition signifies the end of the read

transfer.

FAN2510xx allows only 1 byte. The byte count field can

only have the value 01, followed by the one byte of data.

A Block Read differs from a block write in that the

repeated START condition exists to satisfy the requirement

for a change in the transfer direction. A NACK immediately

PMBUS Block Read

1

7

1

8

1

7

1

8

1

8

1

S

SLAVE ADDRESS WR

A

COM-

MAND_CODE

A

Sr

SLAVE ADDRESS RD

A

BYTE COUNT = 1

A

DATA BYTE

A

P

Packet Error Checking (PEC)

the input bit stream with a fixed CRC polynomial. The PEC

byte is calculated on all bytes in the I²C transaction including

device address and read/write. PEC does not include start,

stop, ACK/NACK, and repeated start bits.

PEC is optionally implemented in PMBUS devices, but is

highly recommended due to the critical nature of data

validity in power−management systems. Packet Error Code

(also PEC) bytes are generated using the popular CRC−8

algorithm that is based on performing XOR operations on

PMBUS Send byte with PEC:

PMBUS Send Byte with PEC

1

7

1

8

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE

A

PEC BYTE

A

P

PMBUS Write Byte with PEC:

PMBUS Write Byte with PEC

1

7

1

8

1

8

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE

A

DATA_BYTE

A

PEC BYTE

A

P

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18

FAN251030

PMBUS Write Word with PEC:

PMBUS Write Word with PEC

1

7

1

8

1

8

1

8

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE A DATA_BYTE LOW

A

DATA_BYTE HIGH

A

PEC BYTE

A

P

PMBUS Read Byte with PEC:

PMBUS Read Byte with PEC

1

7

1

8

1

7

1

8

1

8

1

S

SLAVE ADDRESS WR

A

COMMAND_CODE A Sr SLAVE ADDRESS RD

A

DATA BYTE

A

PEC BYTE

A

P

PMBUS Read Word with PEC:

PMBUS Read Word with PEC

1

S

7

1

A

8

1

A

1

7

1

A

8

1

8

1

A

8

1

A

1

P

SLAVE ADDRESS WR

COMMAND_CODE

Sr SLAVE ADDRESS RD

DATA BYTE LOW

A

DATA BYTE

HIGH

PEC

BYTE

PMBUS Block Write with PEC:

PMBUS Block Write with PEC

1

7

1

8

1

8

1

8

1

8

1

S

SLAVE ADDRESS

WR

A

COMMAND_CODE

A

BYTE COUNT =1

A

DATA BYTE

A

PEC BYTE

A

P

PMBUS Block Read with PEC:

PMBUS Block Read with PEC

1

7

1

8

1

7

1

8

1

8

1

8

1

S

SLAVE

ADDRESS

WR

A

COMMAND_CODE

A

Sr

SLAVE

ADDRESS

RD

A

BLOCK COUNT = 1

A

DATA

BYTE

A

PEC BYTE

A

P

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19

FAN251030

PMBUS COMMAND LIST (Note 7)

Default

Value

Address

01h

PMBUS Command Name

OPERATION

Type

R/W

Range

Step

Default

Comments

−

0

Immediate off

Turn on with

enable pin

02h

ON_OFF_CONFIG

8’h 17

03h

10h

CLEAR_FAULTS

Write

R/W

−

WRITE_PROTECT

8’h 00

Enable all

writes

15h

16h

STORE_USER_ALL

Write

−

RESTORE_USER_ALL

Write

Read

−

19h

1Bh

CAPABILITY

B0h

PEC supported, 400 kHz max,

SMBALERT# supported, linear

formats, AVSBUS not supported

No alert

masked

All faults can be individually

masked

SMBALERT_MASK

Write

−

20h

21h

24h

25h

VOUT_MODE

Read

R/W

−

1.953 mV

17h

−

VOUT_COMMAND

VOUT_MAX

0.5 V to 5.5 V

1.953 mV 16’h 0B00

1.953 mV 16’h 06CD

5.5 V

3.4 V

VOUT_MARGIN_ HIGH

R/W

26h

27h

VOUT_MARGIN_ LOW

0.5 V to 5.5 V

1.953 mV 16’h 0667

3.2 V

R/W

VOUT_TRANSI-

TION_RATE

0.203 to 9.375 mV/ms

1.953 mV 16’h D00D 0.203 mV/ms 4 options allowed: 0.203, 1.953,

2.9218, 9.375 mV/ms

29h

33h

35h

VOUT_SCALE_LOOP

FREQUENCY_SWITCH

VIN_ON

R/W

0.25 to 1

200 kHz to 1.8 MHz

3 V to 10.5 V

0.25

16’h F002

0.5

600 kHz

6 V

3 options allowed: 0.25, 0.5, 1

50−100 kHz 16’h 092C

0.5 V

16’h F80C

16’h F80B

16’h 0000

36h

37h

VIN_OFF

R/W

2.5 V to 10 V

4 options

5.5 V

INTERLEAVE

Standalone Standalone, Master, Slave 0°,

Slave 180°

41h

VOUT_OV_FAULT_

RESPONSE

R/W

ignore, latch−off, hiccup

−

8’h 40

Latch−off

Adjustable filter

43h

45h

VOUT_UV_WARN_LIMIT

R/W

0.1 V to 5.5 V

1.953 mV 16’h 0067

0.2 V

VOUT_UV_FAULT_ RE-

SPONSE

Ignore, latch−off, hiccup

−

2 A

−

8’h 40

16’h 081B

8’h 80

Latch−off

Adjustable filter

46h

47h

IOUT_OC_FAULT_LIMIT

R/W

2 A to 62 A

4 options

54 A

Sets cycle−by−cycle peak current

limit in HSFET

IOUT_OC_FAULT_ RE-

SPONSE

Latch−off

Ignore w/o V

OUT

uv, ignore with

OUT

V

uv, latch−off, hiccup

4Ah

4Bh

IOUT_OC_WARN_LIMIT

IOUT_UC_FAULT_LIMIT

R/W

1 A to 64 A

62.5 mA

2 A

16’h E200

16’h 000E

32 A

14 A

Sets average output current warn

10 A to 24 A

Sets negative cycle−by−cycle

peak current limit in LSFET

4Fh

50h

OT_FAULT_LIMIT

R/W

80°C to 160°C

1°C

16’h 008C

8’h C0

140°C

OT_FAULT_RESPONSE

Ignore, hiccup,

latch−off, recovery

−

recovery

Adjustable filter

51h

55h

56h

OT_WARN_LIMIT

R/W

70°C to 150°C

1°C

2 V

−

16’h 0073

16’h 080A

8’h C0

115°C

20 V

VIN_OV_FAULT_LIMIT

18 V to 24 V

VIN_OV_FAULT_

RESPONSE

ignore, hiccup, latch−off,

recovery

60h

61h

62h

TON_DELAY

R/W

1 ms to 10 ms

1 ms to 20 ms

0 ms to 50 ms

1 ms

2 ms

16’h 0001

16’h 0005

16’h 0806

1 ms

5 ms

TON_RISE

TON_MAX_FAULT_LIMIT

12 ms

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20

FAN251030

PMBUS COMMAND LIST (Note 7) (continued)

Default

Value

Address

PMBUS Command Name

Type

Range

Step

Default

Comments

63h

TON_MAX_FAULT_

RESPONSE

ignore, latch−off, hiccup

8’h 80

Latch−off

R/W

64h

65h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

80h

88h

89h

8Bh

8Ch

8Dh

95h

98h

99h

TOFF_DELAY

R/W

0 ms to 10 ms

1 ms

16’h 0000

16’h 0005

0 ms

TOFF_FALL

1 ms to 20 ms

1 ms

5 ms

−

STATUS_BYTE

STATUS_WORD

STATUS_VOUT

STATUS_IOUT

STATUS_INPUT

STATUS_TEMPERATURE

STATUS_CML

Read

Block R/W

−

STATUS_MFR_SPECIFIC

READ_VIN

−

0 to 25 V

0 to 64 A

0 to 5.5 V

0 to 64 A

−40°C to 175°C

200 kHz to 2.5 MHz

−

31.25 mV

62.5 mA

1.953 mV

62.5 mA

1°C

−

READ_IIN

−

READ_VOUT

−

READ_IOUT

−

READ_TEMPERATURE

READ_FREQ

−

1 kHz

−

PMBUS_REVISION

MFR_ID

8’h 33

33h

PMBUS rev 1.3

Block R/W format,

−

16’h 3001

3001h

The LSB byte can only be 01(h)

9Ah

9Bh

9Eh

MFR_MODEL

MFR_REVISION

MFR_SERIAL

Block R/W

−

16’h 3001

16’h 4X01

16’h 0001

3001h

4X01h

0001h

Block R/W format,

The LSB byte can only be 01(h)

Block

Read

Block R/W format,

The LSB byte can only be 01(h)

Block R/W

Block R/W format,

The LSB byte can only be 01(h)

A4h

A5h

ADh

MFR_VOUT_MIN

MFR_VOUT_MAX

IC_DEVICE_ID

Read

−

16’h 0100

16’h 0B01

16’h 4001

0.5

5.5

Block

Read

4001h

Block R format,

The LSB byte can only be 01(h)

AEh

C4h

IC_DEVICE_REV

Block

Read

−

16’h 4001

8’h 80

4001h

Block R format,

The LSB byte can only be 01(h)

IOUT_AVG_FAULT_

RESPONSE

R/W

ignore, hiccup, latch−off

Latch−off

Adjustable delay

C5h

C6h

IOUT_AVG_FAULT_LIMIT

PCT_VOUT_LIMIT

R/W

1 A to 64 A

62.5 mA

2%

16’h E2D0

16’h 06E0

45 A

Sets OCP average current limit

110% to 124%

116%

Replaces

VOUT_OV_FAULT_LIMIT

R/W

106% to 116%

55% to 90%

2%

5%

108%

75%

Replaces

VOUT_OV_WARN_LIMIT

Replaces

VOUT_UV_FAULT_LIMIT

2%

C7h

PCT_VOUT_PGOOD

R/W

84% to 98%

82% to 96%

8’h 19

90%

84%

Replaces POWER_GOOD_ON

Replaces POWER_GOOD_OFF

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21

FAN251030

PMBUS COMMAND LIST (Note 7) (continued)

Default

Value

Address

PMBUS Command Name

Type

Range

Step

Default

Comments

C8h

MFR_MODE_SETTINGS

R/W

CCM,

−

8’h A0

CCM, Enable Enables VSET pin setting for

VSET pin, LS VOUT, and enables LSFET turn−

FET OFF at on at OV_WARN.

Enable/Disable VSET pin,

turn on/off LS FET at

OV_WARN

Bits 7:4 are used for IMON HSD

RIIN programmability.

C9h

CAh

7’h10

10h

MFR_PMBUS_BASE

MFR_ID2

R/W

Sets the PMBUS base address

R/W Word format,

16’h 4F4E

4F4Eh

MFR_ID2 register is added for

customers who need 16 bits of

MFR ID. MTP bits allocated for all

16 bits

7. The regulation should be always disabled when:

− Writing commands that change device settings.

− Accessing the MTP using STORE_USER_ALL & RESTORE_USER_ALL commands.

− The device should be discarded, If #ALERTB pad is pulled low during startup and indicates the MTP programming Fault (Bit#1 of

STATUS_MFR_SPECIFIC).

PMBUS Commands Details

OPERATION (01h)

The OPERATION command is one byte command used

• Select whether fault conditions caused by margining are

to configure the operational state of the converter, in

conjunction with input from the ENABLE pin.

The OPERATION command is used to:

• Turn the PMBUS device output on and off with

commands sent over the PMBUS

ignored or acted upon

• Select whether the converter powers down immediately

or follows the programmed TOFF_DELAY and

TOFF_FALL commands when commanded to turn off

the output

• Select the margin state of the device (margin off,

margin high, margin low)

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command.

Operation Command Bit Number

Device State/Response

Bit <5:4> Bit <3:2>

Bit 7 ON/

Voltage

Margin

Fault

Bit 6 Turn

OFF

Output Voltage

Command

OFF

Command

Bit < 1:0>

Not Used

Behavior

Source Response

Behavior

Power OFF Behavior

On/Off

Device Response

Source

R/W

R

(reads 00

only)

0

1

XX

Off

Immediate Off

N/A

Immediate OFF

Power down sequencing

Use TOFF_DELAY &

TOFF_FALL for shutdown

1

X

01

10

XX

On

VOUT_MAR

GIN_LOW

Ignore faults when margined

N/A

Act on faults when margined

VOUT_MAR

GIN_LOW

1

X

10

00

01

10

XX

On

Ignore faults when margined

VOUT_MAR

GIN_HIGH

VOUT_MAR

GIN_HIGH

Act on faults when margined

XX

VOUT_CO

MMAND

Regulate to VOUT commanded value

List if all Invalid Data Operation Bits<7:2>

100100

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22

FAN251030

110100

100111

110111

101000

111000

101011

111011

NOTE: Invalid data fault flag gets set if invalid data is sent. Any data other than the data listed above is accepted.

ON_OFF_CONFIG (02h)

The ON_OFF_CONFIG command is one byte command.

This command configures the combination of ENABLE pin

input and serial bus commands needed to turn the unit on and

off. This includes how the unit responds when power is

applied. The default response for any PMBUS device is

specified by the device manufacturer.

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command.

GENERIC STRADDLE TABLE

R/W

Bit

access Number

Default

000

Purpose

Bit Value

Meaning

R/W

[7:5]

4

0

1

Reserved

1

Chip turns on when VCC is present

Sets the default to either operate any

time power is present or for the on/off

to be controlled by ENABLE pin and

serial bus commands

Chip does not turn on until commanded by the

ENABLE pin and OPERATION command

(as programmed in bits [3:0])

0

1

R/W

3

2

Controls how the unit responds to

Bit [7] of OPERATION command is ignored

0

1

commands received via the serial bus

Bit[7] of the OPERATION command needs to be

high and depending on Bit [2] of ON_OFF_

CONFIG, the unit may also require the ENABLE

pin to be asserted for the chip to start.

Controls how the unit responds to the

ENABLE pin

0

1

Unit ignores the ENABLE pin (on/off controlled

only by the OPERATION command)

The ENABLE pin needs to be asserted to start

the unit.

Depending on Bit [3] of ON_OFF_CONFIG, the

OPERATION command may also be required to

instruct the chip to start

Polarity of the ENABLE pin

0

Active low (Pull pin low to turn on the chip)

– Not Supported

1

R/W

1

0

1

0

Active high (Pull high to turn on the chip)

ENABLE pin action when commanding

the unit to turn off

Use the programmed turn off delay

(TOFF_DELAY) and fall time (TOFF_FALL)

1

Turn off the output immediately

ON_OFF_CONFIG Valid

data Bits<4:1>

Turn on behavior

Turn on any time power is up

0XX1

1011

1101

Turn on with ENABLE pin ( Default setting)

Turn on with the PMBus bit

(Bit 7 OPERATION command)

1111

Tunr on when both ENABLE pin and PMBus bit

#7 of OPERATION command are high

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23

FAN251030

CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is used to clear any fault

bits that have been set. This command clears all bits in all

status registers simultaneously. At the same time, the device

negates (clears, releases) its SMBALERT# signal output if

the device is asserting the SMBALERT# signal.

The CLEAR_FAULTS command does not cause a unit

that has latched off for a fault condition to restart. Any

device that has shut down due to a fault condition remains

off until:

• 00010000b indicates that bit [4] is to be cleared and all

other bits are to be unchanged,

• 01100010b indicates that bits [6], [5], and [1] are to be

cleared and all other bits are to be unchanged

• 11111111b, or FFh, indicates all bits are to be cleared

WRITE_PROTECT (10h)

The WRITE_PROTECT command is used to control

writing to the PMBUS device. The intent of this command

is to provide protection against accidental changes. This

command is not intended to provide protection against

deliberate or malicious changes to a device’s configuration

or operation. All supported commands may have their

parameters read, regardless of the WRITE_PROTECT

settings. This command has one data byte, described in

below table.

• A RESET signal (if one exists) is asserted,

• The output is commanded through the CONTROL pin,

the OPERATION command, or the combined action of

the CONTROL pin and OPERATION command, to

turn off and then to turn back on, or

• Bias power (VCC) is removed from the PMBUS device

If a device receives a data byte that is not listed in the table,

then the device shall treat this as invalid data, declare a

communications fault. If a PMBUS device receives

unsupported data, the response is that the device shall:

• Flush or ignore the received command code and any

received data,

If the fault is still present when the bit is cleared, the fault

bit shall immediately be set again and the host notified by the

usual means.

Clearing Individual Bits

Any or all of the bits in any status register except

STATUS_BYTE and STATUS_WORD can be directly

cleared by issuing the status command with one data byte

that is written. The data byte is a binary value. A 1 in any bit

position indicates that bit is to be cleared, if set, and

unchanged if not set. Examples of data bytes:

• Set the CML bit in the STATUS_BYTE,

• Set the Invalid or Unsupported Data Received bit in the

STATUS_CML register

Data Byte Value

Meaning

1000_0000

0100_0000

0010_0000

Disable all writes except to the WRITE_PROTECT command

Disable all writes except to the WRITE_PROTECT and OPERATION commands

Disable all writes except to the WRITE_PROTECT, OPERATION,

ON_OFF_CONFIG and VOUT_COMMAND commands

0000_0000

Enable writes to all commands (default)

Any other data other than given in the above table will

cause an invalid data fault. The contents of this register can

be stored to nonvolatile memory using the

STORE_USER_ALL command.

Store memory (MTP). It is permitted to use the

STORE_USER_ALL command while the device is

operating. However, the device may be unresponsive during

the copy operation with unpredictable, undesirable or even

catastrophic results. This command is not allowed until the

initial MTP reading is done during startup. This command,

once received, takes ~110 ms to complete successfully.

This command has no data bytes, and it is write only.

STORE_USER_ALL (15h)

The STORE_USER_ALL command instructs the

PMBUS device to copy the entire contents of the Operating

Memory to the matching locations in the non−volatile User

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24

FAN251030

RESTORE_USER_ALL (16h)

initial MTP reading is done during startup. This command

once received takes ∼2.5 ms to complete successfully.

This command has no data bytes, and it is write only.

The RESTORE_USER_ALL command instructs the

PMBUS device to copy the entire contents of the

non−volatile User Store memory (MTP) to the matching

locations in the Operating Memory. The values in the

Operating Memory are overwritten by the value retrieved

from the User Store. This command is allowed only when

output is disabled. This command is not allowed until the

CAPABILITY (19h)

This command provides a way for a host system to

determine some key capabilities of a PMBUS device. There

is one data byte formatted as shown in the below Table. This

command is read only and returns 1011_0000.

Bits

R/W Access

Default

Description

Value

0

Meaning

7

Read only

1

Packet Error Checking not supported

Packet Error Checking is supported

Maximum supported bus speed is 100 kHz

Maximum supported bus speed is 400 kHz

Maximum supported bus speed is 1 MHz

Reserved

Packet Error

Checking

1

6:5

Read only

01

1

Maximum Bus

Speed

00

01

10

11

0

4

ALERT#

The device does not have a ALERT# pin and does

not support the PMBus Alert Response Protocol

1

The device does have a ALERT# pin and supports

the PMBus Alert Response Protocol and ARA if base

address ≥40h. With multiple slaves responding dur-

ing arbitration, the device does not release the SDA

signal if a lower address slave responds.

3

Read only

0

Numeric Format

0

1

Numeric data is in LINEAR11, ULINEAR16,

SLINEAR16 or DIRECT format

Numeric data is in IEEE Half precision Floating Point

Format

2

Read only

0

AVS Bus

Support

0

1

AVS Bus not supported

AVS Bus supported

Reserved

1:0

00

Reserved

SMBALERT_MASK (1Bh)

the mask byte 01000000b, then an Over temperature

Warning condition would be blocked from asserting

SMBALERT#.

The SMBALERT_MASK command may be used to

prevent a warning or fault condition from asserting the

SMBALERT# signal. The command format used to block a

status bit or bits from causing the SMBALERT# signal to be

asserted. The bits in the mask byte align with the bits in the

corresponding status register. For example if the

STATUS_TEMPERATURE command code were sent with

VOUT_MODE (20h)

Supports Linear Mode only: ULINEAR16 Format. The

ULINEAR16 format is given below

Mode

Bit[7] Bit[6:5]

00b

Bit[4:0] (Parameter)

ULINEAR16

X

Five bit two’s compliment exponent for the mantissa delivered as the

data bytes for an output voltage related command

VOUT_MODE

VOUT_COMMAND,

VOUT_MARGIN_HIGH,

command

is

used

VOUT_MAX,

VOUT_MARGIN_LOW,

for

VOUT_UV_WARN_LIMIT,

commands.

and

READ_VOUT

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25

FAN251030

VOUT_MODE, Data Byte for

Linear Mode

7

6

5

4

3

2

1

0

Mode= 00b

Exponent N

VOUT COMMAND, VOUT_MAX Data Bytes

For Linear Mode

Data Byte High

Data Byte Low

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Mantissa V

VOUT_MAX (24h)

The Mode bits are set to 000b. The Voltage, in Volts is

calculated from the equation: Voltage = V X 2

N

Sets the maximum allowed VOUT target regardless of

any other commands or combinations. The VOUT_MAX

follows the ULINEAR16 format. If mantissa is not within

the range 256 to 2817(d), it flags an invalid data fault. The

contents of this register can be stored to nonvolatile memory

using the STORE_USER_ALL command.

Where, Voltage is the parameter of interest in Volts; V is

a 16 bit unsigned binary integer, and N is a 5 bit two’s

compliment binary integer. The exponent N is fixed −9,

VOUT step size = 1.953 mV with 10 bit DAC. Attempt to

write to VOUT_MODE command will cause an invalid data

fault. VOUT_MODE Read back is 17(hex).

Range

Resolution

Default

VOUT_COMMAND (21h)

Sets the value of VOUT when the OPERATION

command is configured for PMBUS nominal operation. The

VOUT_COMMAND follows the ULINEAR16 format. The

contents of this register can be stored to nonvolatile memory

using the STORE_USER_ALL command.

0.5−5.5 V

1.953 mV

5.5 V

VOUT_MARGIN_HIGH (25h)

Sets the value of VOUT when the OPERATION

command is configured for margin high. The

VOUT_MARGIN_HIGH follows the ULINEAR16 format.

If the data is lower or equal to VOUT_MARGIN_LOW

setting, it flags an invalid data fault. Also if mantissa is not

within the range 256 to 2816, it flags an invalid data fault.

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command.

Range

Resolution

Default

0.5−5.5 V

1.953 mV

− V

RECOMMENDED VOUT_SCALE_LOOP SETTING

VOUT Range

0.5−1.99 V

1.992−3.99 V

4.0−5.5 V

VOUT_SCALE_LOOP

Range

Resolution

Default

F004

F002

F001

0.5−5.5 V

1.953 mV

3.4 V

VOUT_MARGIN_LOW (26h)

Sets the value of VOUT when the OPERATION

command is configured for margin low. The

VOUT_MARGIN_LOW follows the ULINEAR16 format.

If the data is higher or equal to VOUT_MARGIN_HIGH

setting, it flags an invalid data fault. Also if mantissa is not

within the range 256 to 2816, it flags an invalid data fault.

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command.

Exponent is FIXED −9 and Mantissa Range is 256 to

2816. Any data outside this range flags is an invalid data

fault. If MFR_MODE(C7hex) Bit#0 is set low the VSET pin

sets the default value of this register. Some Examples for

setting the VOUT are given below.

VOUT Voltage

0.8 V

PMBUS DATA

019A(hex)

0200(hex)

0300(hex)

0400(hex)

069A(hex)

0A00(hex)

0B00(hex)

Range

Resolution

Default

1.0 V

0.5−5.5 V

1.953 mV

3.2 V

1.5 V

2.0 V

3.3 V

5.0 V

5.5 V

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26

FAN251030

VOUT_TRANSITION_RATE (27h)

When

a

PMBUS device receives either

a

The contents of this register can be stored to nonvolatile

VOUT_COMMAND or OPERATION (Margin High,

Margin Low, Margin Off) that causes the output voltage to

change, this command sets the rate in mV/ms at which the

output should change voltage. This commanded rate of

change does not apply when the unit is commanded to turn

on or to turn off.

memory using the STORE_USER_ALL command. The

VOUT_TRANSITION_RATE command has two data

bytes encoded in LINEAR11 format as shown below (5bits

signed exponent and 11 bits mantissa)

LINEAR11 Format

Data Byte High

Data Byte Low

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

N

Y

The relation between Y, N and the real world value is

N

X = Y ꢀ 2

PMBUS Data(hex)

Gain

0.25

0.5

1

Where X is the real world value; Y is the 11 bit, two’s

compliment integer, and N is a 5 bit, two’s compliment

integer Exponent N is Fixed −6 ⇒11010(b) (Equivalent

LSB = 15.625 mV/ms)

Mantissa Y: Only 4 options allowed 00D, 07D, 0BB,

258(hex).

All the options allowed are given below. The default is

0.203 mV/ms. Attempting to write a value other than the

values listed in the below table will cause an invalid data

fault.

F001

F002

F004

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

VOUT_SCALE_LOOP command has two data bytes

encoded in LINEAR11 format:

• Exponent N is Fixed 11110(b) (Equivalent LSB = 0.25)

• Mantissa Y: Only 3 options allowed 01, 02, 04(hex)

Transition Rate in mV/ms

PMBUS Data(hex)

D00D

FREQUENCY_SWITCH (33h)

0.203

1.953

2.9218

9.375

The FREQUENCY_SWITCH command sets the

switching frequency in kHz. This command has two data

bytes encoded in LINEAR11 format. Exponent N is Fixed

00001(b) (Equivalent LSB = 2 kHz)

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command.

D07D

D0BB

D258

VOUT_SCALE_LOOP (29h)

The VOUT_SCALE_LOOP sets the output sense scaling

ratio for the main control loop. FAN2510xx supports only 3

options/ratios: 1, 0.5, 0.25. Attempting to write a value other

than the values listed in the below table will cause an invalid

data fault.

Range

Resolution

Default

200−1800 kHz

2 kHz

600 kHz

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27

FAN251030

All the options supported are given in the Table below.

Any data other than the data given in the table below will flag

an invalid data fault.

Frequency (kHz)

200

PMBUS Data (hex)

0864

250

087D

0896

300

350

08AF

08C8

08E1

400

450

500

08FA

550

0913

600

092C

0945

650

700

095E

750

0977

800

0990

850

09A9

900

09C2

09DB

09F4

950

1000

1050

1100

1150

1200

1300

1400

1500

1600

1700

1800

0A0D

0A26

0A3F

0A58

0A8A

0ABC

0AEE

0B20

0B52

0B84

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28

FAN251030

VIN_ON (35h)

The VIN_ON command sets the value of V in Volts at

which the chip should start the power conversion. The two

data bytes are encoded in LINEAR11 format as shown

below. Exponent is in 2’s compliment format and mantissa

is unsigned binary. The contents of this register can be stored

to nonvolatile memory using the STORE_USER_ALL

command. The format, supported range and resolution are

given in the below table.

IN

Data Byte High

5 Bit Exponent

Data Byte Low

11 Bit Unsigned Mantissa

4

3

2

1

0

10

R

9

8

7

6

5

4

3

2

1

0

R

R/W

Default Exponent

Default Mantissa

1

0

1

0

Default VIN UVLO Rising Threshold: 6 V

compliment format and mantissa is unsigned binary. The

contents of this register can be stored to nonvolatile memory

using the STORE_USER_ALL command. The format is

same as VIN_ON command. The range and resolution are

given in the below table.

VIN UVLO Rising Threshold Range: 3.0 V to 10.5 V

VIN_IN Exponent: Fixed −1 (Equivalent LSB = 0.5 V)

All the options supported are given in the Table below.

Any data other than the data given in the table below will flag

an invalid data fault. If V “on” data is lower or equal to V

IN

“off”; the invalid data flag is set. If the input voltage does not

reach the rising VIN UVLO Threshold after the VCC Enable

Threshold is crossed, a VIN UVLO Fault will trigger.

Range

Resolution

Default

2.5−10.0 V

0.5 V

6 V(F80C (hex))

All the options supported are given in the Table below.

Any data other than the data given in the table below will flag

an invalid data fault. If Vin_off data is higher than Vin_on

the invalid data flag is set.

PMBUS data

F806

VIN ON Threshold (V)

3

3.5

4

F807

F808

PMBUS data

F805

VIN OFF Threshold (V)

F809

4.5

5

2.5

3

F80A

F80B

F80C

F80D

F80E

F80F

F810

F806

5.5

6

F807

3.5

4

F808

6.5

7

F809

4.5

5

F80A

F80B

F80C

F80D

F80E

F80F

F810

7.5

8

5.5

6

F811

8.5

9

6.5

7

F812

F813

9.5

10

10.5

7.5

8

F814

F815

F811

8.5

9

VIN_OFF (36h)

F812

The VIN_OFF command sets the value of the input

voltage in volts at which the unit once operation has started

should stop power conversion. The two data bytes are

encoded in LINEAR11 format. Exponent is in 2’s

F813

9.5

10

F814

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29

FAN251030

INTERLEAVE (37h)

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

default is set to standalone.

The INTERLEAVE command is used to arrange multiple

units to facilitate paralleling of multiple units. The

Interleave is a 16− bit command with 3 components (plus 4

unused bits in front):

• Group ID (4 bits)

PMBUS Data

Mode

Standalone

• Number of units in the group (4 bits)

16’b0000_0000_0000_0000

16’b0000_0001_0000_0000

16’b0000_0001_0010_0000

16’b0000_0001_0010_0001

• Interleave order of the unit in the group (4 bits)

Master Sync

The following options are supported by FAN251030:

Sync Slave − In Phase

Sync Slave − Out of Phase

Standalone:

Group ID = 0, Number of units = 0, Interleave order = 0

[0000 0000 0000 0000] ⇒ unit is neither master nor slave,

does not drive the SYNC pin and ignores any clock on

SYNC pin.

VOUT_OV_FAULT_RESPONSE (41h)

VOUT_OV_FAULT_RESPONSE command Instructs

the device on what action to take in response to an output

over voltage fault set based on the manufacture specific

command PCT_VOUT_LIMIT(C6h), Bits<11:9>.

For synchronization

Master:

Group ID = 1, Number of units = 0, Interleave order = 0

[0000 0001 0000 0000] ⇒ unit is master, and sends its

internal clock out on the SYNC pin.

The device also sets

• Sets the VOUT_OV bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the VOUT OV Fault bit in the STATUS_VOUT

• Notifies the host by asserting the ALERTB

Slave:

• Group ID = 1, Number of units = 2, Interleave order =

0 [0000 0001 0010 0000] ⇒ the unit operates in−phase

to the clock applied on its SYNC (or operates on its

own internal clock if no clock on SYNC)

• Group ID = 1, Number of units = 2, Interleave order =

1 [0000 0001 0010 0001] ⇒ the unit operates

out−of−phase to the clock applied on its SYNC (or

operates on its own internal clock if no clock on

SYNC).

The fault bit once set is cleared only in accordance with

Clear Faults section and not when the fault condition is

removed. The contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

The default of this register is set to 40(hex) ⇒ latch off

behavior The data byte is encoded in the format shown

below

Bits

Description

Value

00

Meaning

7:6

Chip continues operation without interruption

01

Chip continues operation for the delay time specified by bits[2:0].

If the fault condition is still present at the end of the delay time,

the chip responds as programmed in the Retry setting (bits[5:3])

10

11

Not Supported – The chip shuts down (disables the output) and responds according

to the retry setting bits[5:3]

Not Supported – The chip’s output is disabled while the fault is present. Operation

resumes and the output is enabled when the fault condition no longer exists

5:3

2:0

000

A zero value for the retry setting means that the chip does not attempt to restart.

The output remains disabled until the faulty is cleared

Retry Setting

(Latchoff or

Hiccup)

001−110

Not Supported

111

The chip attempts to restart continuously without limitation, until it is commanded

OFF (by the ENABLE pin or OPERATION command or both), VIN/VCC is removed

or another fault condition causes the unit to shut−down. Hiccup time is 1 s

Delay Time

XXX

X00− 6.25 ms

X01 – 7.5 ms

X10 – 8.75 ms

X11 − 10 ms

For 0 V warning the FETs are turned off immediately. An

option is provided to turn off the high side FET and turn on

the low side FET. MFR_MODE _SETTINGS(C8) Bit<2>

is used for this purpose. An attempt to write “Not supported”

data given in the table above will flag an invalid data fault.

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30

FAN251030

VOUT_UV_WARN_LIMIT (43h)

under voltage fault set based on the manufacture specific

command PCT_VOUT_LIMIT(C6h) Bits<5:3>.

The device also

• Sets the VOUT bit in the STATUS_WORD

• Sets the VOUT UV Fault bit in the STATUS_VOUT

• Notifies the host by asserting the ALERTB

The VOUT_UV_WARN_LIMIT command specifies the

VOUT UV warn limit threshold. The command follows the

ULINEAR16 format. The contents of this register can be

stored

to

nonvolatile

memory

using

the

STORE_USER_ALL command. The range, resolution and

default value is given in the table below.

The fault bit once set is cleared only in accordance with

Clear Faults section and not when the fault condition is

removed. The contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

The default of this register is set to 40(hex) ⇒ latch off

behavior The data byte is encoded in the format shown

below

Range

Resolution

Default

0.5−5.5 V

1.9535 mV

0.2 V (0067 (hex))

When VOUT crosses the VOUT UV threshold the

STATUS _VOUT(7A) Bit#6 is flagged.

VOUT_UV_FAULT_RESPONSE (45h)

VOUT_UV_FAULT_RESPONSE command Instructs

the device on what action to take in response to an output

Bits

Description

Value

00

Meaning

7:6

Chip continues operation without interruption

01

Chip continues operation for the delay time specified by bits[2:0]. If the fault condi-

tion is still present at the end of the delay time, the chip responds as programmed in

the Retry setting (bits[5:3])

10

11

Not Supported – The chip shuts down (disables the output) and responds according

to the retry setting bits[5:3]

Not Supported – The chip’s output is disabled while the fault is present. Operation

resumes and the output is enabled when the fault condition no longer exists.

5:3

2:0

000

A zero value for the retry setting means that the chip does not attempt to restart.

The output remains disabled until the faulty is cleared

Retry Setting

(Latchoff or

Hiccup)

001−110

Not Supported

111

The chip attempts to restart continuously without limitation, until it is commanded

OFF (by the ENABLE pin or OPERATION command or both), VIN/VCC is removed

or another fault condition causes the unit to shutdown. Hiccup time is 1 s

Delay Time

XXX

X00 – 6.25 ms

X01 – 7.5 ms

X10 – 8.75 ms

X11 – 10 ms

An attempt to write “Not supported” data given in the

table above will flag an invalid data fault.

(5 bits un−signed exponent and 11 bits mantissa). The range,

resolution and default are shown in the below table.

IOUT_OC_FAULT_LIMIT (46h)

Range

Resolution

Default

This command sets the value of the peak output current in

amperes for the high side FET and causes an over current

peak detection fault. The IOUT_OC_FAULT_LIMIT

command has two data bytes encoded in LINEAR11 format

2−62A

2

54 A (081B(hex))

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31

FAN251030

The contents of this register can be stored to nonvolatile

supported are given in the Table below. Any data other than

the data given in the table below will flag an invalid data

fault.

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than 1 is

written, an invalid data fault is flagged. All the options

PMBUS Data(hex)

0801

OC Peak Fault Limit(A)

2

0802

4

0803

6

0804

8

0805

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

0806

0807

0808

0809

080A

080B

080C

080D

080E

080F

0810

0811

0812

0813

0814

0815

0816

0817

0818

0819

081A

081B

081C

081D

081E

081F

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32

FAN251030

IOUT_OC_FAULT_RESPONSE (47h)

The fault bit once set is cleared only in accordance with

“Clear Faults” section and not when the fault condition is

removed. The contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

The default of this register is set to 80(hex) ⇒ latch off

behavior.

The data byte is encoded in the format shown below.

This command instructs the device on what action to take

in response to an output over current peak fault The device

also

• Sets the IOUT bit in the STATUS_WORD

• Sets the IOUT bit in the STATUS_BYTE

• Sets the OCP Peak Fault Bit #7 in the STATUS_IOUT

• Notifies the host by asserting the ALERTB

Bits

Description

Value

Meaning

7:6

00

Chip continues operation without interruption while maintaining the output current at

the values set by IOUT_OC_FAULT_LIMIT without regard to the output voltage

01

10

Chip continues operating indefinitely except if VOUT_UV is detected

The chip continues to operate, maintaining the output current at the value set by

IOUT_OC_FAULT_LIMIT without regard to the output voltage. For the delay time

set by bits[2:0]. If the chip is still operating in current limiting at the end of the delay

time , the chip responds as programmed by the Retry Setting in bits[5:3]

11

The chip shuts down and responds as programmed by the Retry setting in bits[5:3]

5:3

2:0

Retry Setting

(Latchoff or

Hiccup)

000

A zero value for the retry setting means that the chip does not attempt to restart.

The output remains disabled until the faulty is cleared

001−110

Not Supported

111

The chip attempts to restart continuously without limitation, until it is commanded

OFF (by the ENABLE pin or OPERATION command or both), VIN/VCC is removed

or another fault condition causes the unit to shutdown. Hiccup time is 1 s

Delay Time

XXX

000 – 160−320 ms

001 – 320−480 ms

010 – 640−800 ms

011 – 1.28−1.44 ms

100 – 2.56−2.72 ms

101 – 5.12−5.28 ms

110 – 9.6−9.76 ms

111 – 10.08−10.24 ms

NOTE: An attempt to write “Not supported” data given in the table above will flag an invalid data fault.

IOUT_OC_WARN_LIMIT (4Ah)

Few examples are given in the Table below. The exponent

is read only and if an exponent other than −4(11100b) is

written, an invalid data fault is flagged. There is no range

check on this command.

This command sets the value of the output current in

amperes that causes a over current detection warn flag.

The IOUT_OC_WARN_LIMIT command has two data

bytes encoded in LINEAR11 format (5 bits signed exponent

and 11 bits mantissa). The range, resolution and default are

shown in the below table.

Examples

IOUT OC WARN Limit

PMBUS Data

E0A0(hex)

E0F0(hex)

E140(hex)

E190(hex)

E1E0(hex)

E230(hex)

10 A

15 A

20 A

25 A

30 A

35 A

Range

Resolution

Default

1−64 A

62.5 mA

32 A (E200(hex))

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command.

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33

FAN251030

IOUT_UC_FAULT_LIMIT (4Bh)

The fault bit once set is cleared only in accordance with

Clear Faults section and not when the fault condition is

removed.

This command sets the value of the output negative

current limit in amperes that causes a under current detection

fault flag. The IOUT_UC_FAULT_LIMIT command has

two data bytes encoded in LINEAR11 format (5 bits

un−signed exponent and 11 bits mantissa). The range,

resolution and default are shown in the below table.

OT_FAULT_LIMIT (4Fh)

This command sets the temperature in degrees Celsius at

which chip should indicate an over temperature fault. The

OT_FAULT_LIMIT command has two data bytes encoded

in LINEAR11 format (5 bits unsigned exponent and 11 bits

mantissa). The range, resolution and default are shown in the

below table.

Range

Resolution

Default

10−24 A

2 A

14A(000Ehex)

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than

0(00000b) is written, an invalid data fault is flagged. All the

options supported are given in the Table below. Any data

other than the data given in the table below will flag an

invalid data fault.

Range

Resolution

Default

80−160°C

1°C

140°C

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than

0(00000b) is written, an invalid data fault is flagged. The

mantissa range is 80°C to 160°C. Any mantissa outside this

range will assert invalid data fault. Also if the OT fault limit

is set lower or equal to OT warn limit then an invalid data

fault is flagged. Few examples are given in the Table below.

IOUT UC FAULT Limit

PMBUS Data

000A(hex)

10 A

12 A

14 A

000C(hex)

000E(hex)

0010(hex)

0012(hex)

0014(hex)

0016(hex)

0018(hex)

OT Fault Limit

80°C

PMBUS Data

0050(hex)

005A(hex)

0064(hex)

0069(hex)

0078(hex)

00A0(hex)

16 A

18 A

20 A

22 A

24 A

90°C

100°C

105°C

120°C

160°C

When this fault happens the device sets

• Sets the None of the above bit in the STATUS_BYTE

• Sets the IOUT bit in the STATUS_WORD

• Sets the IOUT UC Fault bit in the STATUS_IOUT

• Notifies the host by asserting the ALERTB

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34

FAN251030

OT_FAULT_RESPONSE (50h)

The fault bit once set is cleared only in accordance with

Clear Faults section and not when the fault condition is

removed. The contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

OT_FAULT_RESPONSE command Instructs the device

on what action to take in response to an over temperature

fault set by OT_FAULT_LIMIT command. The device also:

• Sets the Temp bit in the STATUS_BYTE

• Sets the Over Temp Fault bit in the STATUS_TEMP

• Notifies the host by asserting the ALERTB

The default of this register is set to C0(hex) ⇒ recovery

The data byte is encoded in the format shown below

Bits

Description

Value

00

Meaning

7:6

Ignore/latchoff

or recovery

Chip continues operation without interruption

01

Not Supported − Chip continues operation for the delay time specified by bits[2:0].

If the fault condition is still present at the end of the delay time, the chip responds

as programmed in the Retry setting (bits[5:3])

10

11

The chip shuts down (disables the output) and responds according to the retry

setting bits[5:3]

The chip’s output is disabled while the fault is present. Operation resumes and the

output is enabled when the fault condition no longer exists

5:3

2:0

Retry Setting

(Latchoff )

000

A zero value for the retry setting means that the chip does not attempt to restart.

The output remains disabled until the faulty is cleared

001−110

Not Supported

111

Not Supported The chip attempts to restart continuously without limitation, until it is

commanded OFF (by the ENABLE pin or OPERATION command or both), VIN/

VCC is removed or another fault condition causes the unit to shut−down. Hiccup

time is 1 s

Delay Time

XXX

Not Supported

An attempt to write “Not supported” data given in the

table above will flag an invalid data fault.

is set higher or equal to OT fault limit then an invalid data

fault is flagged. Few examples are given in the Table below.

OT_WARN_LIMIT (51h)

OT Warn Limit

80°C

PMBUS Data

0050(hex)

005A(hex)

0064(hex)

0069(hex)

0078(hex)

00A0(hex)

This command sets the temperature in degrees Celsius at

which chip should indicate an over temperature warn flag.

The OT_WARN_LIMIT command has two data bytes

encoded in LINEAR11 format (5 bits unsigned exponent

and 11 bits mantissa). The range, resolution and default are

shown in the below table.

90°C

100°C

105°C

120°C

Range

Resolution

Default

160VC

70−150°C

1°C

115°C

When over temperature warn flag is asserted, the device:

• Sets the Temp bit in the STATUS_BYTE

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than

0(00000b) is written, an invalid data fault is flagged. The

mantissa range is 70°C to 150°C. Any mantissa outside this

range will assert invalid data fault. Also if the OT warn limit

• Sets the Over Temp Warn bit in the STATUS_TEMP

The warn bit once set is cleared only in accordance with

Clear Faults section and not when the warn condition is

removed.

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35

FAN251030

VIN_OV_FAULT_LIMIT (55h)

VIN_OV_FAULT_RESPONSE (56h)

This command sets the value of the input voltage V in

volts that causes an input over voltage fault.

VOUT_OV_FAULT_RESPONSE command Instructs

the device on what action to take in response to an input over

IN

The VIN_OV_FAULT_LIMIT command has two data

bytes encoded in LINEAR11 format (5 bits unsigned

exponent and 11 bits mantissa). The range, resolution and

default are shown in the below table.

voltage

fault

set

based

on

the

VIN_OV_FAULT_LIMIT(55h) . The device also sets

• Sets the None of the above bit in the STATUS_BYTE

• Sets the VIN OVP bit in the STATUS_WORD

• Sets the VIN OV Fault bit in the STATUS_INPUT

• Notifies the host by asserting the ALERTB

Range

Resolution

Default

18−24 V

2 V

20 V

The fault bit once set is cleared only in accordance with

Clear Faults section and not when the fault condition is

removed. The contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

The default of this register is set to C0(hex) ⇒ Recovery

behavior The data byte is encoded in the format shown

below.

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than

1(00001b) is written, an invalid data fault is flagged. All the

options supported are given in the Table below. Any data

other than the data given in the table below will flag an

invalid data fault.

V

IN

Fault Limit

18 V

PMBUS Data

0809(hex)

080A(hex)

080B(hex)

080C(hex)

20 V

22 V

24 V

Bits

Description

Value

Meaning

7:6

00

01

Chip continues operation without interruption

Chip continues operation for the delay time specified by bits[2:0].

If the fault condition is still present at the end of the delay time, the chip responds

as programmed in the Retry setting (bits[5:3])

10

11

Not Supported – The chip shuts down (disables the output) and responds according

to the retry setting bits[5:3]

The chip’s output is disabled while the fault is present. Operation resumes and the

output is enabled when the fault condition no longer exists.

5:3

2:0

Retry Setting

(Latchoff or

Hiccup)

000

A zero value for the retry setting means that the chip does not attempt to restart.

The output remains disabled until the faulty is cleared

001−110

111

Not Supported

Delay Time

XXX

X00 – 6.25 ms

X01 – 7.5 ms

X10 – 8.75 ms

X11 – 10 ms

For 0 V warning the FETs are turned off immediately. An

option is provided to turn off the high side FET and turn on

the low side FET. MFR_MODE _SETTINGS(C8) Bit<2>

is used for this purpose. An attempt to write “Not supported”

data given in the table will flag an invalid data fault.

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36

FAN251030

TON_DELAY (60h)

This command sets the time, in milliseconds, from when

a start condition is received (as programmed by the

ON_OFF_CONFIG command) until the output voltage

starts to rise. The TON_DELAY command has two data

bytes encoded in LINEAR11 format (5 bits unsigned

exponent and 11 bits mantissa). The range, resolution and

default are shown in the below table.

TON Rise

1 ms

PMBUS Data

0001(hex)

0002(hex)

0003(hex)

0005(hex)

0009(hex)

000A(hex)

2 ms

3 ms

5 ms

9 ms

10 ms

Range

Resolution

Default

1−10 ms

1 ms

TON_MAX_FAULT_LIMIT (62h)

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than

0(00000b) is written, an invalid data fault is flagged. Any

mantissa Bit<10:4> if not 00(hex) will assert invalid data

fault. Few examples are given in the Table below.

This command sets an upper limit, in milliseconds, on

how long the unit can attempt to power up the output without

reaching the output under voltage fault limit. The

TON_MAX_FAULT_LIMIT command has two data bytes

encoded in LINEAR11 format (5 bits unsigned exponent

and 11 bits mantissa). The range, resolution and default are

shown in the below table.

TON Delay

1 ms

PMBUS Data

0001(hex)

0002(hex)

0003(hex)

0005(hex)

0009(hex)

000A(hex)

Range

Resolution

Default

0−50 ms

2 ms

12 ms

2 ms

3 ms

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than

1(00001b) is written, an invalid data fault is flagged. Any

mantissa Bit<10:5> if not 00(hex) will assert invalid data

fault. 0ms setting will also set an invalid data fault. Few

examples are given in the Table below.

5 ms

9 ms

10 ms

TON_RISE (61h)

This command sets the time, in milliseconds, from when

the output starts to rise until the voltage has entered the

regulation band. The TON_RISE command has two data

bytes encoded in LINEAR11 format (5 bits unsigned

exponent and 11 bits mantissa). The range, resolution and

default are shown in the below table.

TON Max Fault Limit

PMBUS Data

0801(hex)

0802(hex)

0805(hex)

080A(hex)

080F(hex)

0814(hex)

2 ms

4 ms

10 ms

20 ms

30 ms

40 ms

Range

Resolution

Default

1−20 ms

1 ms

5 ms

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than

0(00000b) is written, an invalid data fault is flagged. Any

mantissa Bit<10:5> if not 00(hex) will assert invalid data

fault. 0ms setting will also set an invalid data fault. Few

examples are given in the Table below.

TON_MAX_FAULT_RESPONSE (63h)

TON_MAX_FAULT_RESPONSE command Instructs

the device on what action to take in response to an Ton−max

fault set by TON_MAX_FAULT_LIMIT command; The

device also:

• Sets the VOUT bit in the STATUS_BYTE

• Sets the TON MAX fault bit in the STATUS_VOUT

• Notifies the host by asserting the ALERTB

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37

FAN251030

The fault bit once set is cleared only in accordance with

The default of this register is set to 80(hex) ⇒ Latchoff

The data byte is encoded in the format shown below

Clear Faults section and not when the fault condition is

removed. The contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

Bits

Description

Value

00

Meaning

7:6

Chip continues operation without interruption

Ignore/latchoff or

recovery

01

Not Supported − Chip continues operation for the delay time specified by bits[2:0]. If

the fault condition is still present at the end of the delay time, the chip responds as

programmed

in the Retry setting (bits[5:3])

10

11

The chip shuts down (disables the output) and responds according to the retry

setting bits[5:3]

Not Supported −The chip’s output is disabled while the fault is present. Operation

resumes and the output is enabled when the fault condition no longer exists.

5:3

2:0

000

A zero value for the retry setting means that the chip does not attempt to restart.

The output remains disabled until the faulty is cleared

Retry Setting

(Latchoff )

001−110

Not Supported

111

The chip attempts to restart continuously without limitation, until it is commanded

OFF (by the ENABLE pin or OPERATION command or both), VIN/VCC is removed

or another fault condition causes the unit to shutdown. Hiccup time is 1 s

Delay Time

XXX

Not Supported

NOTE: An attempt to write “Not supported” data given in the table above will flag an invalid data fault.

TOFF_DELAY (64h)

TOFF_FALL (65h)

This command sets the time, in milliseconds, from when

a stop condition is received (as programmed by the

ON_OFF_CONFIG command) until the unit stops

transferring energy to the output. The TOFF_DELAY

command has two data bytes encoded in LINEAR11 format

(5bits unsigned exponent and 11 bits mantissa). The range,

resolution and default are shown in the below table.

This command sets the time, in milliseconds, from the end

of the turn−off delay time until the voltage is commanded to

zero. The TOFF_FALL command has two data bytes

encoded in LINEAR11 format (5 bits unsigned exponent

and 11 bits mantissa). The range, resolution and default are

shown in the below table.

Range

Resolution

Default

Range

Resolution

Default

1−20 ms

1 ms

5 ms

0−10 ms

1 ms

0 ms

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than

0(00000b) is written, an invalid data fault is flagged. Any

mantissa Bit<10:5> if not 00(hex) will assert invalid data

fault. 0ms setting will also set an invalid data fault. Few

examples are given in the Table below.

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. The

exponent is read only and if an exponent other than

0(00000b) is written, an invalid data fault is flagged. Any

mantissa Bit<10:4> if not 00(hex) will assert invalid data

fault. Few examples are given in the Table below.

TOFF Delay

1 ms

PMBUS Data

0001(hex)

0002(hex)

0003(hex)

0005(hex)

0009(hex)

000A(hex)

TOFF Fall

1 ms

PMBUS Data

0001(hex)

0002(hex)

0003(hex)

0005(hex)

0009(hex)

000A(hex)

2 ms

3 ms

5 ms

9 ms

10 ms

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38

FAN251030

STATUS_BYTE (78h)

This command returns one byte of information with the

summary of the critical faults. The below table shows all the

bits.

Bit

7

Function

Support

Yes

Busy – nonvolatile memory is being accessed either for read or write operation

6

OFF

Yes

5

VOUT_OVP Fault

Yes

4

IOUT_OC(Peak Fault)

Yes

3

VIN_UV

No

2

Temperature Fault or Warn

CML(PEC Failed, Invalid data or Invalid command)

Yes

1

Yes

0

None of the above (vin_ovp, vin_off, ocp average fault, hsd_ilim2, lsd_ilim,

pgood_fault, vout_uvlo_fault, vout_ uvwarn, ocp_warn, ocp_peak & uvlo fault,

over temp umbrella, sw_fault, boot_uvlo, all STATUS_MFR faults

Yes

STATUS_WORD (79h)

This command returns two bytes of information with the

summary of the critical faults. The lower byte of

STATUS_WORD is the same register as STATUS_BYTE

command. The below table shows all the bits in the upper

byte.

Upper Byte Bit #

Function

Supporting

7

6

VOUT(all STATUS_VOUT)

Yes

IOUT/POUT(Peak OCP Fault or Average OCP Fault or Warn or Neg ILIM Fault)

5

4

3

2

1

0

INPUT(VIN OVP Fault & VIN_OFF Fault)

Yes

No

MFR(all STATUS_MFR)

POWERGOOD#

FANS

Other

No

Unknown

No

If output voltage is valid then POWERGOOD# bit is

cleared. If output voltage is not present POWERGOOD# is

set.

bits. The table also shows SMBALERT_MASK command

support.

STATUS_VOUT (7Ah)

This command returns one byte of information with the

summary of the V

faults. The below table shows all the

OUT

Status VOUT Reporting

Support

Yes

No

Support Alert Mask

Bit<7> output over voltage fault

Bit<6> output over voltage warning

Bit<5> output under voltage warning

Bit<4> output under voltage fault

Bit<3>output max or min warning

Bit<2> ton max fault

Yes

No

Yes

No

Yes

No

Yes

No

Bit<1> ton max warning

Bit<0> output voltage tracking error

No

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39

FAN251030

STATUS_IOUT (7Bh)

This command returns one byte of information with the

bits. The table also shows SMBALERT_MASK command

support.

summary of the I

faults. The below table shows all the

OUT

Status IOUT Reporting

Support

Yes

No

Support Alert Mask

Bit<7> output over current peak fault

Bit<6> output over current and low voltage fault

Bit<5> output over current average warning

Bit<4> output under current fault

Bit<3> current share fault

Yes

No

Yes

No

Bit<2> in power limiting mode

No

Bit<1> output overpower fault

No

Bit<0> output overpower warning

No

STATUS_INPUT (7Ch)

This command returns one byte of information with the

summary of the VIN faults. The below table shows all the

bits. The table also shows SMBALERT_MASK command

support.

Status INPUT Reporting

Support

Yes

No

Support Alert Mask

Bit<7> input over voltage fault

Yes

Bit<6> input over voltage warning

Bit<5> input under voltage warning

Bit<4> input under voltage fault

Bit<3> unit off for insufficient input voltage

Bit<2> input over current fault

No

Yes

No

Yes

No

Bit<1> input over current warning

Bit<0> input overpower warning

No

STATUS_TEMPERATURE (7Dh)

This command returns one byte of information with the

summary of the temperature faults. The below table shows

all the bits. The table also shows SMBALERT_MASK

command support.

Status Temperature Reporting

Bit<7> over temperature fault

Support

Yes

No

Support Alert Mask

Yes

No

Bit<6> over temperature warning

Bit<5> under temperature warning, reports 0

Bit<4> under temperature fault

Bit<3> Reserved, reports 0

No

Bit<2> Reserved, reports 0

No

Bit<1> Reserved, reports 0

No

Bit<0> Reserved, reports 0

No

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40

FAN251030

STATUS_CML(7Eh)

This command returns one byte of information with the

summary of the below faults. The table also shows

SMBALERT_MASK command support.

Status CML Reporting

Bit<7> command not supported

Support

Yes

No

Support Alert Mask

Yes

No

Bit<6> invalid data

Bit<5> PEC fault

Bit<4> OTP fault − Not supported, reports 0

Bit<3:2> Reserved, reports 0

No

Bit<1> other communication fault, reports 0

Bit<0>other memory or logic fault, reports 0

No

STATUS_MFR_SPECIFIC (80h)

This command returns one byte of information with the

summary of the below faults. The table also shows

SMBALERT_MASK command support.

Status MFR Reporting

Bit<7> ocp average fault flag

Bit<6> hsd_ilim2

Support

Support Alert Mask

Yes

No

Yes

No

Bit<5>sw_fault

Bit<4>boot_uvlo

Bit<3> over temp analog

Bit<2> Lg Pin Fault

Bit<1>

MTP

Programming Fault

Bit<0> Not used, reports 0

READ_VIN (88h)

READ_IIN (89h)

The READ_VIN command returns the input voltage in

Volts. The two data bytes are encoded in LINEAR11 format

(5 bits signed exponent and 11 bits mantissa). Exponent is

FIXED −5 (11011b) indicating a LSB of 31.25 mV.

The range and resolution are shown in the below table.

The READ_IIN command returns the input current in

Amps. The two data bytes are encoded in LINEAR11 format

(5 bits signed exponent and 11 bits mantissa). Exponent is

FIXED −4 (11100b) indicating a LSB of 62.5 mA. The range

and resolution are shown in the below table. READ_IIN

acknowledges only if the device is regulating.

Range

Resolution

Range

Resolution

0−25 V

31.25 mV

0−64 A

62.5 mA

Few examples are given in the Table below.

Read VIN

6 V

PMBUS Data

Read IIN(Amps)

PMBUS Data

D8C0(hex)

D940(hex)

D980(hex)

DA40(hex)

6

E060(hex)

E0A0(hex)

E0C0(hex)

E120(hex)

10 V

10

12

18

12 V

18 V

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41

FAN251030

READ_VOUT(8Bh)

The READ_VOUT command returns the actual,

measured (not commanded) output voltage in the same

format as set by the VOUT_MODE command. The two data

bytes are encoded in LINEAR16 format as shown in below.

READ_VOUT ULINEAR16 Format

Data Byte High

Data Byte Low

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Mantissa V

READ_TEMPERATURE(8Dh)

The exponent is defined by VOUT_MODE command.

Exponent is FIXED −9 (10111b) indicating a LSB of

1.953 mV.

The range and resolution are shown in the below table.

READ_VOUT will only acknowledge if the device is

regulating.

The READ_TEMPERATURE command returns the

measured temperature in degree Celsius. The two data bytes

are encoded in LINEAR11 format (5 bits unsigned exponent

and 11 bits signed mantissa). Exponent is FIXED 0 (00000b)

indicating a LSB of 1°C.The range and resolution are shown

in the below table.

Range

Resolution

Range

Resolution

0.5 V−5.5 V

1.953 mV (set by VOUT_MODE command)

−40 to 175°C

1°C

Few examples are given in the Table below.

Read VOUT(V)

0.8 V

PMBUS Data

019A(hex)

0200(hex)

0300(hex)

0400(hex)

069A(hex)

0A00(hex)

0B00(hex)

PMBUS Data

Read Temp (°C)

1.0 V

25

50

0019(hex)

0032(hex)

0064(hex)

07EC(hex)

1.5 V

2.0 V

100

−20

3.3 V

5.0 V

READ_FREQ(95h)

5.5 V

The READ_ FREQ command returns the switching

frequency in KHz. The two data bytes are encoded in

LINEAR11 format (5bits unsigned exponent and 11 bits

unsigned mantissa). Exponent is FIXED 0 (00000b)

indicating a LSB of 1KHz. The range and resolution are

shown in the below table. READ_FREQ will only

acknowledge if the device is regulating.

READ_IOUT(8Ch)

The READ_IOUT command returns the measured output

current in Amps. The two data bytes are encoded in

LINEAR11 format (5 bits signed exponent and 11 bits

mantissa). Exponent is FIXED −4 (11100b) indicating a

LSB of 62.5 mA. The range and resolution are shown in the

below table. “READ_IOUT” will not acknowledge if the

device is not regulating.

Range

Resolution

100 Khz – 2.5 MHz

1 KHz

Range

Resolution

Few examples are given in the Table below.

0−64 A

62.5 mA

Few examples are given in the Table below.

Read Freq (KHz)

PMBUS Data

200

400

600

800

00C8(hex)

0190(hex)

0258(hex)

0320(hex)

Read IOUT(Amps)

PMBUS Data

6

E060(hex)

E0A0(hex)

E0C0(hex)

E120(hex)

10

12

18

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42

FAN251030

PMBUS_REVISION(98h)

indicate the revision of PMBUS specification Part I to which

the device is compliant. Bits [3:0] indicate the revision of

PMBUS specification Part II to which the device is

compliant. The permissible values are shown below.

PMBUS_REVISION command stores or reads the

revision of the PMBUS to which the device is compliant.

This command is read only and has one data byte. Bits [7:4]

Part II

Revision

Bits [7:4]

0000b

Part I Revision

Bits[3:0]

0000b

0001b

0010b

0011b

1.0

1.1

1.2

1.3

1.0

0001b

1.1

0010b

1.2

0011b

1.3

FAN2510xx supports Revsion1.3 and therefore reads

back 33(hex) for PMBUS_REVISION command.

MFR_ID(99h)

MFR_ID command is used to either set or read the

manufacture’s ID (name, abbreviation or symbol that

identifies the unit’s manufacturer). This command is

read/write accessible and has two data bytes as shown

below.

MFR_ID Format

Dat a Byte High

Byte Count = 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Block R/W Format

MFR_REVISION (9Bh)

The Block R/W format needs to be used to access this

register for read and write operations. The lower byte

represents the number of bytes and this is fixed to

1(00000001b). The higher byte is used to represent the

MFR_ID.

The higher byte contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

MFR_REVISION command is used to either set or read

the manufacture’s revision number. This command is

read/write accessible and has two data bytes. The Block

R/W format needs to be used to access this register for read

and write operations. The lower byte represents the number

of bytes and this is fixed to 1(00000001b). The higher byte

is used to represent the MFR_REVISION.

The higher byte contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

MFR_MODEL (9Ah)

MFR_MODEL command is used to either set or read the

manufacture’s model number. This command is read/ write

accessible and has two data bytes. The Block R/W format

needs to be used to access this register for read and write

operations. The lower byte represents the number of bytes

and this is fixed to 1(00000001b). The higher byte is used to

represent the MFR_MODEL.

The higher byte contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

MFR_SERIAL (9Eh)

MFR_SERIAL command is used to either set or read the

manufacture’s serial number of the device. This command

is read/write accessible and has two data bytes. The Block

R/W format needs to be used to access this register for read

and write operations. The lower byte represents the number

of bytes and this is fixed to 1(00000001b). The higher byte

is used to represent the MFR_SERIAL. The higher byte

contents of this register can be stored to nonvolatile memory

using the STORE_USER_ALL command.

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43

FAN251030

MFR_VOUT_MIN (A4h)

IC_DEVICE_REV (AEh)

MFR_VOUT_MIN command is used to retrieve the

minimum rated value, in Volts, to which the output voltage

may be set for the device. This command is read accessible

and has two data bytes in UNLINEAR16 format. The

exponent is defined by VOUT_MODE command. Exponent

is FIXED −9 (10111b) indicating a LSB of 1.953 mV. The

read back of this register is set to 0100(hex) to represent

0.5 V.

IC_DEVICE_REV command is used to read the revision

of the IC whose type or part number is read with the

IC_DEVICE_ID command. This command is read

accessible and has two data bytes. The Block Read format

needs to be used to access this register for read operation.

The lower byte represents the number of bytes and this is

fixed to 1(00000001b). The higher byte is used to represent

the IC_DEVICE_REV.

MFR_VOUT_MAX (A5h)

IOUT_AVG_FAULT_RESPONSE (C4h)

MFR_VOUT_MIN command is used to retrieve the

maximum rated value, in Volts, to which the output voltage

may be set for the device. This command is read accessible

and has two data bytes in UNLINEAR16 format The

exponent is defined by VOUT_MODE command. Exponent

is FIXED −9 (10111b) indicating a LSB of 1.953 mV. The

read back of this register is set to 0B01(hex) to represent

5.5 V.

This manufacture specific command instructs the device

on what action to take in response to an output over current

average fault. The device also:

• Sets the IOUT bit in the STATUS_WORD

• Sets the None of the above bit in the STATUS_BYTE

• Sets the OCP Average Fault Bit #7 in the

STATUS_MFR_SPECIFIC

• Notifies the host by asserting the ALERTB

IC_DEVICE_ID (ADh)

The fault bit once set is cleared only in accordance with

“ClearFaults” section and not when the fault condition is

removed. The contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

The default of this register is set to 80(hex) ⇒ latch off

behavior The data byte is encoded in the format shown

below

IC_DEVICE_ID command is used to read the type or part

number of the IC embedded within a PMBUS that is used for

the PMBUS interface. This command is read accessible and

has two data bytes. The Block Read format needs to be used

to access this register for read operation. The lower byte

represents the number of bytes and this is fixed to

1(00000001b). The higher byte is used to represent the

IC_DEVICE_ID.

Bits

Description

Value

Meaning

7:6

00

Chip continues operation without interruption while maintaining the output current at

the values set by IOUT_OC_FAULT_LIMIT without regard to the output voltage

01

10

Chip continues operating indefinitely except if VOUT_UV is detected

The chip continues to operate, maintaining the output current at the value set by

IOUT_OC_FAULT_LIMIT without regard to the output voltage. For the delay time set

by bits[2:0]. If the chip is still operating in current limiting at the end of the delay time ,

the chip responds as programmed by the Retry Setting in bits[5:3]

11

The chip shuts down and responds as programmed by the Retry setting in bits[5:3]

5:3

2:0

Retry

Setting(Latchoff

or Hiccup)

000

A zero value for the retry setting means that the chip does not attempt to restart. The

output remains disabled until the faulty is cleared

001−110

Not Supported

111

The chip attempts to restart continuously without limitation, until it is commanded OFF

(by the ENABLE pin or OPERATION command or both), VIN/VCC is removed or an-

other fault condition causes the unit to shutdown. Hiccup time is 1 second

Delay Time

XXX

000 – 160−320 ms

001 – 320−480 ms

010 – 640−800 ms

011 – 1.28−1.44 ms

100 – 2.56−2.72 ms

101 – 5.12−5.28 ms

110 – 9.6−9.76 ms

111 – 10.08−10.24 ms

NOTE: An attempt to write “Not supported” data given in the table above will flag an invalid data fault.

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44

FAN251030

IOUT_AVG_FAULT_LIMIT (C5h)

Examples

IOUT_AVG_FAULT Limit

This manufacturer specific command sets the value of the

output current in amperes that causes an average over current

detection fault flag. The IOUT_AVG_FAULT_LIMIT

command has two data bytes encoded in LINEAR11 format

(5 bits signed exponent and 11 bits mantissa). The range,

resolution and default are shown in the below table.

PMBUS Data

E0A0(hex)

E0F0(hex)

E140(hex)

E1E0(hex)

E280(hex)

E2D0(hex)

10 A

15 A

20 A

30 A

40 A

45 A

Range

Resolution

Default

1−64 A

62.5 mA

45 A(E2D0(hex))

The contents of this register can be stored to nonvolatile

memory using the STORE_USER_ALL command. Few

examples are given in the Table below. The exponent is read

only and if an exponent other than −4(11100b) is written, an

invalid data fault is flagged. The 0A setting is not allowed

and there is no maximum value range check on this

command.

PCT_VOUT_LIMIT (C6h)

This manufacturer specific command sets the value of the

output voltage in terms of %, the level that causes an output

under voltage, over voltage 1, over voltage 2 fault.

The PCT_VOUT_LIMIT command has two data bytes

encoded in LINEAR16 format. The contents of this register

can be stored to nonvolatile memory using the

STORE_USER_ALL command. The below table shows all

the options allowed

OVP2

UVLO

Thresh(Fault)

Thresh

55%

60%

65%

70%

75%

80%

85%

90%

OVP1 Thresh (Warn)

Bit<11:9>

000

Bit<8:6>

000

Bit<5:3>

000

110%

112%

114%

116%

118%

120%

122%

124%

N/A

001

N/A

001

010

106%

108%

110%

112%

114%

116%

010

011

100

101

110

111

Default is set to OVP Warn: 108%, OVPFault−116%,

UVLO Fault−75% (Default = 06E0(hex)).

OVP Warn threshold needs to be less than OVP Fault

threshold. UVLO Fault threshold needs to be less than OVP

Fault and Warn threshold.

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45

FAN251030

PCT_PGOOD_LIMIT (C7h)

This manufacture specific command sets the value of the

good on and off levels in %. The PCT_PGOOD_LIMIT

command has one byte. The contents of this register can be

Bit #

Function

Default

0

1

2

3

4

5

6

7

“1” Disable Select VSET pin Select VSET(0)

CCM(0)

stored

STORE_USER_ALL command.

The below table shows all the options allowed

to

nonvolatile

memory

using

the

“1” Enable LS on for OVP1

Unused

LS off (0)

0

Input IMON<3:0>

1010

Bit<5:3>

000

PGOOD ON

84%

Bit<2:0>

000

PGOOD OFF

82%

84%

86%

88%

90%

92%

94%

96%

001

86%

001

010

88%

010

011

90%

011

VSET pin resistor (with up to 1% tolerance) is used to set the

initial Vout setting of the device. The table shows the

mapping from various resistors to the selected Vout and gain

setting. A MFR_MODE_SETTINGS bit<0> is used to

100

92%

100

101

94%

101

110

96%

110

select this initial V

value or not.

SET

111

98%

111

V

SET

Resistor

V

OUT

Preset

The default PGOOD ON level is set to 90% and default

PGOOD OFF level is set to 84% (19(hex)). If PGOOD_ON

level is set to a value which is less than PGOOD_OFF level

an invalid data fault is flagged.

Value (V)

0.6

Value (kW)

Short

0.845

1.3

Gain

1

0.6

1

0.9

MFR_MODE_SETTINGS (C8h)

This manufacture specific command sets

• CCM behavior,

1

1.78

0.95

1

2.32

• Enable/Disable VSET pin,

• Turn on/off LS FET at OV_WARN and

• Gain calibration for input current reporting

(READ_IIN)

1

2.87

1.05

1.2

1

3.48

1

4.12

1.25

1.5

1

4.75

This is a one byte command. The contents of this register

can be stored to nonvolatile memory using the

STORE_USER_ALL command. The below table shows all

the options allowed

1

5.49

1.8

0.5

0.25

1

6.19

2.1

6.98

2.5

7.87

3.3

8.87

5

10 & greater value

0.8

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46

FAN251030

MFR_PMBUS_BASE (C9h)

MFR_ID2 (CAh)

This manufacture specific command sets part of the base

part of the PMBUS address. ADDR pin resistor (with up to 1%

tolerance) is used to set the PMBUS address of the device.

This is a one byte command. The contents of this register

can be stored to nonvolatile memory using the

STORE_USER_ALL command.

The table shows the mapping from ADDR pin resistors to

the selected PMBUS address. The base part of the address

comes from the MFR_PMBUS_BASE command. Base

address is added to the offset from the below table to

generate the 7 bit PMBUS address used for all the PMBUS

communication.

This manufacture specific command provides an option

for customers who need 16 bits of manufacture’s ID (name,

abbreviation or symbol that identifies the unit’s

manufacturer). This is a two byte command accessible for

read and write. The contents of this register can be stored to

nonvolatile memory using the STORE_USER_ALL

command.

PMBUS Device Fault Management Clearing Warning or

Fault Bits

All of the warning or fault bits (except PGOOD fault) set

in the status registers remain set , even if the fault or warning

condition is removed or corrected until one of the following

occur:

• Bit is individually cleared

• Device receives a CLEAR_FAULTS command

To change the base address, use the current base address

(factory default is 7’10h) to write the new/desired address to

this register. All subsequent data transactions use the revised

base address.

When an ARA command is received by the FAN2510XY,

it responds by sending its slave address. This functionality

is supported only when the base address is 7’40h or greater.

The FAN2510XY should not be used with a base address

less than 40h in systems employing ARA functionality, as it

will result in an incorrect device response to the system.

• The output is commanded through the ENABLE pin,

the OPERATION command, or the combined action of

ENABLE pin and OPERATION command to turn OFF

and then turn back on, or

• Bias power is removed from the PMBUS device. This

means that VDD or VIN supply collapses below the

level

ADDR Resistor

The two exceptions to the above rule that status bits

remain set are the OFF and POWERGOOD# bits. These bits

always reflect the current state of the device and the

POWER_GOOD signal.

Value (kW)

0 (short)

0.845

1.3

Offset Address (h) PMBUS Address (h)

−

0F

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

−

Base+00

Base+01

Base+02

Base+03

Base+04

Base+05

Base+06

Base+07

Base+08

Base+09

Base+0A

Base+0B

Base+0C

Base+0D

0F

Clearing Individual Bits

1.78

Any or all the bits in any status register except

STATUS_BYTE and STATUS_WORD can be directly

cleared by issuing the status command with one data byte

written. The data byte is a binary value. A 1 in any bit

position indicates that bit is to be cleared, if set, and

unchanged if not set. Examples of data bytes:

• 00010000b indicates that bit[4] is to be cleared and all

other bits are to be unchanged,

• 01100010b indicates that bits[6],[5] and [11] are to be

cleared and all other bits are to be unchanged

• 11111111b, or FFh, indicates all bits are to be cleared

2.32

2.87

3.48

4.12

4.75

5.49

6.19

6.98

7.87

Clearing Bits in the STATUS_BYTE and

STATUS_WORD

8.87

10

Most bits in the STATUS_BYTE and STATUS_WORD

are cleared by clearing the bit or all of the bits that cause the

bit in STATUS_BYTE or STATUS_WORD to be set. In

general, STATUS_BYTE and STATUS_WORD are the

logical OR of the bits in a lower level status register. Figure

10 shows this concept.

≥12.4

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47

FAN251030

Status

Bit<7> output over voltage fault

Bit<6> output over voltage warning

Bit<5> output under voltage

warning

Bit<4> output under voltage fault

Bit<3>output max or min warning

STATUS_WORD(Upper Byte)

OR

Gate

Bit<7> VOUT

Bit<2> ton max fault

Bit<1> ton max warning

Bit<0> Not Supported

Figure 13. Conceptual View of Creating Bits in STATUS_BYTE and STATUS_WORD

For example, if the VOUT_OV_FAULT bit is

STATUS_VOUT register is set, then the VOUT bit in the

STATUS_WORD is also set. When the

VOUT_OCV_FAULT bit in the STATUS_VOUT register is

cleared, the VOUT bit in the STATUS_WORD will be

cleared at the same time provided no other bits in the

STATUS_VOUT are set.

The output of the latch passes through a gate controlled by

the corresponding SMBALERT_MASK bit. If this bit is set,

the output of the latch is blocked from driving the

SMBALERT# circuit. If the SMBALERT_MASK bit is

cleared, the latch output is allowed to pass and drive the

SMBALERT# circuit. Figure 14 below gives a conceptual

illustration of how the SMBALERT# signal is generated.

When the SMBALERT# circuit detects the rising edge of

the latch output it asserts the SMBALERT# signal output

goes low).

The SMBALERT# signal remains asserted until is

cleared. It is cleared when the device successfully transmits

its address in response to receiving the Alert Response

Address. It is also cleared by a CLEAR_FAULTS command.

The latch can also be cleared by writing a 1 to corresponding

bit in the status register.

Conceptually the bit clearing commands act as pulses,

driving the reset pin on the latch only momentarily. This

means that if the vent is ongoing (the event detector is still

active) the output latch will immediately set again. As

described above, this will cause the SMBALERT# to

reassert if it had been previously cleared (and the

SMBALERT_MASK bit is not set). This also means that

host won’t be able to see the status bit get cleared.

OFF and POWERGOOD# bits cannot be cleared as they

always reflect the current state of the device.

Immediate Reassertion after Clearing if Condition is

still present

If the warning or fault condition is present when the bit is

cleared, the bit is immediately set again. The ALERTB# will

also be asserted again immediately after the status bit is

cleared. The SMBALERT_MASK command can be used to

prevent this behavior.

Conceptual View of How Status Bits and ALERTB#

Work

When some warning or fault event is detected a latch is set.

The output of this latch becomes the status bit in one of the

lower level status register (such as STATUS_VOUT). The

latch output may also be used, either by itself or OR’ed with

other status bits, to create the corresponding bit in

STATUS_BYTE or STATUS_WORD and to affect

SMBALERT#.

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48

FAN251030

Other status bits that can set the

same bit in

STATUS_BYTE/STATUS_WORD

Bit in

STATUS_BYTE/STATUS

_WORD Register

Event Detector

Output

CLEAR_FAULTS

SET

Q

LATCH

Bit in STATUS_X

Register

CLR

Write 1 to Status

register bit

SMBALERT

#

SMBAL

ERT#

Circuit

SMBALERT

_MASK Bit

CLEAR_F

AULTS

Device Address

sent in response

to the Alert

Response

Address while

SMBALERT#

asserted

Figure 14. Conceptual Schematic of Status Bits and SMBALERT#

PCB Layout Guideline

Place de−coupling capacitors for PVCC and VCC

adjacent to their respective IC pins and connect with widest

possible trace on the top layer. The other side of the bypass

caps may be connected with vias to the system GND plane,

and PGND.

All high−current nodes, such as PVIN, SW, VOUT, and

PGND, should have the shortest and widest copper possible

to reduce parasitic inductance and resistance. This helps

reduces switching noise and PCB temperature rise,

improving system performance.

It is recommended to create a location for a series boot

Place ceramic input bypass capacitors (C ) next to the

resistor (R

and PH pins. A low value (<5Ω) R

), in series with C

, between the BOOT

can be useful in

IN

BOOT

IC’s PVIN and PGND pins. Route directly to the IC on top

layer using the widest and shortest possible traces to reduce

series parasitics. Series L increases peak switching voltage

levels and may result in the necessity of adding a RC

snubber, which typically impacts efficiency. Input bulk

capacitors can be placed farther away from the IC.

The SW, PH, and BOOT pins contain high voltage

discontinuous switching signals with sharp edges. Care

should be taken to avoid capacitive coupling to noise

sensitive signals (FB, COMP, VSEN , VDIFF). Avoid

routing sensitive signals next to, or over/under on adjacent

layers without GND shields, to the discontinuous switching

signals.

BOOT

limiting peak SW voltages to safe levels, particularly when

elevated PVIN levels are used. R slows the rising SW

BOOT

edge and may be a useful RC snubber substitute, although

either can have a negative impact on efficiency. Use the

widest and most direct trace possible to reduce series

parasitics. Avoid adding stray, or parasitic, capacitance from

BOOT−GND.

The PVIN and PGND pins handle large, high frequency

currents. The use of thermal ties on PVIN and PGND

connections is not recommended, as this tends to raise

parasitic L. Multiple, direct connected vias are

recommended, instead.

ORDERING INFORMATION

Device

Current

Package

Shipping †

FAN251030MNTXG

35 A

WQFN34, 5.0 x 7.0 mm

4,000 / Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

The PMBus and AVSBus name and logo are trademarks of SMIF, Inc.

www.onsemi.com

49

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WQFN34 5x7, 0.5P

CASE 510CL

ISSUE B

DATE 08 DEC 2022

GENERIC

MARKING DIAGRAM*

XXXX = Specific Device Code

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

*This information is generic. Please refer to

XXXXXXXXX

AWLYYWW

A

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON06837H

WQFN34 5x7, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

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


型号：	FAN251030MNTXG
厂家：	ONSEMI
描述：	35A Synchronous Buck Regulator with PMBUS
文件：	总51页 (文件大小：1241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN251030MNTXG [ONSEMI]

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