FAN23SV65AMPX [ONSEMI]
降压稳压器，同步，15 A;
| 型号： | FAN23SV65AMPX |
| 厂家： | 
ONSEMI |
| 描述： | 降压稳压器，同步，15 A 稳压器 |
| 文件： | 总21页 (文件大小：1138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAN23SV65AMPX
Buck Regulator,
Synchronous, 15 A
Description
The FAN23SV65A is a highly efficient synchronous buck regulator.
The regulator is capable of operating with an input range from 7 V to
24 V and supporting up to 15 A continuous load currents. The device
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can operate from a 5 V rail ( 10%) if V , P , and P are
IN
VIN
VCC
connected together to bypass the internal linear regulator.
The FAN23SV65A utilizes ON Semiconductor’s constant on−time
control architecture to provide excellent transient response and to
maintain a relatively constant switching frequency. This device
utilizes Pulse Frequency Modulation (PFM) mode to maximize
light−load efficiency by reducing switching frequency when the
inductor is operating in discontinuous conduction mode at light loads,
while clamping the minimum frequency above the audible range with
ultrasonic mode.
PQFN34
CASE 483AM
Switching frequency and over−current protection can be
programmed to provide a flexible solution for various applications.
Output over−voltage, under−voltage, over−current, and thermal
shutdown protections help prevent damage to the device during fault
conditions. After thermal shutdown is activated, a hysteresis feature
restarts the device when normal operating temperature is reached.
MARKING DIAGRAM
$Y&Z&3&K
FAN23
SV65A
Features
• V Range: 7 V to 24 V Using Internal Linear Regulator for Bias
IN
• V Range: 4.5 V to 5.5 V with V /P /P
Connected to Bypass
IN
IN VIN VCC
Internal Regulator
$Y
&Z
&3
&K
= Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
= Specific Device Code
• High Efficiency: Over to 96% Peak
• Continuous Output Current: 15 A
• Internal Linear Bias Regulator
FAN23SV65A
• Accurate Enable Facilitates V UVLO Functionality
IN
• PFM Mode for Light−Load Efficiency
• Excellent Line and Load Transient Response
• Precision Reference: 1% Over Temperature
• Output Voltage Range: 0.6 to 5.5 V
• Programmable Frequency: 200 kHz to 1 MHz
• Programmable Soft−Start
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
• Low Shutdown Current
• Adjustable Sourcing Current Limit
• Internal Boot Diode
• Thermal Shutdown
• Halogen and Lead Free, RoHS Compliant
Applications
• Mainstream Notebooks
• Servers and Desktop Computers
• Game Consoles
• Telecommunications
• Storage
• Base Stations
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
June, 2018 − Rev. 2
FAN23SV65AMPX/D
FAN23SV65AMPX
ORDERING INFORMATION
Part Number
Operating
Temperature Range
Configuration
PFM with Ultrasonic Mode
Package
Output Current (A)
FAN23SV65AMPX
−40 to 125°C
15
34−Lead,
PQFN, 5.5 mm x 5.0 mm
TYPICAL APPLICATION DIAGRAMS
VIN = 19V
VIN = 19 V
R11
10 ꢀ
C10
2.2 ꢁF
C9
0.1 ꢁF
CIN
0.1 ꢁF
CIN
4x10 ꢁF
R7
64.9 kꢀ
PVCC
VIN
PVIN
VCC
EN
Ext
EN
C3
0.1 ꢁF
R8
VOUT = 1.2 V
BOOT
SW
10 kꢀ
FAN23SV65A
IOUT = 0 − 15 A
R7, R8 used for Accurate EN
R7, R8 open for Ext EN
L1
0.56 ꢁH
PGOOD
ILIM
SOFT−START
R2
1.5 kꢀ
C4
0.1 ꢁF
COUT
8x47 ꢁF
R5 1.47 kꢀ
R3
10 kꢀ
C5
100 pF
C7
15 nF
FREQ
FB
R9
54.9 kꢀ
R6
4.99 kꢀ
R4
10 kꢀ
AGND
PGND
Figure 1. Typical Application with VIN = 19 V
VIN = 5 V
R11
10 ꢀ
C10
2.2 ꢁ F
C9
0.1 ꢁ F
CIN
CIN
0.1 ꢁ F
4x10 ꢁ F
PVCC
VIN
PVIN
VCC
EN
Ext
EN
C3
0.1 ꢁ F
VOUT = 1.2 V
BOOT
SW
FAN23SV65A
= 0 − 15 A
IOUT
L1
0.56 ꢁ H
PGOOD
ILIM
SOFT−START
R2
1.5 kꢀ
C4
0.1 ꢁ F
COUT
8x47 ꢁ F
R5 1.47 kꢀ
R3
10 kꢀ
C5
100 pF
C7
15 nF
FREQ
FB
R9
54.9 kꢀ
R6
4.99 kꢀ
R4
10 kꢀ
AGND
PGND
Figure 2. Typical Application with VIN = 5 V
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2
FAN23SV65AMPX
FUNCTIONAL BLOCK DIAGRAM
VIN
BOOT PVIN
PVCC
VCC
Linear
Regulator
PVCC
VCC
VCC UVLO
ENABLE
1.26V/1.14V
PVCC
EN
VCC
VCC
10mA
Modulator
HS Gate
Driver
SS
FB
FB
Comparator
VREF
SW
PFM
Comparator
FREQ
Control
Logic
nd
2
Level OVP
x1.2
x1.1
x0.9
Comparator
PVCC
1st Level OVP
Comparator
LS Gate
Driver
Under−Voltage
Comparator
VCC
PGOOD
Thermal
Shutdown
10mA
Current Limit
Comparator
AGND
ILIM
PGND
Figure 3. Block Diagram
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3
FAN23SV65AMPX
PIN CONFIGURATION
5
5
7
6
4
2
1
3
4
6
8
9
8
3
2
7
1
9
PVIN 10
PVIN 11
34 NC
33 NC
NC
34
33
10 PVIN
PVIN
(P2)
11
12
13
NC
PVIN
FREQ
SS
FREQ
32
31
SW
32
31
SW
SW
SW 13
SS
AGND
(P1)
SW
(P3)
SW 14
SW 15
SW 16
SW 17
PGOOD 30
SW
SW
SW
SW
30 PGOOD
14
15
EN
29
28
27
EN
29
28
27
16
17
NC
FB
NC
FB
21
20
19
18
18
19
20
21
22
23
24
25
26
25
24
23
22
26
Figure 4. Pin Assignment (Bottom View)
Figure 5. Pin Assignment (Top View)
Description
PIN DEFINITIONS
Name
PVIN
VIN
Pad / Pin
P2, 5−11
1
Power input for the power stage
Power input to the linear regulator; used in the modulator for input voltage feed−forward
Power output of the linear regulator; directly supplies power for the low−side gate driver
and boot diode. Can be connected to VIN and PVIN for operation from 5 V rail
PVCC
25
VCC
PGND
AGND
SW
26
18−21
Power supply input for the controller
Power ground for the low−side power MOSFET and for the low−side gate driver
Analog ground for the analog portions of the IC and for substrate
Switching node; junction between high−and low−side MOSFETs
P1, 4, 23
P3, 2, 12−17, 22
3
BOOT
Supply for high−side MOSFET gate driver. A capacitor from BOOT to SW supplies the
charge to turn on the N−channel high−side MOSFET. During the freewheeling interval
(low−side MOSFET on), the high−side capacitor is recharged by an internal diode
connected to PVCC
ILIM
FB
24
27
29
31
32
Current limit. A resistor between ILIM and SW sets the current limit threshold
Output voltage feedback to the modulator
EN
Enable input to the IC. Pin must be driven logic high to enable, or logic low to disable
Soft−start input to the modulator
SS
FREQ
On−time and frequency programming pin. Connect a resistor between FREQ and AGND
to program on−time and switching frequency
PGOOD
NC
30
Power good; open−drain output indicating V
is within set limits
OUT
28, 33−34
Leave pin open or connect to AGND
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4
FAN23SV65AMPX
ABSOLUTE MAXIMUM RATINGS (T = 25°C, Unless otherwise specified)
A
Symbol
Parameter
Power Input
Conditions
Referenced to PGND
Min.
−0.3
−0.3
Max.
30.0
30.0
Unit
V
V
PVIN
V
IN
Modulator Input
Boot Voltage
Referenced to AGND
V
V
BOOT
Referenced to PVCC
−0.3
−0.3
30.0
33.0
V
V
Referenced to PVCC, < 20 ns
V
SW
SW Voltage to GND
Referenced to PGND, AGND
−1
−5
30.0
30.0
V
V
Referenced to PGND, AGND < 20 ns
Boot to SW Voltage
Boot to PGND
Referenced to SW
−0.3
−0.3
6.0
30
V
V
V
V
BOOT
Referenced to PGND
Gate Drive Supply Input Referenced to PGND, AGND
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
6.0
6.0
V
V
PVCC
V
Controller Supply Input
Current Limit Input
Referenced to PGND, AGND
Referenced to AGND
VCC
V
6.0
V
ILIM
V
Output Voltage Feedback Referenced to AGND
6.0
V
FB
EN
SS
V
Enable Input
Referenced to AGND
6.0
V
V
Soft Start Input
Frequency Input
Referenced to AGND
6.0
V
V
Referenced to AGND
6.0
V
FREQ
V
Power Good Output
Referenced to AGND
6.0
V
PGOOD
ESD
Electrostatic Discharge
Human Body Model, JESD22−A114
Charged Device Model, JESD22−C101
1000
2500
+150
+150
V
V
T
J
Junction Temperature
Storage Temperature
°C
°C
T
STG
−55
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Conditions
Referenced to PGND
Referenced to AGND
Min
Max.
Unit
V
PVIN
Power Input
7
7
24
24
V
V
V
IN
Modulator Input
T
Junction Temperature
Load Current
−40
+125
°C
J
I
T = 25°C, No Airflow
20
A
V
LOAD
A
VPVIN, VIN,
PV , V , and Gate Drive Supply Input
V
V
, V Connected for 5 V
PVCC
4.5
5.5
IN
IN
PVIN, IN
V
Rail Operation and Referenced to
PGND, AGND
PVCC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
FAN23SV65AMPX
THERMAL CHARACTERISTICS
(The thermal characteristics were evaluated on a 4−layer pcb structure (1 oz/1 oz/1 oz/1 oz) measuring 7 cm x 7 cm).
Symbol
Parameter
Typ.
35
Unit
°C/W
°C/W
°C/W
ꢂ
Thermal Resistance, Junction−to−Ambient
JA
ꢂ
Thermal Characterization Parameter, Junction−to−Top of Case
Thermal Characterization Parameter, Junction−to−PCB
2.7
2.3
JC
ꢂ
JPCB
ELECTRICAL CHARACTERISTICS (Unless otherwise noted; V = 12 V, V
=1.2 V, and T = T = −40 to +125°C. (Note 2)
OUT A J
IN
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
SUPPLY CURRENT
I
Shutdown Current
Quiescent Current
EN = 0 V
EN = 5 V, Not Switching
EN =5 V, f = 500 kHz
16
ꢁ A
mA
mA
VIN,SD
I
1.8
VIN,Q
IVIN,GateCharge Gate Charge Current
22
sw
LINEAR REGULATOR
V
Regulator Output Voltage
Regulator Current Limit
4.75
60
5.05
5.25
V
REG
REG
I
mA
REFERENCE, FEEDBACK COMPARATOR
V
FB Voltage Trip Point
FB Pin Bias Current
590
596
0
602
100
mV
nA
FB
FB
I
−100
MODULATOR
t
On−Time Accuracy
R
= 56.2 kꢀ,
FREQ
−20
20
%
ON
V
=10 V,
IN
t
=250 ns, No Load
ON
t
Minimum SW Off−Time
Minimum SW On−Time
Minimum Duty Cycle
320
45
374
ns
ns
OFF,MIN
t
ON,MIN
D
FB = 1 V
0
%
MIN
f
Minimum Frequency Clamp
18.2
25.4
32.7
kHz
MINF
SOFT−START
I
Soft−Start Current
SS = 0.5 V
SS < 0.6 V
7
10
13
ꢁ A
%
SS
t
SS On−Time Modulation
25
100
ON,SSMOD
VSSCLAMP,NOM Nominal Soft−Start Voltage
V
= 0.6 V
400
40
mV
FB
Clamp
VSSCLAMP,OVL
Soft−Start Voltage Clamp in
Overload Condition
V
=0.3 V,
mV
mV
FB
OC Condition
PFM ZERO−CROSSING DETECTION COMPARATOR
V
OFF
ZCD Offset Voltage
T = T = 25°C
A
−6
0
J
CURRENT LIMIT
I
Valley Current Limit Accuracy
T = T = 25°C,
−10
−1
10
1
%
LIM
A
J
IVALLEY=18 A
VILIM,OFFSET
Comparator Offset
mV
K
ILIM
I
Set−Point Scale Factor
85
LIM
I
Temperature Coefficient
4000
ppm/°C
LIMTC
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FAN23SV65AMPX
ELECTRICAL CHARACTERISTICS (Unless otherwise noted; V = 12 V, V
=1.2 V, and T = T = −40 to +125°C. (Note 2)
OUT A J
IN
Symbol
ENABLE
Parameter
Condition
Min.
Typ.
Max.
Unit
V
Rising Threshold
1.11
1.26
122
1.14
4.5
1.43
V
mV
V
TH+
V
HYST
Hysteresis
V
Falling Threshold
Enable Voltage Clamp
Clamp Current
1.00
4.3
1.28
TH−
ENCLAMP
V
I
IEN = 20 ꢁ A
V
24
100
76
ꢁ A
nA
ꢁ A
ENCLAMP
I
Enable Pin Leakage
Enable Pin Leakage
EN = 1.2 V
EN = 5 V
ENLK
ENLK
I
UVLO
V
ON
V
CC
Good Threshold Rising
4.4
V
V
HYS
Hysteresis Voltage
160
mV
FAULT PROTECTION
V
PGOOD UV Trip Point
PGOOD OV Trip Point
Second OV Trip Point
On FB Falling
On FB Rising
86
89
111
122
92
115
125
125
2.03
1
%
%
UVP
V
108
118
VOP1
OVP2
V
On FB Rising; LS = On
%
R
PGOOD Pull−Down Resistance IPGOOD = 2 mA
PGOOD Soft−Start Delay
ꢀ
PGOOD
tPG,SSDELAY
0.82
1.42
ms
ꢁ A
I
PGOOD Leakage Current
PG,LEAK
THERMAL SHUTDOWN
T
Thermal Shutdown Trip Point
(Note 1)
155
15
°C
°C
OFF
T
HYS
Hysteresis (Note 1)
INTERNAL BOOTSTRAP DIODE
V
Forward Voltage
Reverse Leakage
I = 10 mA
0.6
V
FBOOT
F
I
R
V
R
= 24 V
1000
ꢁ
A
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design; not production tested.
2. Device is 100% production tested at T = 25°C. Limits over that temperature are guaranteed by design.
A
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7
FAN23SV65AMPX
TYPICAL PERFORMANCE CHARACTERISTICS
Tested using evaluation board circuit shown in Figure 1 with V = 19 V, V
= 1.2 V, F = 500 kHz, T = 25°C, and no airflow;
IN
OUT
sw
A
unless otherwise specified.
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
19VIN_5VOUT_500KHZ_1.2UH
12VIN_5VOUT_500KHZ_1.2UH
12VIN_3.3VOUT_500KHZ_1.2UH
12VIN_1.2VOUT_500KHZ_0.56UH
12VIN_1.05VOUT_500KHZ_0.4UH
19VIN_3.3VOUT_500KHZ_1.2UH
19VIN_1.2VOUT_500KHZ_0.56UH
19VIN_1.05VOUT_500KHZ_0.4UH
40
30
20
20
10
0.01
0.1
1
0.01
0.1
1
10
20
Load Current (A)
Load Current (A)
Figure 6. Efficiency vs. Load Current with VIN = 19 V
and fSW = 500 kHz
Figure 7. Efficiency vs. Load Current with VIN = 12 V
and fSW = 500 kHz
100
90
80
70
60
100
90
80
70
60
50
50
12VIN_1.2VOUT_300KHZ_0.72UH
19VIN_1.2VOUT_300KHZ_0.72UH
40
40
19VIN_1.2VOUT_500KHZ_0.56UH
12VIN_1.2VOUT_500KHZ_0.56UH
30
30
19VIN_1.2VOUT_1MHZ_0.3UH
12VIN_1.2VOUT_1MHZ_0.3UH
20
20
0.01
0.1
1
10
0.01
0.1
1
10
Load Current (A)
Load Current (A)
Figure 8. Efficiency vs. Load Current with
Figure 9. Efficiency vs. Load Current with
VIN = 12 V and VOUT = 1.2 V
V
IN = 19 V and VOUT = 1.2 V
100
90
80
70
60
50
100
90
80
70
60
50
12VIN_1.05VOUT_500KHZ_0.4UH
12VIN_1.2VOUT_300KHZ_0.72UH
12VIN_1.2VOUT_500KHZ_0.56UH
12VIN_1.2VOUT_1MHZ_0.3UH
12VIN_3.3VOUT_500KHZ_1.2UH
12VIN_5VOUT_500KHZ_1.2UH
19VIN_5VOUT_500KHZ_1.2UH
19VIN_3.3VOUT_500KHZ_1.2UH
19VIN_1.2VOUT_300KHZ_0.72UH
19VIN_1.2VOUT_500KHZ_0.56UH
19VIN_1.05VOUT_500KHZ_0.4UH
19VIN_1.2VOUT_1MHZ_0.3UH
0
5
10
15
20
0
5
10
15
20
Load Current (A)
Load Current (A)
Figure 10. Efficiency vs. Load Current with
VIN = 19 V
Figure 11. Efficiency vs. Load Current with
VIN = 12 V
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FAN23SV65AMPX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Tested using evaluation board circuit shown in Figure 1 with V = 19 V, V
= 1.2 V, F = 500 kHz, T = 25°C, and no airflow;
IN
OUT
sw A
unless otherwise specified.
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
19VIN_1.2VOUT_1MHz_0.3uH
19VIN_1.2VOUT_500kHz_0.56uH
19Vin_1.2Vout_300kHz_0.72uH
12VIN_1.2VOUT_1MHz_0.3uH
12VIN_1.2VOUT_500kHz_0.56uH
12VIN_1.2VOUT_300kHz_0.72uH
0
5
10
15
20
0
5
10
15
20
Load Current (A)
Load Current (A)
Figure 12. Case Temperature Rise vs. Load Current on
4 Layer PCB, 1 oz Copper, 7 cm x 7 cm
Figure 13. Case Temperature Rise vs. Load Current
on 4 Layer PCB, 1 oz Copper, 7 cm x 7 cm
1.22
1.215
1.21
1.22
1.215
1.21
1.205
1.2
1.205
1.2
1.195
1.195
0A_1.2VOUT
19VIN_1.2VOUT
1.19
1.19
15A_1.2VOUT
12VIN_1.2VOUT
1.185
1.185
1.18
1.18
0
2
4
6
8
10
7
9
11 13 15 17 19 21 23 25
Input Voltage (V)
Load Current (A)
Figure 14. Load Regulation
Figure 15. Line Regulation
EN (5 V/div)
EN (5 V/div)
V
= 19 V
= 0 A
V
= 19 V
= 15 A
IN
IN
Soft Start (0.5 V/div)
Soft Start (0.5 V/div)
I
I
OUT
OUT
V
OUT
(0.5 V/div)
V
OUT
(0.5 V/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (500 ꢁ s/div)
Time (500 ꢁ s/div)
Figure 16. Startup Waveforms with 0 A Load Current
Figure 17. Startup Waveforms with 15 A Load Current
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FAN23SV65AMPX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Tested using evaluation board circuit shown in Figure 1 with V = 19 V, V
= 1.2 V, F = 500 kHz, T = 25°C, and no airflow;
IN
OUT
sw
A
unless otherwise specified.
EN (5 V/div)
EN (5 V/div)
V
= 19 V
= 0 A
IN
Soft Start (0.5 V/div)
I
OUT
Soft Start (0.5 V/div)
V
(0.5 V/div)
OUT
V
= 19 V
= 15 A
IN
V
OUT
Prebias
I
OUT
V
OUT
(0.5 V/div)
PGOOD (5 V/div)
PGOOD (5 V/div)
Time (200 ꢁ s/div)
Time (500 ꢁ s/div)
Figure 18. Shutdown Waveforms with
15 A Load Current
Figure 19. Startup Waveforms with Pre−Bias
Voltage on Output
V
OUT
(20 mV/div)
V
OUT
(20 mV/div)
V
= 19 V
= 0 A
V
= 19 V
= 15 A
IN
IN
I
I
OUT
OUT
V
SW
(10 V/div)
V
SW
(10 V/div)
Time (20 ꢁ s/div)
Time (1 ꢁ s/div)
Figure 20. Static Load Ripple at No Load
Figure 21. Static Load Ripple at Full Load
V
OUT
(20 mV/div)
V
OUT
(20 mV/div)
V
= 19 V
= 1.2 V
V
= 19 V
= 1.2 V
IN
IN
I
(1 A/div)
OUT
V
OUT
V
OUT
I
(1 A/div)
OUT
Time (50 ꢁ s/div)
Time (50 ꢁ s/div)
Figure 22. Operation as Load Changes from 0 A to 3 A Figure 23. Operation as Load Changes from 3 A to 0 A
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FAN23SV65AMPX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Tested using evaluation board circuit shown in Figure 1 with V = 19 V, V
= 1.2 V, F = 500 kHz, T = 25°C, and no airflow;
IN
OUT
sw
A
unless otherwise specified.
V
OUT
(20 mV/div)
V
OUT
(20 mV/div)
V
IN
= 19 V, V
= 1.2 V
OUT
I
from 0 A to 7.5 A, 2.5 A/ꢁ s
OUT
I
(5 A/div)
OUT
I
(5 A/div)
OUT
V
IN
= 19 V, V
= 1.2 V
OUT
I
from 7.5 A, to 15 A, 2.5 A/ꢁ s
OUT
Time (100 ꢁ s/div)
Time (100 ꢁ s/div)
Figure 24. Load Transient from 0% to 50%
Load Current
Figure 25. Load Transient from 50% to 100%
Load Current
PGOOD indicates UVP
Level 2
Pull VOUT to 3.8 V
through 3 ꢀ resistor
PGOOG (5 V/div)
With V
falling in OCP
OUT
V
OUT
(1 V/div)
V (0.5 V/div)
fb
Level 1
V
OUT
(1 V/div)
Soft Start (1 V/div)
PGOOD (5 V/div)
I (10 A/div)
L
I
= 0 A then short output
OUT
V
SW
(10 V/div)
Time (20 ꢁ s/div)
Figure 26. Over−Current Protection with Heavy
Figure 27. Over−Voltage Protection Level 1
Load
and Level 2
www.onsemi.com
11
FAN23SV65AMPX
CIRCUIT OPERATION
The FAN23SV65A uses a constant on−time modulation
architecture with VIN feed−forward input to
accommodate a wide VIN range. This method provides
normal operating range. The resistor value can be calculated
from the following equation:
a
V
IN,max * VEN,Clamp,min
22 ꢁ A
REN
u
(eq. 2)
fixed switching frequency (f ) operation when the
SW
inductor operates in Continuous Conduction Mode (CCM)
and variable frequency when operating in Pulse Frequency
Mode (PFM) at light loads. Additional benefits include
excellent line and load transient response, cycle−by−cycle
current limiting, and no loop compensation is required.
At the beginning of each cycle, FAN23SV65A turns on
Constant On−time Modulation
The FAN23SV65A uses a constant on−time modulation
technique, in which the HS MOSFET is turned on for a fixed
time, set by the modulator, in response to the input voltage
and the frequency setting resistor. This on−time is
proportional to the desired output voltage, divided by the
input voltage. With this proportionality, the frequency is
essentially constant over the load range where inductor
current is continuous.
the high−side MOSFET (HS) for a fixed duration (t ). At
ON
the end of t , HS turns off for a duration (t ) determined
ON
OFF
by the operating conditions. Once the FB voltage (V ) falls
FB
below the reference voltage (V ), a new switching cycle
REF
For buck converter in Continuous−Conduction Mode
(CCM), the switching frequency f is expressed as:
begins.
SW
The modulator provides a minimum off−time (t
)
OFF−MIN
VOUT
VIN tON
fSW
+
of 320 ns to provide a guaranteed interval for low−side
MOSFET (LS) current sensing and PFM operation. Toffmin is
also used to provide stability against multiple pulsing and
limits maximum switching frequency during transient
events.
(eq. 3)
The on−time generator sets the on−time (t ) for the
ON
high−side MOSFET, which results in the switching
frequency of the regulator during steady−state operation. To
maintain a relatively constant switching frequency over a
wide range of input conditions, the input voltage
information is fed into the on−time generator.
Enable
The enable pin can be driven with an external logic signal,
connected to a resistive divider from PVIN/Vin to ground to
create an Under−Voltage Lockout (UVLO) based on the
PVIN/VIN supply, or connected to PVIN/VIN through a
single resistor to auto−enable while operating within the EN
pin internal clamp current sink capability.
The EN pin can be directly driven by logic voltages of 5 V,
3.3 V, 2.5 V, etc. If the EN pin is driven by 5 V logic, a small
current flows into the pin when the EN pin voltage exceeds
the internal clamp voltage of 4.3 V. To eliminate clamp
current flowing into the EN pin use a voltage divider to limit
the EN pin voltage to < 4 V.
tON is determined by:
CtON
ItON
tON
+
+
2 V
(eq. 4)
(eq. 5)
where ItON is:
VIN
RFREQ
1
10
ItON
where R
is the frequency−setting resistor described
FREQ
in the Setting Switching Frequency section; C
is the
tON
internal 2.2 pF capacitor; and I
is the V feed−forward
tON
IN
current that generates the on−time.
The FAN23SV65A implements open−circuit detection on
the FREQ pin to protect the output from an infinitely long
on−time. In the event the FREQ pin is left floating, switching
of the regulator is disabled. The FAN23SV65A is designed
To implement the UVLO function based on PVIN/VIN
voltage level, select values for R7 and R8 in Figure 1 such
that the tap point reaches 1.26 V when VIN reaches the
desired startup level using the following equation:
for V input range 7 to 24 V, f 200 kHz to 1 MHz,
IN
SW
VIN,on
resulting in an I
ratio exceeding 1 to 15.
R7 + R8ǒ Ǔ
* 1
tON
(eq. 1)
VEN,on
As the ratio of V
to V increases, t
introduces
OUT
IN
OFF,min
where VIN,on is the input voltage for startup and V
is
a limit on the maximum switching frequency as calculated
in the following equation, where the factor 1.2 is included in
the denominator to provide some headroom for transient
operation:
EN,on
the EN pin rising threshold of 1.26 V. With R8 selected as
10 kꢀ, and V = 9 V the value of R7 is 61.9 kꢀ.
IN,on
The EN pin can be pulled high with a single resistor
connected from VIN to the EN pin. With VIN > 5.5 V a series
resistor is required to limit the current flow into the EN pin
clamp to less than 24 ꢁ A to keep the internal clamp within
VOUT
ǒ1 * Ǔ
Vin,min
fSW +t
(eq. 6)
1.2 tOFF,min
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12
FAN23SV65AMPX
Soft−Start (SS)
filter of a 10 ꢀ resistor and 0.1 ꢁ F capacitor to minimize any
noise sources from the driver supply.
An Under−Voltage Lockout (UVLO) circuit monitors the
VCCvoltage to ensure proper operation. Once the VCC voltage
is above the UVLO threshold, the part begins operation after
an initialization routine of 50 ꢁ s. There is no UVLO circuitry
A conventional soft−start ramp is implemented to provide
a controlled startup sequence of the output voltage. A
current is generated on the SS pin to charge an external
capacitor. The lesser of the voltage on the SS pin and the
reference voltage is used for output regulation.
To reduce V
ripple and achieve a smoother ramp of the
on either the PVCC or V rails.
OUT
IN
output voltage, t is modulated during soft−start. T
starts at 50% of the steady−state on−time (PWM Mode) and
ramps up to 100% gradually.
ON
ON
Pulse Frequency Modulation (PFM)
One of the key benefits of using a constant on−time
modulation scheme is the seamless transitions in and out of
Pulse Frequency Modulation (PFM) Mode. The PWM
signal is not slave to a fixed oscillator and, therefore, can
operate at any frequency below the target steady−state
frequency. By reducing the frequency during light−load
conditions, the efficiency can be significantly improved.
The FAN23SV65A provides a Zero−Crossing Detector
(ZCD) circuit to identify when the current in the inductor
reverses direction. To improve efficiency at light load, the
LS MOSFET is turned off around the zero crossing to
eliminate negative current in the inductor. For predictable
operation entering PFM mode the controller waits for nine
consecutive zero crossings before allowing the LS
MOSFET to turn off.
During normal operation, the SS voltage is clamped to
400 mV above the FB voltage. The clamp voltage drops to
40 mV during an overload condition to allow the converter
to recover using the soft−start ramp once the overload
condition is removed. On−time modulation during SS is
disabled when an overload condition exists.
To maintain a monotonic soft−start ramp, the regulator is
forced into PFM Mode during soft−start. The minimum
frequency clamp is disabled during soft−start.
The nominal startup time is programmable through an
internal current source charging the external soft−start
capacitor C :
SS
ISS tSS
VREF
CSS
+
(eq. 7)
In PFM Mode, f varies or modulates proportionally to
SW
where:
the load; as load decreases, f
also decreases. The
SW
C
SS
= External soft−start programming capacitor;
switching frequency, while the regulator is operating in
PFM, can be expressed as:
I
t
= Internal soft−start charging current source, 10 ꢁ A;
= Soft−start time; and
SS
SS
2 L IOUT
VOUT
VIN
V
REF
= 600 mV
fSW
+
(eq. 8)
t2 (VIN * VOUT
)
ON
For example; for 1ms startup time, C = 15 nF. The
soft−start option can be used for ratiometric tracking. When
EN is LOW, the soft−start capacitor is discharged.
SS
where L is inductance and IOUT is output load current.
Minimum Frequency Clamp
To maintain a switching frequency above the audible
range, the FAN23SV65A clamps the switching frequency to
a minimum value of 18 kHz. The LS MOSFET is turned on
to discharge the output and trigger a new PWM cycle. The
minimum frequency clamp is disabled during soft−start.
Startup on Pre−Bias
FAN23SV65A allows the regulator to start on a pre−bias
output, V , and ensures V
OUT
is not discharged during the
OUT
soft−start operation.
To guarantee no glitches on VOUT at the beginning of the
soft−start ramp, the LS is disabled until the first
positivegoing edge of the PWM signal. The regulator is also
forced into PFM Mode during soft−start to ensure the
inductor current remains positive, reducing the possibility of
discharging the output voltage.
Protection Features
The converter output is monitored and protected against
over−current,
over−voltage,
under−voltage,
and
hightemperature conditions.
Over−Current Protection (OCP)
The FAN23SV65A uses current information through the
LS to implement valley−current limiting. While an OC
event is detected, the HS is prevented from turning on and
the LS is kept on until the current falls below the
user−defined set point. Once the current is below the set
point, the HS is allowed to turn on.
Internal Linear Regulator
The FAN23SV65A includes a linear regulator to facilitate
single−supply operation for self−biased applications. PVCC
is the linear regulator output and supplies power to the
internal gate drivers. The PVCC pin should be bypassed
with a 2. 2 ꢁ F ceramic capacitor. The device can operate
During an OC event, the output voltage may droop if the
load current is greater than the current the converter is
providing. If the output voltage drops below the UV
threshold, an overload condition is triggered. During an
overload condition, the SS clamp voltage is reduced to
from a 5 V rail if the V , P , and P
together to bypass the internal linear regulator.
pins are connected
IN VIN
VCC
VCC Bias Supply and UVLO
The VCC rail supplies power to the controller. It is
generally connected to the PVCC rail through a lowpass
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13
FAN23SV65AMPX
40 mV and the on−time is fixed at the steady−state duration.
In certain applications, especially designs utilizing only
ceramic output capacitors, there may not be sufficient ripple
magnitude available on the feedback pin for stable
operation. In this case, an external circuit consisting of 2
resistors (R2 and R6) and 2 capacitors (C4 and C5) can be
added to inject ripple voltage into the FB pin (see Figure 1).
There are some specific considerations when selecting the
RCC ripple injector circuit. For typical applications, use
4.99 kꢀ for R6, the value of C4 can be selected as 0.1 ꢁ F and
approximate values for R2 and C5 can be determined using
the following equations.
By nature of the control method; as VOUT drops, the
switching frequency is lower due to the reduced rate of
inductor current decay during the off−time.
The ILIM pin has an open−detection circuit to provide
protection against operation without a current limit.
Under−Voltage Protection (UVP)
If VFB is below the under−voltage threshold of −11% V
REF
(534 mV), the part enters UVP and PGOOD pulls LOW.
Over−Voltage Protection (OVP)
There are two levels of OV protection: +11% and +22%.
During an OV event, PGOOD pulls LOW.
R2 must be small enough to develop 12 mV of ripple:
(VIN * VOUT) VOUT
VIN 0.012 V C4 fSW
R2 t
(eq. 11)
When V is > +11% of V
(666 mV), both HS and LS
FB
REF
turn off. By turning off the LS during an OV event, V
overshoot can be reduced when there is positive inductor
current by increasing the rate of discharge. Once the V
R2 must be selected such that the R2C4 time constant
enables stable operation:
OUT
FB
0.33 2ꢄ fSW LOUT COUT
R2 t
(eq. 12)
voltage falls below V , the latched OV signal is cleared
REF
C4
and operation returns to normal.
A second over−voltage detection is implemented to
The minimum value of C5 can be selected to minimize the
capacitive component of ripple appearing on the feedback
pin:
protect the load from more serious failure. When V rises
FB
+22% above the V
(732 mV), the HS turns off until a
REF
LOUT COUT (R3 ) R4)
power cycle on VCC and the LS is forced on until 530 mV
of V
C5min
+
(eq. 13)
R2 R3 R4 C4
.
FB
Using the minimum value of C5 generally offers the best
transient response, and 100 pF is a good initial value in many
applications. However, under some operating conditions
excessive pulse jitter may be observed. To reduce jitter and
improve stability, the value of C5 can be increased:
Over−Temperature Protection (OTP)
FAN23SV65A incorporates an over−temperature
protection circuit that disables the converter when the
controller die temperature reaches 155°C. The IC restarts
when the die temperature falls below 140°C.
C5 ≥ 2 C5min
(eq. 14)
Power Good (PGOOD)
The PGOOD pin serves as an indication to the system that
the output voltage of the regulator is stable and within
regulation. Whenever V
window or the regulator is at overtemperature (UV, OV, and
OT), the PGOOD pin is pulled LOW.
5 V PVCC
The PVCC is the output of the internal regulator that
supplies power to the drivers and V . It is crucial to keep
this pin decoupled to PGND with a w1 ꢁ F X5R or X7R
ceramic capacitor. Because VCC powers internal analog
circuit, it is filtered from PVCC with a 10 ꢀ resistor and
0.1ꢅ ꢁ F X7R decoupling ceramic capacitor to AGND.
CC
is outside the regulation
OUT
PGOOD is an open−drain output that asserts LOW when
V
OUT
is out of regulation or when OT is detected.
Setting the Output Voltage (VOUT)
The output voltage V
highside MOSFET on−time interval when the valley of the
is regulated by initiating a
OUT
APPLICATION INFORMATION
Stability
divided output voltage appearing at the FB pin reaches
Constant on−time stability consists of two parameters:
V . Since this method regulates at the valley of the output
REF
stability criterion and sufficient signal at V
Stability criterion is given by:
.
FB
ripple voltage, the actual DC output voltage on V
is
OUT
offset from the programmed output voltage by the average
value of the output ripple voltage. The initial V setting
tON
RESR COUT uu
2
OUT
(eq. 9)
of the regulator can be programmed from 0.6 V to 5.5 V by
an external resistor divider (R3 and R4):
Sufficient signal requirement is given by:
R3
ꢃ
I
R
u
ꢃ
V
(eq. 10)
R4 +
I
N
D
E
S
R
F
B
(eq. 15)
VOUT
ǒ Ǔ* 1
VREF
where ꢃI
is the inductor current ripple and ꢃV is the
FB
IND
ripple voltage on V
FB, which should be w12 mV.
where V
is 600 mV.
REF
www.onsemi.com
14
FAN23SV65AMPX
For example; for 1.2 V V
and 10 kꢀ R3, then R4 is
at VIN = 19 V, with a resultant small increase in
פ
VIN ripple voltage above 120 mV used in the calculation. Also, each
10ꢅ ꢁ F can carry over 3 ARMS in the frequency range from
100 kHz to 1 MHz, exceeding the input capacitor current
rating requirements. An additional 0.1 ꢁ F capacitor may be
needed to suppress noise generated by high frequency
switching transitions.
OUT
10 kꢀꢆ For 600 mV V , R4 is left open. V is trimmed
OUT
FB
to a value of 596 mV when V
output voltage, including the effect of the output ripple
voltage, can be approximated by the equation:
= 600 mV, so the final
REF
Vrip
(eq. 16)
R3
R4
ƪ1 ) ƫ)
ƪ ƫ
VOUT + VFB
2
Output Capacitor Selection
Output capacitor C
RMS current I
is selected based on voltage rating,
rating, and capacitance. For
Setting the Switching Frequency (fSW)
OUT
f
is programmed through external R
as follows:
COUT(RMS)
SW
FREQ
capacitors having DC voltage bias derating, such as ceramic
capacitors, higher rating is highly recommended.
VOUT
20 VtON fSW
(eq. 17)
RFREQ
+
When calculating
requirement is the current load step transient. If the
unloading transient requirement (I transitioning from
C
,
usually the dominant
OUT
where C
= 2.2 pF internal capacitor that generates tON.
For example; for f = 500 kHz and V
tON
= 1.2 V, select a
SW
OUT
OUT
standard value for R
= 54.9 kꢀ.
FREQ
HIGH to LOW), is satisfied, then the load transient (I
OUT
transitioning LOW to HIGH), is also usually satisfied. The
unloading COUT calculation, assuming C has negligible
parasitic resistance and inductance in the circuit path, is
given by:
Inductor Selection
The inductor is typically selected based on the ripple
OUT
current (ꢃI ), which is usually selected as 25% to 45% of the
L
maximum DC load. The inductor current rating should be
selected such that the saturation and heating current ratings
exceed the intended currents encountered in the application
over the expected temperature range of operation.
Regulators that require fast transient response use smaller
inductance and higher current ripple; while regulators that
require higher efficiency keep ripple current on the low side.
The inductor value is given by:
I2MAX * I2
(VOUT ) ꢃ VOUT)
MIN
2 * V2
(eq. 21)
COUT + L
OUT
where IMAX and IMIN are maximum and minimum load
steps, respectively and ꢃVOUT is the voltage overshoot,
usually specified at 3 to 5%.
For example: for V = 12 V, V
= 1.2 V, 10 A IMAX, 5 A
I
OUT
I
, f
MIN SW
= 500 kHz, L
= 560 nH, and 4% ꢃV
OUT OUT
(VIN * VOUT)
ꢃ IL fSW
VOUT
VIN
deviation of 48 mV; the COUT value is calculated to be 356 ꢁ F.
This capacitor requirement can be satisfied using eight
47ꢅ ꢁ F, 6.3 V−rated X5R ceramic capacitors. This
calculation applies for load current slew rates that are faster
than the inductor current slew rate, which can be defined as
VOUT/L during the load current removal.
(eq. 18)
L +
For example: for 19 V V , 1.2 V V
, 15 A load, 25%
IN
OUT
ꢃ
I
,
a
n
d
5
0
0
k
H
z
f
;
L
i
s
5
7
6
n
H
,
a
n
d
a
s
t
a
n
d
a
r
d
v
a
l
u
e
o
f
L
SW
560 nH is selected.
Input Capacitor Selection
Setting the Current Limit
Input capacitor C is selected based on voltage rating,
IN
Current limit is implemented by sensing the inductor
valley current across the LS MOSFET VDS during the LS
on−time. The current limit comparator prevents a new
on−time from being started until the valley current is less
than the current limit.
The set point is configured by connecting a resistor from
the ILIM pin to the SW pin. A trimmed current is output onto
the ILIM pin, which creates a voltage across the resistor.
When the voltage on ILIM goes negative, an over−current
condition is detected.
RMS current I
rating, and capacitance. For
CIN(RMS)
capacitors having DC voltage bias derating, such as ceramic
capacitors, higher rating is strongly recommended. RMS
current rating is given by:
Ǹ
D (1 * D)
(eq. 19)
ICIN(RMS) + ILOAD*MAX
where I
is the maximum load current and D is
LOAD−MAX
the duty cycle V
V . The maximum I
occurs
OUT/ IN
CIN(RMS)
at 50% duty cycle.
The capacitance is given by:
R
ILIM
is calculated by:
ILOAD*MAX D (1 * D)
fSW ꢃ VIN
(eq. 20)
CIN
+
RILIM + 1.08 KILIM IVALLEY
(eq. 22)
where ꢃVIN is the input voltage ripple, normally 1% of
V .
where K
is the current source scale factor, and
ILIM
I
is the inductor valley current when the current limit
IN
VALLEY
threshold is reached. The factor 1.08 accounts for the
temperature offset of the LS MOSFET compared to the
control circuit.
For example; for V = 19 V, ꢃVIN = 120 mV, V
=
IN
OUT
1.2 V, 15 A load, and f = 500 kHz; C is 14.8 ꢁ F and
SW
IN
I
is 3.64 A . Select a minimum of three 10 ꢁ F 25
RMS
CIN(RMS)
With the constant on−time architecture, HS is always
turned on for a fixed on−time; this determines the
peak−to−peak inductor current.
V rated ceramic capacitors with X7R or similar dielectric,
recognizing that the capacitor DC bias characteristic
indicates that the capacitance value falls approximately 60%
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15
FAN23SV65AMPX
Current ripple ꢃI is given by:
Sensitive analog components including SS, FB, ILIM,
FREQ, and EN should be placed away from the highvoltage
switching circuits such as SW and BOOT and connected to
their respective pins with short traces. The inner PCB layer
closest to the FAN23SV65A device should have power
ground (PGND) under the power processing portion of the
device (PVIN, SW, and PGND). This inner PCB layer
should have a separate analog ground (AGND) under the P1
pad and the associated analog components. AGND and
PGND should be connected together near the IC between
PGND pins 18−21 and AGND pin 23, which connects to P1
thermal pad.
The AGND thermal pad (P1) should be connected to
AGND plane on inner layer using four 0.25 mm vias spread
under the pad. No vias are included under PVIN (P2) and
SW (P3) to maintain the PGND plane under the power
circuitry intact.
ǒV
Ǔ
IN * VOUT tON
ꢃ IL
+
(eq. 23)
L
From the equation above, the worst−case ripple occurs
during an output short circuit (where V is 0 V). This
should be taken into account when selecting the current limit
set point.
The FAN23SV15M uses valley−current sensing; the
) set point is the valley (I
The valley current level for calculating R
OUT
current limit (I
).
ILIM
VALLEY
is given by:
ILIM
ꢃ IL
2
IVALLEY + ILOAD(CL)
*
(eq. 24)
where I
is the DC load current when the current
limit threshold is reached.
LOAD (CL)
For example: In a converter designed for 15 A steadystate
operation and 4.5 A current ripple, the current−limit
threshold could be selected at 120% of I
accommodate transient operation and inductor value
decrease under loading. As a result, I is 18 A,
Power circuit loops that carry high currents should be
arranged to minimize the loop area. Primary focus should be
to minimize the loop for current flow from the input
capacitor to PVIN, through the internal MOSFETs, and
returning to the input capacitor. The input capacitor should
be as close to the PVIN terminals as possible.
to
LOAD,(SS)
LOAD,(CL)
I
= 15.75 A, and R
is selected as the standard
VALLEY
ILIM
value of 1.47 kꢀ.
The current return path from PGND at the low−side
MOSFET source to the negative terminal of the input
capacitor can be routed under the inductor and also through
vias that connect the input capacitor and lowside MOSFET
source to the PGND region under the power portion of the
IC.
Boot Resistor
In some applications, especially with higher input
voltage, the V ring voltage may exceed derating
guidelines of 80% to 90% of absolute rating for V . In this
situation a resistor can be connected in series with boot
SW
SW
capacitor (C3 in Figure 1) to reduce the turn−on speed of the
The SW node trace that connects the source of the
high−side MOSFET and the drain of the low−side MOSFET
to the inductor should be short and wide.
To control the voltage across the output capacitor, the
output voltage divider should be located close to the FB pin,
with the upper FB voltage divider resistor connected to the
positive side of the output capacitor and the bottom resistor
connected to the AGND portion of the FAN23SV65A
device.
When using ceramic capacitors with external ramp
injection circuitry (R2, C4, C5 in Figure 1), R2 and C4
should be connected near the inductor and coupling
capacitor C5 should be placed near FB pin to minimize FB
pin trace length.
high side MOSFET to reduce the amplitude of the V ring
SW
voltage. If necessary, a resistor and capacitor snubber can be
added from VSW to PGND to reduce the magnitude of the
ringing voltage. Please contact ON Semiconductor
Customer Support for assistance selecting a boot resistor or
snubber circuit in applications that operate above a 21 V
typical input voltage.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
GUIDELINES
The following points should be considered before
beginning a PCB layout using the FAN23SV65A. A sample
PCB layout from the evaluation board is shown in Figure 28
− Figure 31 following these layout guidelines.
Power components (input capacitors, output capacitors,
inductor, and FAN23SV65A device) should be placed on a
common side of the PCB in close proximity to each other
and connected using surface copper.
Decoupling capacitors for PVCC and VCC should be
located close to their respective device pins.
SW node connections to BOOT, ILIM, and ripple
injection resistor R2 should be through separate traces.
www.onsemi.com
16
FAN23SV65AMPX
Figure 28. Evaluation Board Top Layer Copper
Figure 29. Evaluation Board Inner Layer 1 Copper
www.onsemi.com
17
FAN23SV65AMPX
Figure 30. Evaluation Board Top Layer Copper
Figure 31. Evaluation Board Inner Layer 1 Copper
www.onsemi.com
18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN34 5X5.5, 0.5P
CASE 483AM
ISSUE A
DATE 02 JUL 2021
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13662G
PQFN34 5X5.5, 0.5P
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN34 5X5.5, 0.5P
CASE 483AM
ISSUE A
DATE 02 JUL 2021
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DOCUMENT NUMBER:
DESCRIPTION:
98AON13662G
PQFN34 5X5.5, 0.5P
PAGE 2 OF 2
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相关型号：
FAN2500S285
Fixed Positive LDO Regulator, 2.85V, 0.14V Dropout, CMOS, PDSO5, SOT-23, 5 PIN
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