FAN2110MPX [ONSEMI]

-10A,24V 输入,集成同步降压稳压器;
FAN2110MPX
型号: FAN2110MPX
厂家: ONSEMI    ONSEMI
描述:

-10A,24V 输入,集成同步降压稳压器

信息通信管理 开关 稳压器
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September 2015  
FAN2110 3-24 V Input, 10 A, High-Efficiency,  
Integrated Synchronous Buck Regulator  
Features  
Description  
The FAN2110 is a highly efficient, small footprint,  
constant frequency, 10 A integrated synchronous Buck  
regulator.  
.
.
.
.
.
.
Wide Input Voltage Range: 3 V-24 V  
Wide Output Voltage Range: 0.8 V to 80% VIN  
10 A Output Current  
The FAN2110 contains both synchronous MOSFETs  
and a controller/driver with optimized interconnects in  
one package, which enables designers to solve high-  
current requirements in a small area with minimal  
external components. Integration helps to minimize  
critical inductances making component layout simpler  
and more efficient compared to discrete solutions.  
1% Reference Accuracy Over Temperature  
Over 93% Peak Efficiency  
Programmable Frequency Operation: 200 KHz to  
600 KHz  
.
Fully Synchronous Operation with Integrated  
Schottky Diode on Low-Side MOSFET Boosts  
Efficiency  
The FAN2110 provides for external loop compensation,  
programmable switching frequency, and current limit.  
These features allow design flexibility and optimization.  
High frequency operation allows for all ceramic solutions.  
.
.
.
.
.
.
.
Internal Bootstrap Diode  
Power-Good Signal  
The summing current mode modulator uses lossless  
current sensing for current feedback and over-current  
protection. Voltage feedforward helps operation over a  
wide input voltage range.  
Starts up on Pre-Bias Outputs  
Accepts Ceramic Capacitors on Output  
External Compensation for Flexible Design  
Programmable Current Limit  
Fairchild’s advanced BiCMOS power process,  
combined with low-RDS(ON) internal MOSFETs and a  
thermally efficient MLP package, provide the ability to  
dissipate high power in a small package.  
Under-Voltage, Over-Voltage, and Thermal  
Shutdown Protections  
.
.
Internal Soft-Start  
Output over-voltage, under-voltage, and thermal  
shutdown protections help protect the device from  
damage during fault conditions. FAN2110 also prevents  
pre-biased output discharge during startup in point-of-  
load applications.  
5x6 mm, 25-Pin, 3-Pad MLP Package  
Applications  
.
.
.
.
.
Servers & Telecom  
Related Application Notes  
TinyCalc™ Calculator Design Tool  
Graphics Cards & Displays  
Computing Systems  
Point-of-Load Regulation  
Set-Top Boxes & Game Consoles  
AN-8022 — TinyCalc™ Calculator User Guide  
Ordering Information  
Operating  
Packing  
Part Number  
Temperature Range  
Package  
Method  
FAN2110MPX  
-40°C to 85°C  
Molded Leadless Package (MLP) 5 x 6 mm  
Tape and Reel  
FAN2110EMPX  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
Typical Application  
VIN  
P2  
15  
Boot  
Diode  
+5V  
CHF  
CIN  
VCC  
BOOT  
1
C4  
RRAMP  
Q1  
Q2  
CBOOT  
RAMP  
PGOOD  
EN  
25  
13  
14  
17  
18  
Power  
Good  
VOUT  
SW  
P1  
L
COUT  
Enable  
RILIM  
PWM  
+
DRIVER  
ILIM  
RT  
R(T)  
PGND  
P3  
POWER  
MOSFETS  
COMP  
AGND  
24 NC  
20  
16  
C2  
R1  
FB  
19  
C1  
C3  
RBIAS  
R2  
R3  
Figure 1. Typical Application Diagram  
Block Diagram  
5V  
BOOT  
VCC  
Boot  
Current Limit  
Diode  
IILIM  
Comparator  
VIN  
ILIM  
COMP  
FB  
Int ref  
CBOOT  
Error  
Amplifier  
R
S
Q
PWM  
Comparator  
Gate  
Drive  
Circuit  
VOUT  
SW  
L
SS  
VREF  
COUT  
CLK  
Summing  
Amplifier  
AGND  
PGND  
OSC  
RAMP  
GEN  
Current  
Sense  
EN  
RAMP  
Figure 2. Block Diagram  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
2
 
 
Pin Configuration  
RAMP  
NC  
SW  
SW  
P2  
VIN  
P1  
SW  
PGND  
PGND  
PGND  
SW  
SW  
P3  
GND  
Figure 3. MLP 5 x 6 mm Pin Configuration (Bottom View)  
Pin Definitions  
Pin #  
P1, 6-12  
P2, 2-5  
Name  
SW  
Description  
Switching Node. Junction of high-side and low-side MOSFETs.  
Power Conversion Input Voltage. Connect to the main input power source.  
VIN  
P3, 21-23  
PGND Power Ground. Power return and Q2 source.  
High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC  
1
BOOT  
PGOOD  
EN  
includes an internal synchronous bootstrap diode to recharge the capacitor on this pin to  
VCC when SW is LOW.  
Power-Good Flag. An open-drain output that pulls LOW when FB is outside the limits  
specified in electrical specs. PGOOD does not assert HIGH until the fault latch is enabled.  
13  
14  
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the  
regulator after a latched fault condition. This input has an internal pull-up when the IC is  
functioning normally. When a latched fault occurs, EN is discharged by a current sink.  
Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin.  
This pin should be decoupled to AGND through a > 2.2 µF X5R / X7R capacitor.  
15  
16  
17  
VCC  
AGND  
ILIM  
Analog Ground. The signal ground for the IC. All internal control voltages are referred to  
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.  
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the current-  
limit trip threshold lower than the internal default setting.  
Oscillator Frequency. A resistor (RT) from this pin to AGND sets the PWM switching  
frequency.  
18  
19  
20  
24  
25  
R(T)  
FB  
Output Voltage Feedback. Connect through a resistor divider to the output voltage.  
Compensation. Error amplifier output. Connect the external compensation network  
between this pin and FB.  
COMP  
NC  
No Connect. This pin is not used.  
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the ramp amplitude  
and provides voltage feedforward functionality.  
RAMP  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
3
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device  
reliability. The absolute maximum ratings are stress ratings only.  
Parameter  
VIN to PGND  
VCC to AGND  
BOOT to PGND  
BOOT to SW  
Conditions  
Min.  
Max.  
28  
Unit  
V
AGND=PGND  
Continuous  
6
V
35  
V
-0.5  
-0.5  
-5  
6.0  
V
24.0  
30  
V
SW to PGND  
All other pins  
ESD  
Transient (t < 20 ns, f < 600 KHz)  
V
-0.3  
2.0  
2.5  
VCC+0.3  
V
Human Body Model, JEDEC JESD22-A114  
Charged Device Model, JEDEC JESD22-C101  
KV  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to absolute maximum ratings.  
Symbol  
VCC  
VIN  
Parameter  
Bias Voltage  
Conditions  
VCC to AGND  
VIN to PGND  
Min.  
4.5  
3
Typ.  
Max.  
5.5  
Unit  
V
5.0  
Supply Voltage  
24  
V
TA  
Ambient Temperature  
Junction Temperature  
Switching Frequency  
-40  
+85  
+125  
600  
°C  
TJ  
°C  
fSW  
200  
kHz  
Thermal Information  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
+150  
+300  
Unit  
°C  
TSTG  
TL  
Storage Temperature  
-65  
Lead Soldering Temperature, 10 Seconds  
Thermal Resistance: Junction-to-Case  
°C  
P1 (Q2)  
P2 (Q1)  
P3  
4
7
°C/W  
°C/W  
°C/W  
°C/W  
W
JC  
4
Thermal Resistance: Junction-to-Mounting Surface(1)  
Power Dissipation, TA=25°C(1)  
35  
J-PCB  
PD  
2.8  
Note:  
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 35. Actual results  
are dependent on mounting method and surface related to the design.  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
4
 
Electrical Specifications  
Electrical specifications are the result of using the circuit shown in Figure 1 with VIN=12 V, unless otherwise noted.  
Symbol  
Parameter  
Conditions  
Min. Typ. Max. Unit  
Power Supplies  
SW=Open, VFB=0.7 V, VCC=5 V,  
fSW=600 KHz  
8
12  
mA  
ICC  
VCC Current  
Shutdown: EN=0, VCC=5 V  
Rising VCC  
7
10  
µA  
V
4.1  
4.3  
300  
4.5  
VUVLO  
Oscillator  
fSW  
VCC UVLO Threshold  
Hysteresis  
mV  
255  
540  
300  
600  
50  
345  
660  
65  
KHz  
KHz  
ns  
RT=50 Kto GND  
RT=24 Kto GND  
Frequency  
Minimum On-Time(2)  
Ramp Amplitude, Peak-to-Peak  
Minimum Off-Time(2)  
tONmin  
16 VIN, 1.8 VOUT, RT=30 K,  
RRAMP=200 K  
VRAMP  
0.53  
100  
V
tOFFmin  
150  
805  
ns  
Reference  
Reference Voltage (see Figure 4 for  
Temperature Coefficient)  
VFB  
795  
800  
mV  
Error Amplifier  
G
DC Gain(2)  
Gain Bandwidth Product(2)  
Output Voltage(2)  
80  
12  
85  
15  
dB  
MHz  
V
GBW  
VCOMP  
ISINK  
VCC=5 V  
0.4  
1.5  
0.8  
3.2  
Output Current, Sourcing  
VCC=5 V, VCOMP=2.2 V  
VCC=5 V, VCOMP=1.2 V  
VFB=0.8 V, 25°C  
2.2  
1.2  
mA  
mA  
nA  
ISOURCE Output Current, Sinking  
IBIAS FB Bias Current  
Protection and Shutdown  
-850 -650 -450  
RILIM=182 K, 25°C, fSW=500 KHz,  
VOUT=1.5 V, RRAMP=243 K  
16 Consecutive Clock Cycles(3)  
Current Limit (see Circuit  
ILIM  
12  
14  
16  
-9  
A
Description)(2)  
VCC=5 V, 25°C  
IILIM  
TTSD  
THYS  
VOVP  
VUVSD  
VFLT  
ILIM Current  
-11  
-10  
+155  
+30  
115  
73  
µA  
°C  
°C  
Over-Temperature Shutdown(2)  
Over-Temperature Hysteresis(2)  
Over-Voltage Threshold  
Under-Voltage Shutdown  
Fault Discharge Threshold  
Internal IC Temperature  
2 Consecutive Clock Cycles(3)  
16 Consecutive Clock Cycles(3)  
Measured at FB Pin  
110  
68  
121 %VOUT  
78  
%VOUT  
mV  
250  
250  
Measured at FB Pin (VFB ~500 mV)  
VFLT_HYS Fault Discharge Hysteresis  
mV  
Soft-Start  
tSS  
tEN  
VOUT to Regulation (T0.8)  
Fault Enable/SSOK (T1.0)(2)  
5.3  
6.7  
ms  
ms  
fSW=500 KHz  
Continued on the following page…  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
5
Electrical Specifications (Continued)  
Electrical specifications are the result of using the circuit shown in Figure 1 with VIN=12 V, unless otherwise noted.  
Symbol  
Parameter  
Conditions  
Min. Typ. Max. Unit  
Control Functions  
VEN  
EN Threshold, Rising  
VCC=5 V  
VCC=5 V  
VCC=5 V  
1.35 2.00  
V
VEN_HYS EN Hysteresis  
250  
800  
1
mV  
K  
µA  
REN  
EN Pull-Up Resistance  
IEN_DISC EN Discharge Current  
Auto-Restart Mode, VCC=5 V  
RFBok  
FB OK Drive Resistance  
PGOOD LOW Threshold  
800  
FB < VREF, 2 Consecutive Clock  
Cycles(3)  
VPGTH_LO  
-14  
-11  
-8  
%VREF  
FB > VREF, 2 Consecutive Clock  
Cycles(3)  
VPGTH_UP  
+7.0 +10.0 +13.5  
0.4  
VPG_LO PGOOD Output Low  
IOUT < 2 mA  
VPGOOD=5 V  
V
IPG_LK  
PGOOD Leakage Current  
0.2  
1.0  
µA  
Notes:  
2. Specifications guaranteed by design and characterization; not production tested.  
3. Delay times are not tested in production. Guaranteed by design.  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
6
 
Typical Characteristics  
1.010  
1.005  
1.000  
0.995  
0.990  
1.20  
1.10  
1.00  
0.90  
0.80  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
Temperature (oC)  
Temperature (oC)  
Figure 4. Reference Voltage (VFB  
)
Figure 5. Reference Bias Current (IFB  
)
vs. Temperature, Normalized  
vs. Temperature, Normalized  
1500  
1200  
900  
600  
300  
0
1.02  
1.01  
1.00  
0.99  
0.98  
600KHz  
300KHz  
-50  
0
50  
100  
150  
0
20  
40  
60  
80  
100  
120  
140  
Temperature (oC)  
RT (K)  
Figure 6. Frequency vs. RT  
Figure 7. Frequency vs. Temperature, Normalized  
1.4  
1.2  
1
1.04  
1.02  
1.00  
0.98  
0.96  
Q1 ~0.32%/°C  
Q2 ~0.35%/°C  
0.8  
0.6  
-50  
-50  
0
50  
100  
150  
0
50  
100  
150  
Temperature (oC)  
Temperature (°C)  
Figure 8. RDS vs. Temperature, Normalized  
(VCC=VGS=5 V), Figure 1  
Figure 9. ILIM Current (IILIM) vs. Temperature,  
Normalized  
© 2008 Fairchild Semiconductor Corporation  
FAN2110 • Rev. 1.12  
www.fairchildsemi.com  
7
Application Circuits  
FAN2110  
VIN  
VCC  
P2  
15  
+5V  
10-20 VIN  
2.2u  
X5R  
10K  
243K  
PGOOD  
13  
24  
20  
3.3n  
3 x 10u  
X5R  
VOUT  
RAMP  
25  
NC  
2.49K  
5.6n 120p  
COMP  
34  
2.49K  
BOOT  
FB  
ILIM  
EN  
1
* Cooper Industries  
HC8-1R2-R  
19  
17  
14  
18  
5.6n  
0.1u  
VOU  
S
P1  
182K  
1.2u *  
R(T)  
1.5  
30.1K  
2.80K  
4 x 47u  
X5R  
AGND  
PGND  
P3  
16  
390p  
3.3n  
Figure 10. Application Circuit: 1.5 VOUT, 10 A, 500 KHz (10 V-20 VIN)  
FAN2110  
100  
VIN  
VCC  
P2  
+5V  
VOU  
15  
3.3-5.5 VIN  
2.2  
u
10K  
1u  
X5R  
PGOOD  
13  
3.3n  
470u  
10u  
X5R  
NC 24  
140K  
4.99K  
3.3n 330p  
COMP  
RAMP  
BOOT  
20  
25  
1
100  
2.49K  
FB  
ILIM  
EN  
* Cooper  
HC8-R75-R  
19  
17  
14  
18  
2.2n  
u
0.1  
VOUT  
S
P1  
P3  
182K  
750n *  
R(T)  
1.5  
30.1K  
2.80K  
4 x 47u  
X5R  
AGND  
PGND  
16  
390p  
3.3n  
Figure 11. Application Circuit: 1.5 VOUT, 10 A, 500 KHz (3.3 V-5.5 VIN)  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
8
 
 
Typical Performance Characteristics  
Typical operating characteristics using the circuit in Figure 10. VIN=12 V, VCC=5 V, TA=25°C, unless otherwise specified.  
FAN2110_1.5V_500Khz  
FAN2110_3.3V_500Khz  
100  
95  
90  
85  
80  
75  
70  
100  
95  
90  
85  
80  
75  
70  
VIN = 10V  
VIN = 12V  
VIN = 16V  
VIN = 20V  
VIN = 10V  
VIN = 12V  
VIN = 16V  
VIN = 20V  
0
2
4
6
8
10  
0
2
4
6
8
10  
Load Current (Amps)  
Load Current (Amps)  
Figure 12. 1.5 VOUT Efficiency, 500 KHz  
Figure 13. 3.3 VOUT Efficiency, 500 KHz(4)  
FAN2110_1.5V_300Khz  
FAN2110_3.3V_300Khz  
100  
100  
95  
90  
85  
80  
75  
70  
95  
90  
85  
80  
75  
70  
VIN = 10V  
VIN = 12V  
VIN = 16V  
VIN = 20V  
VIN = 10V  
VIN = 12V  
VIN = 16V  
VIN = 20V  
0
2
4
6
8
10  
0
2
4
6
8
10  
Load Current (Amps)  
Load Current (Amps)  
Figure 14. 1.5 VOUT Efficiency, 300 KHz  
Figure 15. 3.3 VOUT Efficiency, 300 KHz(4)  
FAN2110_2.5V_600Khz  
FAN2110_1.5V_500K(3.3-5.5V)  
95  
90  
85  
80  
75  
70  
100  
95  
90  
85  
80  
75  
70  
VIN = 10V  
VIN = 12V  
VIN = 16V  
VIN = 20V  
VIN=3.5V  
VIN=4.5V  
VIN=5.5V  
0
2
4
6
8
10  
0
2
4
6
8
10  
Load Current (Amps)  
Load Current (Amps)  
Figure 16. 2.5 VOUT Efficiency ,600 KHz(4)  
Figure 17. 1.5 VOUT Efficiency, 500 KHz  
(VIN=3.3 V to 5 V), Figure 11  
Note:  
4. Circuit values for this configuration change in Figure 10.  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
9
 
Typical Performance Characteristics (Continued)  
Typical operating characteristics using the circuit in Figure 10. VIN=12 V, VCC=5 V, TA=25°C unless otherwise specified.  
Peak HS & LS Mosfet Tempr for 1.5V Output  
(Measured on Demo Board)  
Package Power Dissipation at various Vout(s)  
Fsw = 500Khz  
80  
70  
60  
50  
40  
30  
20  
10  
0
3
2.5  
2
1.5  
1
VIN=10V_HS  
VIN=10V_LS  
VIN=20V_HS  
VIN=20V_LS  
Vout = 1.5V  
Vout = 1.8V  
Vout = 3.3V  
0.5  
0
1
2
3
4
5
6
7
8
9
10  
0
2
4
6
8
10  
Load Current (A)  
Load Current (Amps)  
Figure 18. Peak MOSFET Temperatures, Figure 10  
Figure 19. Device Dissipation Over VOUT vs. Load  
Line Regulation Data  
Load Regulation  
0.05  
0.02  
0
0.01  
0
0
2
4
6
8
10  
-0.05  
-0.1  
5
10  
15  
20  
25  
-0.01  
-0.02  
-0.03  
-0.04  
-0.15  
-0.2  
VIN=10V  
VIN=20V  
No Load  
1A Load  
-0.25  
Input Voltage (Volts)  
Load Current (Amps)  
Figure 20. 1.5 VOUT Line Regulation  
Figure 21.  
1.5 VOUT Load Regulation  
Peak HS & LS Mosfet Tempr for 3.3V Output  
(Measured on Demo Board)  
Safe Operating Area curves for 70 Deg Temperature rise  
VIN = 20V, Natural Convection  
100  
80  
60  
40  
20  
0
12  
10  
8
6
4
VIN=10V_HS  
300K  
500K  
600K  
VIN=10V_LS  
VIN=20V_HS  
VIN=20V_LS  
2
0
0
2
4
6
8
10  
12  
14  
1
2
3
4
5
6
7
8
9
10  
Load Current (Amps)  
Output Voltage (Volts)  
Figure 23.  
Typical 20 VIN Safe Operation Area  
Figure 22. Peak MOSFET Temperatures, 3.3 V Output(5)  
(SOA), 70C Ambient Temperature, Natural  
Convection  
Note:  
5. Circuit values for this configuration change in Figure 10.  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
10  
 
 
 
Typical Performance Characteristics (Continued)  
Typical operating characteristics using the circuit in Figure 10. VIN=12 V, VCC=5 V, TA=25°C unless otherwise specified.  
VOUT  
VOUT  
VSW  
EN  
PGOOD  
PGOOD  
Figure 24. Startup, 10 A Load  
Figure 25. Startup with 1.0 V Pre-Bias on VOUT  
VOUT, 50mV/div  
VOUT  
EN  
VSW, 10V/Div  
PGOOD  
Figure 26. Shutdown, 10 A Resistive Load  
Figure 27. VOUT Ripple and SW Voltage, 10 A Load  
VOUT, 200mV/div  
IOUT, 5A/Div  
IOUT, 5A/Div  
EN, 2V/Div  
Figure 28. Transient Response, 0-8 A Load,  
5 A / µs Slew Rate  
Figure 29. Restart on Short Circuit (Fault)  
© 2008 Fairchild Semiconductor Corporation  
FAN2110 • Rev. 1.12  
www.fairchildsemi.com  
11  
Circuit Description  
PWM Generation  
1.35V  
EN  
FB  
Refer to Figure 2 for the PWM control mechanism.  
FAN2110 uses the summing-mode method of control to  
generate the PWM pulses. An amplified current-sense  
signal is summed with an internally generated ramp and  
the combined signal is compared with the output of the  
error amplifier to generate the pulse width to drive the  
high-side MOSFET. Sensed current from the previous  
cycle is used to modulate the output of the summing  
block. The output of the summing block is also  
compared against a voltage threshold set by the RLIM  
resistor to limit the inductor current on a cycle-by-cycle  
basis. RRAMP resistor helps set the charging current for  
the internal ramp and provides input voltage feed-  
forward function. The controller facilitates external  
compensation for enhanced flexibility.  
2400 CLKs  
0.8V  
Fault  
Latch  
Enable  
1.0V  
0.8V  
SS  
3200 CLKs  
4000 CLKs  
T0.8  
Initialization  
T1.0  
Once VCC exceeds the UVLO threshold and EN is  
HIGH, the IC checks for a shorted FB pin before  
releasing the internal soft-start ramp (SS).  
Figure 31. Soft-Start Timing Diagram  
VCC UVLO or toggling the EN pin discharges the  
internal SS and resets the IC. In applications where  
external EN signal is used, VIN and VCC should be  
established before the EN signal comes up to prevent  
skipping the soft-start function.  
If the parallel combination of R1 and RBIAS is 1 K,  
the internal SS ramp is not released and the regulator  
does not start.  
Enable  
Startup on Pre-Bias  
FAN2110 has an internal pull-up to the enable (EN) pin  
so that the IC is enabled once VCC exceeds the UVLO  
threshold. Connecting a small capacitor across EN and  
AGND delays the rate of voltage rise on the EN pin. The  
EN pin also serves for the restart whenever a fault  
occurs (refer to the Auto-Restart section). If the  
regulator is enabled externally, the external EN signal  
should go HIGH only after VCC is established. For  
applications where such sequencing is required,  
FAN2110 can be enabled (after the VCC comes up) with  
external control, as shown in Figure 30.  
The regulator does not allow the low-side MOSFET to  
operate in full synchronous mode until SS reaches 95%  
of VREF (~0.76 V). This enables the regulator to startup  
on a pre-biased output and ensures that pre-biased  
outputs are not discharged during the soft-start cycle.  
Protections  
The converter output is monitored and protected  
against extreme overload, short-circuit, over-voltage,  
under-voltage, and over-temperature conditions.  
Under-Voltage Shutdown  
If voltage on the FB pin remains below the under-  
voltage threshold for 16 consecutive clock cycles, the  
fault latch is set and the converter shuts down. This  
protection is not active until the internal SS ramp  
reaches 1.0 V during soft-start.  
Figure 30. Enabling with External Control  
Soft-Start  
Once internal SS ramp has charged to 0.8 V (T0.8), the  
output voltage is in regulation. Until SS ramp reaches  
1.0 V (T1.0), the fault latch is inhibited.  
To avoid skipping the soft-start cycle, it is necessary to  
apply VIN before VCC reaches its UVLO threshold. Normal  
sequence for powering up would be VINVCCEN.  
Soft-start time is a function of oscillator frequency.  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
12  
 
 
If auto-restart is not desired, tie the EN pin to the VCC  
pin or pull it HIGH after VCC comes up with a logic gate  
to keep the 1 µA current sink from discharging EN to  
1.1V. Figure 32 shows one method to pull up EN to VCC  
for a latch configuration.  
Over-Voltage Protection  
If voltage on the FB pin exceeds 115% of VREF for two  
consecutive clock cycles, the fault latch is set and  
shutdown occurs.  
A shorted high-side MOSFET condition is detected  
when SW voltage exceeds ~0.7 V while the low-side  
MOSFET is fully enhanced. The fault latch is set  
immediately upon detection.  
The OV/UV fault protection circuits above are active all  
the time, including during soft-start.  
Over-Temperature Protection (OTP)  
The chip incorporates an over-temperature protection  
circuit that sets the fault latch when a die temperature of  
about 150°C is reached. The IC restarts when the die  
temperature falls below 125°C.  
Auto-Restart  
Figure 32. Enable Control with Latch Option  
After a fault, EN pin is discharged by a 1 µA current sink  
to a 1.1 V threshold before the internal 800 Kpull-up  
is restored. A new soft-start cycle begins when EN  
charges above 1.35 V.  
Power-Good (PGOOD) Signal  
PGOOD is an open-drain output that asserts LOW  
when VOUT is out of regulation, as measured at the FB  
pin. Thresholds are specified in the Electrical  
Specifications section. PGOOD does not assert HIGH  
until the fault latch is enabled (T1.0) (see Figure 31).  
Depending on the external circuit, the FAN2110 can be  
configured to remain latched-off or to automatically  
restart after a fault.  
Table 1. Fault / Restart Configurations  
EN Pin  
Controller / Restart State  
Pull to GND  
OFF (Disabled)  
No Restart Latched OFF  
(After VCC Comes Up)  
Pull-up to VCC with 100K  
Open  
Immediate Restart After Fault  
New Soft-Start Cycle After:  
tDELAY (ms)=3.9 C(nf)  
Cap. to GND  
When EN is left open, restart is immediate.  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
13  
 
Application Information  
Bias Supply  
operate at a lower switching frequency. The inductor  
value is calculated by the following formula:  
The FAN2110 requires a 5 V supply rail to bias the IC  
and provide gate-drive energy. Connect a 2.2 µf  
X5R or X7R decoupling capacitor between VCC and  
AGND.  
VOUT  
VOUT (1-  
)
(4)  
Vin  
L   
IL f  
where f is the oscillator frequency.  
Since VCC is used to drive the internal MOSFET  
gates, supply current is frequency and voltage  
Setting the Ramp Resistor Value  
dependent. Approximate VCC current (ICC  
)
is  
RRAMP resistor plays a critical role in the design by  
providing charging current to the internal ramp  
capacitor and also serving as a means to provide  
input voltage feedforward.  
calculated by:  
VCC 5  
227  
ICC  
4.58 [(  
0.013)(f 128)]  
(1)  
(mA )  
where frequency (f) is expressed in KHz.  
RRAMP is calculated by the following formula:  
(VIN 1.8)VOUT  
(312.05IOUT )VIN f 106  
Setting the Output Voltage  
RRAMP(K)  
2  
(5)  
The output voltage of the regulator can be set from  
0.8V to 80% of VIN by an external resistor divider (R1  
and RBIAS in Figure 1). For output voltages >3.3V,  
output current rating may need to be de-rated  
depending on the ambient temperature, power  
dissipated in the package and the PCB layout. (Refer  
to Thermal Information table on page 4, Figure 22,  
and Figure 23.)  
where frequency (f) is expressed in KHz.  
For wide input operation, first calculate RRAMP for the  
minimum and maximum input voltage conditions and  
use larger of the two values calculated.  
In all applications, current through the RRAMP pin must  
be greater than 10 µA from the equation below for  
proper operation:  
The external resistor divider is calculated using:  
VIN 1.8  
RRAMP 2  
VOUT 0.8V  
R1  
0.8V  
10A  
(2)  
(6)  
650nA  
RBIAS  
Connect RBIAS between FB and AGND.  
If the calculated RRAMP values in Equation (5) result in  
a current less than 10 µA, use the RRAMP value that  
satisfies Equation (6). In applications with large Input  
ripple voltage, the RRAMP resistor should be  
adequately decoupled from the input voltage to  
minimize ripple on the ramp pin. For example, see  
Figure 11.  
If R1 is open (see Figure 1), the output voltage is not  
regulated and a latched fault occurs after the SS is  
complete (T1.0).  
If the parallel combination of R1 and RBIAS is 1K,  
the internal SS ramp is not released and the regulator  
does not start.  
Setting the Current Limit  
Setting the Clock Frequency  
Oscillator frequency is determined by an external  
resistor, RT, connected between the RT pin and AGND.  
Resistance is calculated by:  
The current limit system involves two comparators.  
The MAX ILIMIT comparator is used with a VILIM fixed-  
voltage reference and represents the maximum  
current limit allowable. This reference voltage is  
temperature compensated to reflect the RDSON  
variation of the low-side MOSFET. The ADJUST ILIMIT  
comparator is used where the current limit needs to  
be set lower than the VILIM fixed reference. The 10 µA  
current source does not track the RDSON changes over  
temperature, so change is added into the equations  
for calculating the ADJUST ILIMIT comparator  
reference voltage, as is shown below. Figure 33  
shows a simplified schematic of the over-current  
system.  
(106 / f ) 135  
(3)  
RT  
(K)  
65  
where RT is in Kand frequency (f) is in KHz.  
The regulator cannot start if RT is left open.  
Calculating the Inductor Value  
Typically the inductor value is chosen based on ripple  
current (IL), which is chosen between 10 to 35% of  
the maximum DC load. Regulator designs that require  
fast transient response use a higher ripple-current  
setting, while regulator designs that require higher  
efficiency keep ripple current on the low side and  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
14  
PW  
fairly high. This could lead to operation at high load  
currents, causing overheating of the regulator. For a  
given RILIM and RRAMP setting, the current limit point  
varies slightly in an inverse relationship with respect  
to input voltage (VIN).  
RAM  
COMP  
+
_
VERR  
PW  
MAX  
ILIMIT  
Loop Compensation  
+
_
VCC  
VILI  
The loop is compensated using a feedback network  
around the error amplifier. Figure 34 shows a  
complete type-3 compensation network. For type-2  
compensation, eliminate R3 and C3.  
10µA  
ADJUST  
ILIMIT  
ILIMTRIP  
+
_
ILIM  
RILIM  
Figure 33. Current-Limit System Schematic  
Since the ILIM voltage is set by a 10 µA current source  
into the RILIM resistor, the basic equation for setting  
the reference voltage is:  
VRILIM = 10µA*RILIM  
To calculate RILIM  
RILIM = VRILIM/ 10µA  
(7)  
:
Figure 34. Compensation Network  
(8)  
Since the FAN2110 employs summing current-mode  
architecture, type-2 compensation can be used for  
many applications. For applications that require wide  
loop bandwidth and/or use very low-ESR output  
capacitors, type-3 compensation may be required.  
The voltage VRILIM is made up of two components,  
VBOT (which relates to the current through the low-  
side MOSFET) and VRMPEAK (which relates to the  
peak current through the inductor). Combining those  
two voltage terms results in:  
RRAMP also provides feedforward compensation for  
changes in VIN. With a fixed RRAMP value, the  
modulator gain increases as VIN is reduced, which  
could make it difficult to compensate the loop. For  
low-input-voltage-range designs (3 V to 8 V), RRAMP  
and the compensation component values are  
different compared to designs with VIN between 8 V  
and 24 V.  
(9)  
RILIM = (VBOT + VRMPEAK)/ 10µA  
RILIM = {0.96 + (ILOAD * RDSON *KT*8)} +  
{D*(VIN 1.8)/(fSW*0.03*10^-  
3*RRAMP)}/10 µA  
(10)  
where:  
VBOT = 0.96 + (ILOAD * RDSON *KT*8);  
VRMPEAK = D*(VIN 1.8)/(fSW*0.03*10^-3*RRAMP);  
ILOAD = the desired maximum load current;  
Recommended PCB Layout  
Good PCB layout and careful attention to temperature  
rise is essential for reliable operation of the regulator.  
Four-layer PCB with two-ounce copper on the top and  
bottom side and thermal vias connecting the layers is  
recommended. Keep power traces wide and short to  
minimize losses and ringing. Do not connect AGND to  
PGND below the IC. Connect the AGND pin to PGND  
at the output OR to the PGND plane.  
RDSON  
= the nominal RDSON of the low-side  
MOSFET;  
KT = the normalized temperature coefficient for the  
low-side MOSFET (on datasheet graph);  
D = VOUT/VIN duty cycle;  
fSW = Clock frequency in kHz; and  
RRAMP = chosen ramp resistor value in k.  
VIN  
After 16 consecutive, pulse-by-pulse, current-limit  
cycles, the fault latch is set and the regulator shuts  
down. Cycling VCC or EN restores operation after a  
normal soft-start cycle (refer to the Auto-Restart  
section).  
SW  
GND  
GND  
The over-current protection fault latch is active during  
VOUT  
the soft-start cycle. Use 1% resistor for RILIM  
.
Figure 35. Recommended PCB Layout  
Always use an external resistor RILIM to set the  
current limit at the desired level. When RILIM is not  
connected, the IC’s internal default current limit is  
© 2008 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN2110 • Rev. 1.12  
15  
 
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