FAD8253MX-1 [ONSEMI]
1200V Half-Bridge Gate Driver, 2.5 A Source/3.4 A Sink, SOIC-8 package;
| 型号： | FAD8253MX-1 |
| 厂家： | 
ONSEMI |
| 描述： | 1200V Half-Bridge Gate Driver, 2.5 A Source/3.4 A Sink, SOIC-8 package 栅 |
| 文件： | 总19页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Half-Bridge Gate Driver
1200 V 2.5 A Source/3.4 A Sink
14
1
SOIC−14 NB
CASE 751A
FAD8253MX-1
Description
MARKING DIAGRAM
The FAD8253 is a monolithic half−bridge gate driver IC designed
for driving high voltage, high speed and high power IGBTs up to
+1200 V. The FAD8253 employs ON’s high−voltage process and
common−mode noise canceling technique to provide stable operation
of high−side driver under high dv/dt noise circumstances. The gate
driver includes UVLO circuits tailored to IGBT threshold for both
14
Pin 1 Bar
FAD
8253MX
AWLYWW
or
ON
Pin 1 Dot
high side and low side outputs to prevent malfunction when V and
DD
1
V
BS
are lower than the specified threshold voltage.
The FAD8253 offers a built−in low−side current detection circuitry
FAD8253MX
A
WL
Y
WW
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
with an additional provision for soft shutdown (for low side) during
overcurrent or short−circuit conditions. The driver can provide
adequate protection during short−circuits by turning off its outputs
while simultaneously generating a fault output for fault reporting
purposes. The driver also provides additional flexibility by providing
a shutdown pin to disable driver outputs externally.
PIN ASSIGNMENT
Features
VSS
LIN
1
2
3
4
5
6
7
14 VB
13 HO
12 VS
11 NC
10 NC
• Floating Channel for Bootstrap Operation to +1200 V
• Peak Output Current Capability of 2.5 A Source/3.4 A Sink
SD
• Allowable Negative V Transient Swing of up to −15 V at
S
V
BS
= 15 V
HIN
FO
• Built−in Common Mode dv/dt Noise Canceling Circuit
• Separate Power and Signal Ground for Enhanced dl/dt Immunity
• Matched Propagation Delay < 50 ns
• 3.3 V and 5 V Input Logic Compatible
• Built in Shoot−through Prevention Logic with 120 ns (Typ) Dead
Time
CSC
VDD
9
8
LO
COM
ORDERING INFORMATION
• Built−in UVLO Functions for both High and Low Side with
Thresholds Optimized for IGBTs
†
Device
Package
Shipping
FAD8253MX−1 SOIC−14 NB
(Pb−Free)
2,500 /
• Built−in Low Side Short−circuit Protection with Soft Shutdown
Tape & Reel
• In SOIC14NB with Non Connected Pins for High Voltage
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Creepage and Clearance Requirements
• Fault Reporting during Overcurrent or Short−circuit Condition
• External Shutdown Pin to Enable or Disable Driver Outputs
• AEC−Q100 Qualified and PPAP Capable
• Pb−Free Devices
Typical Applications
• High Voltage Auxiliary Motor Drive
• Generic Half−Bridge and Full−Bridge Driver
• On−Board Chargers & DC/DC Converters
• Traction Inverters
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
August, 2022 − Rev. 3
FAD8253/D
FAD8253MX−1
APPLICATION DIAGRAMS
VDC
VCC
VDD
VDD
VDD
or
VSS
HO
VB
VS
VSS
HO
VSS
HO
HIN
LIN
UH
UL
VB
VS
HIN
LIN
VH
VL
WH
WL
3-Phase
W
Motor
Controller
HIN
LIN
VB
VS
FO
SD
FO
SD
FO
SD
LO
LO
LO
CSC
CSC
CSC
COM
COM
COM
Rsense
Figure 1. 3−Phase Motor Drive Application
VDC
VCC
VDD
VDD
or
VSS
HO
VB
VS
VSS
HO
PHA_H
PHA_L
HIN
LIN
PHB_H
PHB_L
HIN
LIN
M
VB
VS
FAULT
FO
SD
FO
SD
SHUTDOWN
LO
LO
CSC
CSC
DC Motor
Controller
COM
COM
Figure 2. DC Motor Drive Application
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2
FAD8253MX−1
BLOCK DIAGRAM
14 VB
13 HO
UVLO
R
LIN
HIN
SD
2
4
3
SCHMITT
TRIGGER INPUT
R
S
NOISE
CANCELLER
Q
SHOOT−THROUGH
PREVENTION
12 VS
CONTROL LOGIC
7
9
VD D
LO
UVLO
V
SS /COM
DELAY
LEVEL SHIFTER
CSC
FO
6
5
Pulse
generator
+
_
RCSCIN
0.5V
8
COM
SOFT
SHUTDOWN
FAULT
LOGIC
VSS
1
Figure 3. Block Diagram
PIN DESCRIPTION
PIN FUNCTION DESCRIPTION
Pin No.
Name
VSS
LIN
Description
1
Logic Ground
2
3
Logic Input for Low−Side Gate Driver Output
Shutdown Control Input with Active Low
Logic Input for High−Side Gate Driver Output
Fault Output with Open Drain (Low True)
Short−Circuit Current Detection Input
Low−Side and Logic Power Supply Voltage
Low−side Driver Return
SD
4
HIN
FO
5
6
CSC
VDD
COM
LO
7
8
9
Low−Side Driver Output
12
13
14
10, 11
VS
High−Side Floating Supply Return
High−Side Driver Output
HO
VB
High−Side Floating Supply
NC
No Connect
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3
FAD8253MX−1
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T = 25°C, unless otherwise specified.)
A
Symbol
Rating
Value
Unit
V
V
S
V
B
High−side Offset Voltage V
(V − 25) to (V + 0.3)
S
B
B
High−side Floating Supply Voltage V
High−side Floating Output Voltage
−0.3 to 1225
V
B
V
(V – 0.3) to (V + 0.3)
V
HO
DD
S
B
V
Low−side and Logic−fixed Supply Voltage
Logic Input Voltage (HIN, LIN, SD)
Current Sense Input Voltage
−0.3 to 25
V
V
IN
−0.3 to (V + 0.3)
V
DD
V
CSC
−0.3 to (V + 0.3)
V
DD
dV /dt
Allowable Offset Voltage Slew Rate
Power Dissipation (SO14NB) (Note 1)
Thermal Resistance, Junction−to−Ambient (SO14NB)
Junction Temperature
50
0.8
V/ns
W
S
P
D
θ
JA
156
°C/W
°C
°C
V
T
+150
J(max)
TSTG
Storage Temperature
−55 to +150
2500
ESDHBM
ESDCDM
ESD, Human Body Model (Note 3)
ESD, Charged Device Model (Note 3)
750
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Do not exceed PD under any circumstances.
2. Mounted on 76.2 × 114.3 × 1.6 mm PCB (FR−4 glass epoxy material). Refer to the following standards:
− JESD51−2: Integral circuits thermal test method environmental conditions – natural convection
− JESD51−3: Low effective thermal conductivity test board for leaded surface mount packages
3. This device series incorporates ESD protection and is tested by the following methods:
− ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001−2012
− ESD Charged Device Model tested per JESD22−C101
RECOMMENDED OPERATING RANGES (Parameters are referenced to V
)
SS
Symbol
Rating
Min
Max
18.0
1200
22
Unit
V
V
DD
Supply Voltage Range
High−Side V Floating Supply Offset Voltage (Note 4)
4.5
V
S
5 − V
V
S
BS
V
High−side V Bootstrap Voltage
V
V
BS
HO
DD
BS
BSUV+
V
V
High−Side Output Voltage
Low−Side and Logic Supply Voltage
Low−Side Output Voltage
Logic Input Voltage (IN, SD)
Power Ground
V
S
V
B
V
V
22
V
DDUV+
V
LO
COM
V
V
DD
DD
DD
V
IN
V
SS
V
V
V
COM
V
− 22
V
DD
T
A
Ambient Temperature (Note 5)
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Recommended based on min 5 V on V , for proper operation of the level shifter circuit and ensure proper propagation of the signal from the
B
input to the output.
5. Power and thermal impedance should be determined with care so that T does not exceed 150°C.
j
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4
FAD8253MX−1
ELECTRICAL CHARACTERISTICS
(V
BIAS
(V
V
) = 15 V, T = −40°C to 125°C unless otherwise specified. The V and I parameters are referenced to V . The V
DD, BS A IN IN SS
O
and I parameters are referenced to V and COM and are applicable to the respective outputs HO and LO.)
O
S
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
LOW SIDE POWER SUPPLY SECTION
Quiescent V Supply Current
I
V = 0 V or 5 V
LIN
50
280
660
400
800
mA
mA
QDD
DD
I
Operating V Supply Current
C = 1 nF, f
= 20 kHz,
400
PDD
DD
L
LIN
rms value
V
V
V
Supply Under−Voltage Positive−going
V
= Rising
11
10.5
−
12
11.4
0.6
12.9
12.4
−
V
V
V
DDUV+
DDUV−
DDHYS
DD
DD
DD
Threshold
V
Supply Under−voltage Negative going
V
= Falling
DD
Threshold
V Supply Under−voltage Lockout Hysteresis
DD
V
BOOSTRAPPED POWER SUPPLY SECTION
Quiescent V Supply Current
I
V
= 0 V or 5 V
−
−
25
45
mA
mA
QBS
BS
HIN
I
Operating V Supply Current
C = 1 nF, f
rms value
= 20 kHz,
430
550
PBS
BS
L
HIN
I
Offset Supply Leakage Current
V
V
= V = 1200 V
−
−
120
mA
LK
B
S
V
V
V
Supply Under−Voltage Positive−going
= Rising
10.6
11.7
12.5
V
BSUV+
BSUV−
BSHYS
BS
BS
Threshold
V
Supply Under−voltage Negative Going
V
BS
= Falling
10.1
11.1
0.6
11.9
V
V
BS
Threshold
V
V
BS
Supply Under−voltage Lockout Hysteresis
−
−
GATE DRIVER OUTPUT SECTION
High−level Output Voltage, V
V
OH
−V
O
I
I
= 0 mA (No Load)
= 0 mA (No Load)
−
−
−
−
50
50
−
mV
mV
mA
BIAS
O
V
OL
O+
Low−level Output Voltage, V
O
O
I
Output HIGH Short−circuit Pulsed Current
V
= 0 V, V = 5 V with
1200
2700
O
IN
PW < 10 ms
I
Output LOW Short−circuit Pulsed Current
V
= 15 V, V = 0 V with
1200
−10.0
−15.0
−7.0
4200
−
−
−
−
mA
V
O−
O
IN
PW < 10 ms
V
Allowable Negative V Pin Voltage, with Signal
V
BS
V
BS
V
DD
= 15 V
−
−
−
S
S
Propagation Capability from HIN to HO
V
Allowable Transient Negative V Pin Voltage,
= 15 V
V
S
S
(Note 6)
No Signal Propagation Capability from HIN to HO
COM−V
Allowable COM−V Power/Signal Grounds Offset
= 15 V, V = 0 V
V
SS
SS
SS
LOGIC INPUT SECTION (HIN, LIN, SD)
V
Logic “1” Input Voltage Threshold
Logic “0” Input Voltage Threshold
Logic Input Hysteresis Voltage
−
1.2
−
−
−
2.5
−
V
V
IH
V
IL
V
0.5
23
−
−
V
INHYS
I
Logic “1” Input Bias Current (HIN, LIN)
Logic “0” Input Bias Current (HIN, LIN)
Logic “1” Input Bias Current (SD)
Logic “0” Input Bias Current (SD)
V
V
V
V
= 5 V
= 0 V
= 5 V
= 0 V
−
−
mA
mA
mA
mA
IN+
IN
I
−
2.0
−
IN−
IN
I
−
15.7
−
SD+
SD
SD
I
−
2.0
SD−
SHORT−CIRCUIT PROTECTION
V
Short−circuit detector reference voltage
Input Pull Down Short Circuit Resistance
Short−Circuit Input Current
0.45
−
0.50
210
23.5
110
0.6
−
V
CSCREF
R
kW
mA
mA
CSCIN
CSCIN
I
V
V
= 5 V
15
70
37.5
140
CSCIN
I
Soft Turn−off Source Current
= 15 V, L = 7.5 V
DD O
SOFT
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5
FAD8253MX−1
ELECTRICAL CHARACTERISTICS (continued)
(V (V ) = 15 V, T = −40°C to 125°C unless otherwise specified. The V and I parameters are referenced to V . The V
V
BIAS
DD, BS
A
IN
IN
SS
O
and I parameters are referenced to V and COM and are applicable to the respective outputs HO and LO.)
O
S
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
FAULT DETECTION SECTION
V
Fault Output High Level Voltage
Fault Output Low Level Voltage
V
V
= 0 V, R = 4.7 kW
PULL−UP
4.7
−
−
−
V
V
FOH
CSC
V
= 1 V, I = 2 mA
−
0.8
FOL
CSC
FO
DYNAMIC OUTPUT SECTION
(V
(V , V ) = 15.0 V, T = −40°C to 125°C, V = V , C
= 1000 pF unless otherwise specified.)
BIAS
DD
BS
A
S
SS
LOAD
t
t
Turn−on Propagation Delay (Note 7)
Turn−off Propagation Delay
SD to Low−side Propagation Delay
SD to How−side Propagation Delay
Turn−on Rise Time
V
V
= 0 V
65
65
25
65
−
100
90
145
145
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ms
ns
on
off
S
= 0 V or 1200 V
S
t
45
SDOFF_LO
SDOFF_HO
t
95
145
25
t
r
13
t
f
Turn−off Fall Time
−
15
26
Mt
Delay Matching HO and LO Turn−On
Delay Matching HO and LO Turn−Off
Dead−time (Note 8)
−
−
25
ON
Mt
−
−
25
OFF
DT
70
−
120
10
200
−
t
Under−voltage Filtering Time (Note 6)
CSC Pin Filtering Time (Note 6)
Time from CSC Triggering to FO
Fault Output Pulse Width
UVFLT
t
−
300
530
65
−
CSCFLT
t
−
1250
140
1350
CSCFO
t
24
−
FO
t
Time from CSC Triggering to Low−side and
High−side Gate Output
From V
turn−off
= 1 V to starting gate
600
CSCLO
CSC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Parameter guaranteed by design.
7. The turn−on propagation delay does not includes the dead time.
8. The dead time includes the turn on propagation time.
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6
FAD8253MX−1
TYPICAL CHARACTERISTICS
13.0
12.5
Min
Typ
Max
12.0
12.5
12.0
11.5
11.5
11.0
10.5
10.0
Min
Typ
Max
11.0
−50
−25
0
25
50
75
100
125
125
125
−50
−25
0
25
50
75
100
125
125
125
Temperature (5C)
Temperature (5C)
Figure 4. VDD UVLO (+) vs. Temperature
Figure 5. VDD UVLO (−) vs. Temperature
12.5
12.0
11.5
11.0
10.5
12.0
11.5
11.0
10.5
10.0
Min
Typ
Max
Min
Typ
Max
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
Temperature (5C)
Temperature (5C)
Figure 6. VBS UVLO (+) vs. Temperature
Figure 7. VBS UVLO (−) vs. Temperature
400
360
45
40
35
30
25
320
280
240
200
160
20
15
10
Typ
Max
Typ
Max
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
Temperature (5C)
Temperature (5C)
Figure 8. VDD Quiescent Current vs. Temperature
Figure 9. VBS Quiescent Current vs. Temperature
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7
FAD8253MX−1
TYPICAL CHARACTERISTICS (Continued)
900
850
800
750
700
650
600
550
600
Typ
Max
575
550
525
500
475
450
425
Typ
Max
500
400
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
125
125
Temperature (5C)
Temperature (5C)
Figure 10. VDD Operating Current vs.
Temperature
Figure 11. VBS Operating Current vs.
Temperature
40
35
30
25
20
35
33
31
29
27
25
23
21
19
17
15
Typ
Max
Typ
Max
15
10
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
Temperature (5C)
Temperature (5C)
Figure 12. Logic High Input Bias Current vs.
Temperature
Figure 13. ICSCIN vs. Temperature
140
130
120
110
25
20
15
10
5
100
90
Typ
Max
Typ
Max
80
−50
0
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
Temperature (5C)
Temperature (5C)
Figure 14. ISOFT vs. Temperature
Figure 15. Turn−on Rising Time vs. Temperature
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8
FAD8253MX−1
TYPICAL CHARACTERISTICS (Continued)
25
150
140
130
120
110
20
15
10
5
100
90
80
70
Typ
Max
Typ
Max
0
−50
60
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 16. Turn−off Falling Time vs. Temperature
Figure 17. Turn−on Delay Time vs. Temperature
150
2.5
2.4
2.3
2.2
2.1
2.0
1.9
140
130
120
110
100
90
80
70
60
Typ
Max
Typ
Max
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 18. Turn−off Delay time vs. Temperature
Figure 19. Logic High Input Voltage Threshold
vs. Temperature
1.9
0.57
Min
Typ
Max
1.8
1.7
1.6
0.55
0.53
0.51
0.49
0.47
0.45
1.5
1.4
1.3
Typ
Max
1.2
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 20. Logic Low Input Voltage Threshold vs.
Temperature
Figure 21. VCSCREF vs. Temperature
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9
FAD8253MX−1
TYPICAL CHARACTERISTICS (Continued)
24
22
20
330
310
290
270
250
Min
Typ
Max
18
230
210
190
16
14
12
Typ
Max
170
10
−50
150
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 22. SD Logic High Input Bias Current vs.
Temperature
Figure 23. Input Pull Down Short Circuit
Resistance vs. Temperature
5.3
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
5.2
5.1
5.0
4.9
4.8
Min
Typ
Max
Min
Typ
Max
4.7
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 24. Fault Output High Level Voltage vs.
Temperature
Figure 25. Fault Output Low Level Voltage vs.
Temperature
−10
5
4
3
2
1
Typ
Max
−11
−12
−13
−14
Min
Typ
Max
−15
−50
0
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 26. Allowable Negative VS Voltage vs.
Temperature
Figure 27. High−level Output Voltage vs.
Temperature
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10
FAD8253MX−1
TYPICAL CHARACTERISTICS (Continued)
5
4
3
2
1
200
Typ
Max
180
160
140
120
100
80
Typ
Max
0
−50
60
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 28. Low−level Output Voltage vs.
Figure 29. Dead Time vs. Temperature
Temperature
25
20
15
10
5
25
20
15
10
5
Typ
Max
Typ
Max
0
−50
0
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 30. Delay Matching HO and LO Turn−on
Figure 31. Delay Matching HO and LO Turn−off
vs. Temperature
vs. Temperature
70
145
135
125
115
105
65
60
55
50
45
40
35
30
95
85
75
Typ
Max
Typ
Max
25
20
65
−50
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 32. SD to Low−side Propagation Delay vs.
Figure 33. SD to High−side Propagation Delay
Temperature
vs. Temperature
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11
FAD8253MX−1
TYPICAL CHARACTERISTICS (Continued)
145
125
1300
1200
1100
1000
900
Typ
Max
105
85
65
45
24
800
700
Typ
Max
600
500
−50
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 34. Fault Output Minimum Pulse Width vs.
Temperature
Figure 35. Time from CSC Triggering to
Low−side Gate Output vs. Temperature
1300
1000
900
Typ
Max
1200
1100
1000
900
Typ
Max
800
700
600
500
400
800
700
600
500
400
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 36. Time from CSC Triggering to
High−side Gate Output vs. Temperature
Figure 37. Time from CSC Triggering to FO vs.
Temperature
8
7
6
5
4
3
9
8
7
6
5
4
3
Typ
Max
Typ
Max
2
1
0
2
1
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (5C)
Temperature (5C)
Figure 38. Output High Short−circuit Pulsed
Figure 39. Output Low Short−circuit Pulsed
Current vs. Temperature
Current vs. Temperature
www.onsemi.com
12
FAD8253MX−1
SWITCHING TIME DEFINITIONS
50%
SD
HIN
LIN
50%
ton
50%
tSDOFF
tr
toff
tf
90%
90%
90%
HO
LO
10%
10%
Figure 40. Switching Timing Waveforms Definition (Propagation Delay, Rise and Fall Time)
IN (LO)
50%
50%
IN (HO)
MTOFF
90%
HO
LO
HO
10%
LO
MTON
Figure 41. Switching Timing Waveforms Definition (Matching Delay)
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13
FAD8253MX−1
LIN
SD
Output activated
at next rising edge
of input signal
V
DD
UVLO−
0.5 V
V
CSC
t
CSCFO
t
FO
FO
LO
t
SDOFF
t
UVFLT
t
CSCLO
Soft−shutdown
Operation
Under−Voltage
Detection Point
Shutdown
Enable Point Disable Point
Shutdown
Short−circuit
Detection Point
Figure 42. Switching Timing Waveforms Definition – Low Side
HIN
SD
Output activated
at next rising edge
of input signal
V
BS
UVLO−
0.5 V
V
CSC
t
CSCFO
t
FO
FO
HO
t
SDOFF
t
UVFLT
t
CSCLO
Under−Voltage
Detection Point
Shutdown
Enable Point Disable Point
Shutdown
Short−circuit
Detection Point
Figure 43. Switching Timing Waveforms Definition – High Side
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14
FAD8253MX−1
APPLICATIONS INFORMATION
Protection Function
designed to prevent the outputs of the high−side and low−
side stages from turning on at the same time.
Shutdown (SD) Function
As shown in Figure 45, if the low−side input (LIN) signal
is provided to the driver while the high−side input (HIN)
signal is already present, the high side output (HO) is turned
off immediately while the low−side output (LO) is kept
turned off. In addition, both driver outputs are kept turned
off for as long as both HIN and LIN are present. This
prevents the shoot−through of the high−side and low−side
devices in an application. Similarly, as shown in Figure 46,
if HIN signal is provided to the driver while LIN signal is
already present, LO is turned off immediately while HO is
kept turned off.
The shutdown (SD) pin of FAD8253 is active low,
meaning that the driver outputs are enabled when SD pin is
pulled up and vice versa. If SD pin is pulled low for a time
equivalent to propagation delay, the outputs of both high and
low side driver stages are turned off. The outputs are
reactivated on the next rising edge of the input signal, once
the SD pin is pulled up.
Under−Voltage Lockout (UVLO)
The FAD8253 has an internal under−voltage lockout
(UVLO) protection circuitry for both high−side and
low−side driver stages, with a threshold optimized for
IGBTs. The UVLO independently monitors the supply
voltage (V ) and bootstrap capacitor voltage (V ) to
DD
BS
HIN
LIN
prevent malfunction if V and V drop lower than the
DD
BS
specified threshold voltage in the manner explained below:
• If V drops below its negative−going threshold voltage,
BS
the output of the high side driver stage is pulled down (or
turned off).
• If V voltage drops below its negative−going threshold
DD
voltage, the outputs of both the low side and high side
driver stages are pulled down (or turned off).
Shoot−through
After DT
HO
LO
Prevention
In either of the above cases, the outputs will resume their
normal operation once the V /V
voltages have risen
BS DD
back to the necessary positive going threshold, as shown in
Figure 44. Moreover, the UVLO hysteresis and the UV
filtering time prevent chattering during power supply
After DT
transitions. If the supply voltage (V or V ) maintains an
DD
BS
under−voltage condition for a duration longer than the
under−voltage filtering time, the high and low side driver
outputs are turned off. Note that an UVLO event has no
impact to the Fault Output flag.
Figure 45. Example Waveforms for
Shoot−through Prevention
LIN
LIN
Shoot−through
HIN
Prevention
UVLO+
UVLO−
V
DD
LO
t
UVFLT
LO
After DT
HO
Figure 44. Waveforms for Under−Voltage Lockout
Shoot−Through Prevention Function
The FAD8253 has a shoot−through prevention circuitry
that monitors both the high−side and low−side inputs. It is
Figure 46. Example waveforms for
Shoot−through Prevention
www.onsemi.com
15
FAD8253MX−1
Please note that the driver resumes normal operation with
a voltage divider that could lower the voltage at the CSC pin
(at point B in Figure 47). To minimize the voltage
a built−in dead time of 120 ns (typ.) between HO and LO,
only when LIN and HIN signals are not provided at the same
time.
difference, a value of 1 kW is recommended for R
.
CSCEXT
As a result, the voltage at point B (or CSC pin) will be
R
/ (R + R ) = 200 kW / (200 kW +
CSCEXT
CSCEXT
CSCIN
Over−Current/Short−Circuit Protection Function
The FAD8253 has a low side over−current detection
circuitry that monitors the voltage across the low side
1 kW), which is only 0.5% lower than at point A.
An over−current condition must last for a minimum
duration of t
(typ. 300 ns) to trigger the short− circuit
CSCFLT
current sensing resistor (R ) through the short−circuit
CSR
protection. This duration has been defined to provide
adequate noise filtering against high frequency noises
during IGBT switching. If this time is not sufficient, an
additional capacitor can be placed at the input of the CSC pin
to further extend the filtering time.
current detection input (CSC) pin.
The input stage of the over current circuitry is depicted in
Figure 47. The principle of overcurrent/short−circuit
detection feature is to monitor the voltage at point A (which
appears due to the phase current flowing into R
). If the
CSR
Upon detection of a short circuit through the CSC pin:
sensed voltage exceeds the short−circuit detector reference
voltage V (typ. 0.5 V), this indicates an over−current
• the high side output turns off immediately;
CSCREF
• the low side driver output initiates a soft shutdown to turn
off the low side IGBT slowly to prevent it from entering
the avalanche mode;
condition and the driver outputs are turned off.
For example, if R = 1 mW, the driver will activate the
short circuit protection for a phase current exceeding 500 A
CSC
(1 mW × 500 A = 0.5 V ≥ V
).
• the Fault Output (FO) pin generates a fault signal for
CSCREF
a duration of t (typ. 60 ms).
FO
Please note that once the FO is triggered, the driver
outputs can be reactivated on the next rising edge of input
FAD8253
+
I
signal only after the duration of t has passed.
PHASE
FO
CSC
B
A
Layout Considerations
For optimum performance, considerations must be taken
during printed circuit board (PCB) layout.
R
= 200 kW
R
CSCIN
_
CSCEXT
R
CSR
0.5 V
Power Supply Bypass Capacitors
V
CSCref
The implementation of bypass capacitors is essential to
optimal operation of gate drivers like FAD8253 and so,
special attention is required.
Figure 47. Input Circuit of the
Overcurrent/Short−circuit Protection Block
The local bypass capacitor between V and V needs
DD
SS
to provide pulsed currents for the low side driver output. At
the same time, if a high−side bootstrap circuit is employed,
it has to rapidly charge the bootstrap capacitor as well.
A typical criterion for choosing the value of bypass
capacitor is to keep the ripple voltage on the supply pin to
≤5%. Typically, two capacitors in parallel are
recommended. Often, a capacitor of smaller value is placed
LIN
0.5 V
V
CSC
very close to the V pin in parallel with another capacitor
DD
t
CSCFO
of higher value to reduce impedance. For sizing of the
bootstrap capacitor please refer to application note
AN−6076.
t
FO
FO
Soft−shutdown
Operation
t
Gate−Drive Loop
CSCLO
Current loops behave like antennae, able to receive and
transmit noise. To reduce the noise coupling/emission and
improve the power switch turn−on and off performance,
gate−drive loops must be reduced as much as possible.
LO
Short−circuit Detection Point
Figure 48. Waveforms for Short Circuit Protection
Ground Plane
To minimize noise coupling, the ground plane should not
be placed under or near the high voltage floating side.
It is recommended to place a series resistance R
to
CSCEXT
limit the input current that may flow into the driver during
transient conditions. Note that R and R form
CSCEXT
CSCIN
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16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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