ESD1213A-04S7 [ONSEMI]
DIODE TVS DIODE, Transient Suppressor;
| 型号： | ESD1213A-04S7 |
| 厂家： | 
ONSEMI |
| 描述： | DIODE TVS DIODE, Transient Suppressor 二极管 电视 |
| 文件： | 总6页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD1213A-04S7
4-Channel
Low Capacitance
ESD Protection Array
Product Description
http://onsemi.com
ESD1213A−04S7 has been designed to provide ESD protection for
electronic components or subsystems requiring minimal capacitive
loading. This device is ideal for protecting systems with high data and
clock rates or for circuits requiring low capacitive loading. Each ESD
channel consists of a pair of diodes in series which steer the positive or
negative ESD current pulse to either the positive (V ) or negative (V )
1
SC−88/363
STYLE 1
CASE 419B
P
N
supply rail. A Zener diode is embedded between V and V , offering
two advantages. First, it protects the V rail against ESD strikes, and
P
N
CC
second, it eliminates the need for a bypass capacitor that would
otherwise be needed for absorbing positive ESD strikes to ground.
This device will protect against ESD pulses up to 8 kV per the
IEC 61000−4−2standard.
This device is particularly well-suited for protecting systems using
®
high-speed ports such as USB 2.0, IEEE1394 (Firewire , iLinkt),
Serial ATA, DVI, HDMI and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
Features
MARKING DIAGRAM
• Four Channels of ESD Protection
• Provides ESD Protection to IEC61000−4−2 Level 4
XXXMG
♦
8 kV Contact Discharge
G
• Minimal Capacitance Change with Temperature and Voltage
• Zener Diode Protects Supply Rail and Eliminates the Need for
External By-pass Capacitors
• Each I/O Pin Can Withstand Over 1000 ESD Strikes*
• This Device is Pb-Free and is RoHS Compliant**
1
XXX
= Specific Device Code
= Date Code
M
G
= Pb−Free Package
(Note: Microdot may be in either location)
Applications
• USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals
ORDERING INFORMATION
®
• IEEE1394 Firewire Ports at 400 Mbps/800 Mbps
†
Device
Package
Shipping
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
ESD1213A−04S7
SC−88
3,000 /
(Pb−Free)
Tape & Reel
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• PCI Express Ports
• General Purpose High−Speed Data Line ESD Protection
**Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to 8 kV contact discharge for 1000 pulses. Discharges
are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production
test to verify that all of the tested parameters are within spec after the 1000 strikes.
**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
March, 2012 − Rev. 0
ESD1213A−04S7/D
ESD1213A−04S7
PACKAGE/PINOUT DIAGRAMS
Table 1. PIN DESCRIPTIONS
Pin
1
Name
Type
I/O
Description
ESD Channel
Top View
CH1
CH1
1
2
3
6
5
4
CH4
2
V
N
GND
I/O
Negative Voltage Supply Rail
ESD Channel
V
N
V
P
3
CH2
CH3
4
I/O
ESD Channel
CH2
CH3
5
V
PWR
I/O
Positive Voltage Supply Rail
ESD Channel
6−Lead SC−88
P
6
CH4
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Units
ESD per IEC 61000−4−2 (Air)
ESD per IEC 61000−4−2 (Contact)
V
ESD
15
8
kV
Operating Temperature Range
Storage Temperature Range
T
–55 to +125
–55 to +150
°C
°C
J
T
STG
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. ELECTRICAL OPERATING CHARACTERISTICS (T = 25°C)
Symbol
Parameter
Reverse Stand−Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Forward Voltage
Conditions
Min
Typ
Max
5
Units
V
V
RWM
Pin 5 to GND
V
BR
I = 1 mA, Any I/O to GND
6
8
9.5
3
V
t
I
R
V
= 5 V, T = 25°C, Any I/O to GND
mA
V
RWM
V
F
I = 100 mA, Any I/O pin to pin 5, GND to any I/O
1.6
15
3
F
V
C
Clamping Voltage
V = 80 V, R = 8 Ohms, tp = 2/10 ms, Any I/O pin to GND
V
C
Junction Capacitance
V
R
= 0 V, f = 1 MHz, Any I/O pin to GND
1.9
pF
J
V
R
= 0 V, f = 1 MHz, Between I/O pins
0.80
1
NOTE: I/O pins are pin 1, 3, 4, and 6
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2
ESD1213A−04S7
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of CIN vs. VIN
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 ꢀF Chip Capacitor between VP and VN, 255C)
Figure 2. Typical Variation of CIN vs. Temp
(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 ꢀ F Chip Capacitor between VP and VN)
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3
ESD1213A−04S7
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V)
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V)
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4
ESD1213A−04S7
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,
which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power
supply is represented by L and L . The voltage V on the line being protected is:
1
2
CL
V
CL
= Fwd Voltage Drop of D + V
+ L x d(I
) / dt + L x d(I
) / dt
1
SUPPLY
1
ESD
2
ESD
where I
is the ESD current pulse, and V
is the positive supply voltage.
ESD
SUPPLY
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I
)/dt can be
ESD
−9
approximated by DI
/Dt, or 30/(1x10 ). So just 10 nH of series inductance (L and L combined) will lead to a 300 V
ESD
1
2
increment in V
!
CL
Similarly for negative ESD pulses, parasitic series inductance from the V pin to the ground rail will lead to drastically
N
increased negative voltage on the line being protected.
The CM1213A has an integrated Zener diode between V and V . This greatly reduces the effect of supply rail inductance
P
N
L on V by clamping V at the breakdown voltage of the Zener diode. However, for the lowest possible V , especially when
2
CL
P
CL
V is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip
P
capacitor be connected between V and the ground plane.
P
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V pin of the Protection
P
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section.
L
2
V
CC
POSITIVE SUPPLY RAIL
V
P
PATH OF ESD CURRENT PULSE I
ESO
LINE BEING
PROTECTED
SYSTEM OR
CIRCUITRY
BEING
L
1
D
D
1
0.22 mF
CHANNEL
INPUT
ONE
PROTECTED
CHANNEL
OF
2
V
CL
25 A
CM1213
0 A
GROUND RAIL
V
N
CHASSIS GROUND
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
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5
ESD1213A−04S7
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE W
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
e
2. CONTROLLING DIMENSION: INCH.
3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.
MILLIMETERS
DIM MIN NOM MAX
0.80
INCHES
NOM MAX
1.10 0.031 0.037 0.043
0.10 0.000 0.002 0.004
0.008 REF
6
1
5
2
4
3
MIN
A
0.95
0.05
H
−E−
E
A1 0.00
A3
0.20 REF
0.21
0.14
2.00
1.25
0.65 BSC
0.20
2.10
b
C
D
E
e
0.10
0.10
1.80
1.15
0.30 0.004 0.008 0.012
0.25 0.004 0.005 0.010
2.20 0.070 0.078 0.086
1.35 0.045 0.049 0.053
0.026 BSC
0.30 0.004 0.008 0.012
2.20 0.078 0.082 0.086
b 6 PL
L
0.10
2.00
M
M
E
0.2 (0.008)
H
E
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
A3
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
C
A
6. COLLECTOR 2
A1
L
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
FireWire is a registered trademark of Apple Computer, Inc.
iLink is a trademark of S. J. Electro Systems, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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ESD1213A−04S7/D
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