EMI4182MTTAG [ONSEMI]
Common Mode Filter with ESD Protection; 共模滤波器与ESD保护型号: | EMI4182MTTAG |
厂家: | ONSEMI |
描述: | Common Mode Filter with ESD Protection |
文件: | 总10页 (文件大小:809K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EMI4182
Common Mode Filter with
ESD Protection
Functional Description
The EMI4182 is an integrated common mode filter providing both
ESD protection and EMI filtering for high speed digital serial
interfaces such as HDMI or MIPI D-PHY.
The EMI4182 provides protection for two differential data line pairs
in a small RoHS-compliant WDFN10 package.
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MARKING
DIAGRAMS
Features
42MG
• Highly Integrated Common Mode Filter (CMF) with ESD Protection
provides protection and EMI reduction for systems using High Speed
Serial Data Lines with cost and space savings over discrete solutions
G
WDFN10
CASE 511BM
• Large Differential Mode Bandwidth with Cutoff Frequency > 2 GHz
42 = Specific Device Code
• High Common Mode Stop Band Attenuation: >25 dB at 700 MHz,
M
G
= Date Code
= Pb−Free Package
>30 dB at 800 MHz
• Provides ESD Protection to IEC61000-4-2 Level 4, 15 kV Contact
Discharge
(Note: Microdot may be in either location)
• Low Channel Input Capacitance Provides Superior Impedance
Matching Performance
PIN CONNECTIONS
• Low Profile Package with Small Footprint in WDFN10 2 x 2.5 mm
Pb−Free Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
2
In_1+
In_1−
GND
10
9
Out_1+
Out_1−
GND
3
4
8
7
Applications
Out_2+
Out_2−
• HDMI/DVI Display in Mobile Phones
In_2+
• MIPI D-PHY (CSI-2, DSI, etc) in Mobile Phones and Digital Still
5
6
In_2−
Cameras
1
10
2
4
9
7
ORDERING INFORMATION
External
(Connector)
Internal
(ASIC)
†
Device
Package
Shipping
5
6
EMI4182MTTAG
WDFN10
3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
3, 8
Figure 1. EMI4182 Electrical Schematic
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 0
EMI4182/D
EMI4182
PIN FUNCTION DESCRIPTION
Pin Name
In_1+
Pin No.
Type
I/O
Description
1
2
CMF Channel 1+ to Connector
CMF Channel 1− to Connector
CMF Channel 1+ to ASIC
CMF Channel 1− to ASIC
CMF Channel 2+ to Connector
CMF Channel 2− to Connector
CMF Channel 2+ to ASIC
CMF Channel 2− to ASIC
Ground
In_1−
I/O
Out_1+
Out_1−
In_2+
10
9
I/O
I/O
4
I/O
In_2−
5
I/O
Out_2+
Out_2−
7
I/O
6
I/O
V
N
3, 8
GND
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Parameter
Operating Temperature Range
Symbol
Value
−40 to +85
−65 to +150
15
Unit
°C
T
OP
Storage Temperature Range
T
STG
°C
ESD Discharge IEC61000−4−2 Contact Discharge
V
PP
kV
Maximum Lead Temperature for Soldering Purposes
(1/8” from Case for 10 seconds)
T
L
260
°C
DC Current per Line
I
100
mA
LINE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Channel Leakage Current
Channel Negative Voltage
Test Conditions
T = 25°C, V = 5 V, GND = 0 V
Min
Typ
Max
1.0
1.5
1.3
Unit
mA
V
I
LEAK
A
IN
V
F
T = 25°C, I = 10 mA
0.1
A
F
C
Channel Input Capacitance to Ground
(Pins 1, 2, 4, 5 to Pins 3, 8)
T = 25°C, At 1 MHz, GND = 0 V,
0.8
8.0
pF
IN
A
IN
V
= 1.65 V
R
Channel Resistance
(Pins 1−10, 2−9, 4−7 and 5−6)
W
CH
f
Differential Mode Cut−off Frequency
50 W Source and Load Termination
2.0
30
GHz
dB
3dB
F
atten
Common Mode Stop Band Attenuation
@ 800 MHz
V
ESD
ESD Protection − Peak Discharge
Voltage at any channel input, in system:
Contact discharge per
T = 25°C
15
kV
A
(Notes 1 and 2)
Pins 1, 2, 4, 5
IEC61000−4−2 standard
V
CL
TLP Clamping Voltage
(See Figure 12)
Forward I = 8 A
12
18
V
V
V
V
PP
Forward I = 16 A
PP
Forward I = −8 A
−6
PP
Forward I = −16 A
−12
PP
R
Dynamic Resistance
Positive Transients
Negative Transients
T = 25°C, I = 1 A, t = 8/20 ms
A PP P
Any I/O pin to Ground;
Notes 1 and 3
DYN
1.36
0.6
V
Reverse Working Voltage
Breakdown Voltage
(Note 3)
5.0
9.0
V
V
RWM
V
I = 1 mA; (Note 4)
T
5.6
BR
1. Standard IEC61000−4−2 with C
= 150 pF, R
= 330, GND grounded.
Discharge
Discharge
2. These measurements performed with no external capacitor.
3. TVS devices are normally selected according to the working peak reverse voltage (V
or continuous peak operating voltage level.
), which should be equal to or greater than the DC
RWM
4. V is measured at pulse test current I .
BR
T
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2
EMI4182
TYPICAL CHARACTERISTICS
0
−5
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−15
−20
−25
−30
−35
−40
1E5
1E6
1E7
1E8
1E9
6E9
1E5
1E6
1E7
1E8
1E9
6E9
Frequency, Hz
Frequency, Hz
Figure 2. Differential Mode Attenuation vs.
Figure 3. Common Mode Attenuation vs.
Frequency (Zdiff = 100 W)
Frequency (Zcomm = 50 W)
0
−5
−10
−15
−20
−25
−30
−35
−40
1E5
1E6
1E7
1E8
1E9
6E9
Frequency, Hz
Figure 4. Differential Return Loss vs. Frequency
Figure 5. Differential Inter−Lane Cross−Coupling
(Zdiff=100 W)
Figure 6. Common Mode Inter−Lane Cross−Coupling
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3
EMI4182
MIPI DSI (D−PHY)
MIPI DSI (D−PHY)
Client
Host
EMI4182
Evaluation
Board
Figure 7. MIPI D−PHY LP Mode Test Setup
Figure 8. EMI4182 MIPI D−PHY LP Mode Measured Results
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4
EMI4182
Figure 9. EMI4182 Eye Diagram Test Setup
Figure 10. EMI4182 Measured Eye Diagram @ 3.4Gbps (EVB through on left, EVB with EMI4182 on right)
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5
EMI4182
Transmission Line Pulse (TLP) Measurements
Transmission Line Pulse (TLP) provides current versus voltage (I-V) curves in which each data point is obtained from a
100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in
Figure 11. TLP I-V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10 s
of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 12 where an 8 kV
IEC61000-4-2 current waveform is compared with TLP current pulses at 8 and 16 A. A TLP curve shows the voltage at which
the device turns on as well as how well the device clamps voltage over a range of current levels. Typical TLP I-V curves for
the EMI4182 are shown in Figure 13.
Attenuator
L
50 W Coax Cable
SW
÷
50 W Coax
Cable
VM
IM
10 MW
VC
DUT
Oscilloscope
Figure 11. Simplified Schematic of a Typical TLP System
Figure 12. Comparison Between 8 kV IEC61000−4−2 and 8 A and 16 A TLP Waveforms
Figure 13. Positive and Negative TLP Waveforms
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6
EMI4182
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low
a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per
the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones
or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor
has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD
pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these screenshots and how to interpret them please refer to On Semiconductor
Application Notes AND8307/D and AND8308/D.
IEC61000−4−2 Waveform
IEC61000−4−2 Spec.
I
peak
Test
Voltage
(kV)
First Peak
Current
(A)
100%
90%
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 14. Diagram of ESD Test Setup
100
90
80
70
60
50
40
30
20
t
r
PEAK VALUE I
@ 8 ms
RSM
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 15. 8 x 20 ms Pulse Waveform
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7
EMI4182
Figure 16. ESD Clamping Voltage +8 kV per IEC6100−4−2 (external to internal pin)
Figure 17. ESD Clamping Voltage −8 kV per IEC6100−4−2 (external to internal pin)
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8
EMI4182
HDMI Type−A
Connector
EMI4182
D2+
GND
D2−
D1+
TMDS Data 2+
TMDS Data 2−
TMDS Data 1+
GND
D1−
TMDS Data 1−
1
10
EMI4182
D0+
TMDS Data 0+
GND
TMDS Data 0−
D0−
CLK+
GND
TMDS Clock+
TMDS Clock−
CEC
1
10
CLK−
CEC
SCL
SDA
HEC DATA
SCL
Hot Plug Detect
SDA
GND
NUP4114
+5V Power
5V
HTP _D
Black = Top layer
Red = other layer
Figure 18. EMI4182 HDMI Type – A Connector Application Diagram
HDMI Type −D
Connector
EMI4182
TMDS Data 2+
PIN 1
TMDS Data 2−
HTP_D
Util
D2+
GND
D2−
TMDS Data 1+
D1+
GND
D1−
TMDS Data 1−
1
10
D0+
D0−
GND
CEC
SCL
5V
GND
TMDS Data 0+
CLK +
TMDS Data 0−
CLK −
GND
SDA
TMDS Clock +
TMDS Clock −
Black = Top layer
Red = other layer
1
10
EMI4182
CEC
SCL
+5V Power
SDA
NUP4114
Figure 19. EMI4182 HDMI Type − D Connector Application Diagram
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9
EMI4182
PACKAGE DIMENSIONS
WDFN10 2.5x2, 0.5P
CASE 511BM−01
ISSUE O
L
L
NOTES:
A
B
E
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
2X
0.10
C
PIN 1
REFERENCE
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
A3
DIM MIN
MAX
0.80
0.05
EXPOSED Cu
MOLD CMPD
2X
0.10
C
A 0.70
TOP VIEW
A1
A3
b
0.00
0.20 REF
(A3)
0.15
0.25
DETAIL B
0.05
C
D
2.50 BSC
2.00 BSC
0.50 BSC
A1
E
A
e
DETAIL B
L
0.70
0.05
0.90
0.15
ALTERNATE
0.05
C
L1
CONSTRUCTIONS
NOTE 4
A1
SEATING
PLANE
C
SIDE VIEW
DETAIL A
RECOMMENDED
MOUNTING FOOTPRINT
1
5
6
8X
0.30
PACKAGE
8X
OUTLINE
8X
L
1.07
0.10
MIN
2.30
10
b
9X
e
1
M
M
C A B
0.10
0.05
NOTE 3
C
0.45
0.50 PITCH
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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EMI4182/D
相关型号:
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