DTC143TXV3T1 [ONSEMI]
Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network; 数字晶体管（ BRT ） NPN硅表面贴装晶体管与单片偏置电阻网络
| 型号： | DTC143TXV3T1 |
| 厂家： | 
ONSEMI |
| 描述： | Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network |
| 文件： | 总10页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DTC114EXV3T1 Series
Digital Transistors (BRT)
NPN Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The digital transistor
contains a single transistor with a monolithic bias network consisting
of two resistors; a series base resistor and a base−emitter resistor. The
digital transistor eliminates these individual components by
integrating them into a single device. The use of a digital transistor can
reduce both system cost and board space. The device is housed in the
SC−89 package which is designed for low power surface mount
applications.
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NPN SILICON
DIGITAL
TRANSISTORS
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Available in 8 mm, 7 inch/3000 Unit Tape & Reel
• Lead−Free Solder Plating (Pure Sn)
PIN 3
COLLECTOR
(OUTPUT)
PIN 1
BASE
(INPUT)
R1
R2
PIN 2
EMITTER
(GROUND)
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
Value
50
Unit
Vdc
V
CBO
V
CEO
50
Vdc
3
I
C
100
mAdc
2
1
SC−89
CASE 463C
STYLE 1
MARKING DIAGRAM
3
xx D
1
2
xx = Specific Device Code
(See Marking Table on page 2)
D = Date Code
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
DTC114EXV3T1/D
January, 2004 − Rev. 0
DTC114EXV3T1 Series
DEVICE MARKING AND RESISTOR VALUES
Device
Marking
R1 (K)
R2 (K)
Shipping†
DTC114EXV3T1
DTC124EXV3T1
DTC144EXV3T1
DTC114YXV3T1
DTC114TXV3T1
DTC143TXV3T1
8A
8B
8C
8D
94
8F
10
22
47
10
10
4.7
10
22
47
47
∞
3000/Tape & Reel
∞
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure,
BRD8011/D.
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Total Device Dissipation,
P
D
FR−4 Board (Note 1) @ T = 25°C
Derate above 25°C
200
1.6
mW
mW/°C
A
Thermal Resistance, Junction−to−Ambient (Note 1)
Total Device Dissipation,
R
600
°C/W
θ
JA
P
D
FR−4 Board (Note 2) @ T = 25°C
Derate above 25°C
300
2.4
mW
mW/°C
A
Thermal Resistance, Junction−to−Ambient (Note 2)
Junction and Storage Temperature Range
R
400
°C/W
°C
θ
JA
T , T
J
−55 to +150
stg
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 × 1.0 Inch Pad.
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2
DTC114EXV3T1 Series
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Collector−Base Cutoff Current (V = 50 V, I = 0)
I
I
−
−
−
−
100
500
nAdc
nAdc
mAdc
CB
E
CBO
Collector−Emitter Cutoff Current (V = 50 V, I = 0)
CE
B
CEO
Emitter−Base Cutoff Current
(V = 6.0 V, I = 0)
DTC114EXV3T1
DTC124EXV3T1
DTC144EXV3T1
DTC114YXV3T1
DTC114TXV3T1
DTC143TXV3T1
I
−
−
−
−
−
−
−
−
−
−
−
−
0.5
0.2
0.1
0.2
0.9
1.9
EBO
EB
C
Collector−Base Breakdown Voltage (I = 10 µA, I = 0)
V
V
50
50
−
−
−
−
Vdc
Vdc
C
E
(BR)CBO
Collector−Emitter Breakdown Voltage (Note 3)
(BR)CEO
(I = 2.0 mA, I = 0)
C
B
ON CHARACTERISTICS (Note 3)
DC Current Gain
DTC114EXV3T1
DTC124EXV3T1
DTC144EXV3T1
DTC114YXV3T1
DTC114TXV3T1
DTC143TXV3T1
h
FE
35
60
80
80
160
160
60
−
−
−
−
−
−
(V = 10 V, I = 5.0 mA)
100
140
140
350
350
CE
C
Collector−Emitter Saturation Voltage (I = 10 mA, I = 0.3 mA)
V
CE(sat)
−
−
0.25
Vdc
Vdc
C
B
(I = 10 mA, I = 1.0 mA) DTC143TXV3T1/DTC114TXV3T1
C
B
Output Voltage (on)
(V = 5.0 V, V = 2.5 V, R = 1.0 kΩ)
V
OL
DTC114EXV3T1
DTC124EXV3T1
DTC114YXV3T1
DTC114TXV3T1
DTC143TXV3T1
DTC144EXV3T1
−
−
−
−
−
−
−
−
−
−
−
−
0.2
0.2
0.2
0.2
0.2
0.2
CC
B
L
(V = 5.0 V, V = 3.5 V, R = 1.0 kΩ)
CC
B
L
Output Voltage (off) (V = 5.0 V, V = 0.5 V, R = 1.0 kΩ)
V
OH
4.9
−
−
Vdc
CC
B
L
(V = 5.0 V, V = 0.25 V, R = 1.0 kΩ)
DTC143TXV3T1
CC
B
L
DTC114TXV3T1
Input Resistor
DTC114EXV3T1
DTC124EXV3T1
DTC144EXV3T1
DTC114YXV3T1
DTC114TXV3T1
DTC143TXV3T1
R1
7.0
15.4
32.9
7.0
7.0
3.3
10
22
47
10
10
4.7
13
28.6
61.1
13
13
6.1
kΩ
Resistor Ratio
DTC114EXV3T1/DTC124EXV3T1/
DTC144EXV3T1
R /R
0.8
1.0
1.2
1
2
DTC114YXV3T1
DTC143TXV3T1/DTC114TXV3T1
0.17
−
0.21
−
0.25
−
3. Pulse Test: Pulse Width < 300 µs, Duty Cycle < 2.0%.
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3
DTC114EXV3T1 Series
250
200
150
100
50
R
= 600°C/W
θ
JA
0
−ꢀ50
0
50
100
150
T , AMBIENT TEMPERATURE (°C)
A
Figure 1. Derating Curve
1.0
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.001
0.00001
0.0001
0.001
0.01
0.1
t, TIME (s)
1.0
10
100
1000
Figure 2. Normalized Thermal Response
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4
DTC114EXV3T1 Series
TYPICAL ELECTRICAL CHARACTERISTICS − DTC114EXV3T1
1
1000
I /I = 10
C B
V
CE
= 10 V
T ꢁ=ꢁ−25°C
A
25°C
T ꢁ=ꢁ75°C
A
25°C
0.1
−25°C
75°C
100
0.01
0.001
10
0
20
40
50
1
10
100
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 3. VCE(sat) versus IC
Figure 4. DC Current Gain
4
3
100
10
25°C
75°C
f = 1 MHz
I = 0 V
E
T ꢁ=ꢁ−25°C
A
T = 25°C
A
1
0.1
2
1
0
0.01
0.001
V
O
= 5 V
9
0
10
20
30
40
50
0
1
2
3
4
5
6
7
8
10
V , REVERSE BIAS VOLTAGE (VOLTS)
R
V , INPUT VOLTAGE (VOLTS)
in
Figure 5. Output Capacitance
Figure 6. Output Current versus Input Voltage
10
V
O
= 0.2 V
T ꢁ=ꢁ−25°C
A
25°C
75°C
1
0.1
0
10
20
30
40
50
I , COLLECTOR CURRENT (mA)
C
Figure 7. Input Voltage versus Output Current
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5
DTC114EXV3T1 Series
TYPICAL ELECTRICAL CHARACTERISTICS − DTC124EXV3T1
1000
1
V
CE
= 10 V
I /I = 10
C B
T ꢁ=ꢁ75°C
A
25°C
25°C
T ꢁ=ꢁ−25°C
A
0.1
−25°C
75°C
100
0.01
10
0.001
1
10
100
0
20
40
50
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 8. VCE(sat) versus IC
Figure 9. DC Current Gain
4
3
2
1
0
100
10
1
75°C
25°C
f = 1 MHz
T ꢁ=ꢁ−25°C
A
I = 0 V
E
T = 25°C
A
0.1
0.01
V
O
= 5 V
0.001
0
10
20
30
40
50
0
2
4
6
8
10
V , REVERSE BIAS VOLTAGE (VOLTS)
R
V , INPUT VOLTAGE (VOLTS)
in
Figure 10. Output Capacitance
Figure 11. Output Current versus Input Voltage
100
V
O
= 0.2 V
T ꢁ=ꢁ−25°C
A
10
1
25°C
75°C
0.1
0
10
20
30
40
50
I , COLLECTOR CURRENT (mA)
C
Figure 12. Input Voltage versus Output Current
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6
DTC114EXV3T1 Series
TYPICAL ELECTRICAL CHARACTERISTICS − DTC144EXV3T1
10
1
1000
V
= 10 V
CE
I /I = 10
C B
T ꢁ=ꢁ75°C
A
25°C
−25°C
25°C
75°C
100
T ꢁ=ꢁ−25°C
A
0.1
0.01
10
0
20
I , COLLECTOR CURRENT (mA)
40
50
1
10
100
I , COLLECTOR CURRENT (mA)
C
C
Figure 13. VCE(sat) versus IC
Figure 14. DC Current Gain
1
100
10
1
25°C
f = 1 MHz
I = 0 V
75°C
E
T ꢁ=ꢁ−25°C
A
0.8
T = 25°C
A
0.6
0.4
0.1
0.01
0.2
0
V
O
= 5 V
0.001
0
10
20
30
40
50
0
2
4
6
8
10
V , REVERSE BIAS VOLTAGE (VOLTS)
R
V , INPUT VOLTAGE (VOLTS)
in
Figure 15. Output Capacitance
Figure 16. Output Current versus Input Voltage
100
V
O
= 0.2 V
T ꢁ=ꢁ−25°C
A
25°C
75°C
10
1
0.1
0
10
20
30
40
50
I , COLLECTOR CURRENT (mA)
C
Figure 17. Input Voltage versus Output Current
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7
DTC114EXV3T1 Series
TYPICAL ELECTRICAL CHARACTERISTICS − DTC114YXV3T1
1
300
T ꢁ=ꢁ75°C
A
V
CE
= 10
I /I = 10
C B
T ꢁ=ꢁ−25°C
250
200
150
100
A
25°C
25°C
75°C
0.1
−25°C
0.01
50
0
0.001
0
20
40
60
80
1
2
4
6
8
10 15 20 40 50 60 70 80 90 100
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 18. VCE(sat) versus IC
Figure 19. DC Current Gain
4
3.5
3
100
10
1
f = 1 MHz
T ꢁ=ꢁ75°C
25°C
A
l = 0 V
E
T = 25°C
A
−25°C
2.5
2
1.5
1
0.5
0
V
O
= 5 V
0
2
4
6
8
10 15 20 25 30 35 40 45 50
0
2
4
6
8
10
V , REVERSE BIAS VOLTAGE (VOLTS)
R
V , INPUT VOLTAGE (VOLTS)
in
Figure 20. Output Capacitance
Figure 21. Output Current versus Input Voltage
10
V
O
= 0.2 V
T ꢁ=ꢁ−25°C
A
25°C
75°C
1
0.1
0
10
20
30
40
50
I , COLLECTOR CURRENT (mA)
C
Figure 22. Input Voltage versus Output Current
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8
DTC114EXV3T1 Series
TYPICAL APPLICATIONS FOR NPN BRTs
+12 V
ISOLATED
LOAD
FROM µP OR
OTHER LOGIC
Figure 23. Level Shifter: Connects 12 or 24 Volt Circuits to Logic
+12 V
V
CC
OUT
IN
LOAD
Figure 24. Open Collector Inverter:
Inverts the Input Signal
Figure 25. Inexpensive, Unregulated Current Source
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9
DTC114EXV3T1 Series
PACKAGE DIMENSIONS
SC−89
CASE 463C−03
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
−X−
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
3
S
4. 463C−01 OBSOLETE, NEW STANDARD 463C−02.
B
−Y−
1
2
K
MILLIMETERS
DIM MIN NOM MAX
INCHES
MIN NOM MAX
A
B
C
D
G
H
J
K
L
M
N
S
1.50
0.75
0.60
0.23
1.60
0.85
0.70
1.70 0.059 0.063 0.067
0.95 0.030 0.034 0.040
0.80 0.024 0.028 0.031
0.33 0.009 0.011 0.013
0.020 BSC
G
2 PL
3 PL
D
0.28
M
0.08 (0.003)
X Y
0.50 BSC
0.53 REF
0.15
0.40
1.10 REF
−−−
0.021 REF
0.10
0.30
0.20 0.004 0.006 0.008
0.50 0.012 0.016 0.020
0.043 REF
−−−
−−−
1.50
10
10
−−−
−−−
−−−
−−−
10
10
_
_
_
_
N
M
−−−
1.60
J
1.70 0.059 0.063 0.067
C
STYLE 1:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
SEATING
PLANE
−T−
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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DTC114EXV3T1/D
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