CM1231-02SO [ONSEMI]
ESD 箝位保护阵列;
| 型号： | CM1231-02SO |
| 厂家： | 
ONSEMI |
| 描述： | ESD 箝位保护阵列 局域网 PC 光电二极管 电视 |
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CM1231-02SO
2, 4 and 8-Channel
Low-Capacitance ESD
Protection Array
Product Description
http://onsemi.com
The CM1231−02SO is a member of the XtremeESDt product
family and is specifically designed for next generation deep
submicron ASIC protection. These devices are ideal for protecting
systems with high data and clock rates and for circuits requiring low
capacitive loading such as USB 2.0.
The CM1231−02SO incorporates the PicoGuard XPt dual stage
ESD architecture which offers dramatically higher system level ESD
protection compared with traditional single clamp designs. In
addition, the CM1231−02SO provides a controlled filter roll−off for
even greater spurious EMI suppression and signal integrity.
The CM1231−02SO protects against ESD pulses up to 12 kV
contact on the “OUT” pins per the IEC 61000−4−2 standard.
The device also features easily routed “pass−through” differential
pinouts in a 6−lead SOT23 package.
SOT23−6
SO SUFFIX
CASE 527AJ
MARKING DIAGRAM
D312 MG
G
Features
1
• Two Channels of ESD Protection
• Exceeds ESD Protection to IEC61000−4−2 Level 4:
D312
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
•
12 kV Contact Discharge (OUT Pins)
• Two−Stage Matched Clamp Architecture
(Note: Microdot may be in either location)
• Matching−of−Series Resistor (R) of 10 mW Typical
• Flow−Through Routing for High−Speed Signal Integrity
• Differential Channel Input Capacitance Matching of 0.02 pF Typical
• Improved Powered ASIC Latchup Protection
ORDERING INFORMATION
†
Device
Package
Shipping
CM1231−02SO
SOT23−6 3000/Tape & Reel
(Pb−Free)
• Dramatic Improvement in ESD Protection vs. Best in Class
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Single−Stage Diode Arrays
• 40% Reduction in Peak Clamping Voltage
• 40% Reduction in Peak Residual Current
• Withstands over 1000 ESD Strikes*
• Available in a SOT23−6 Package
• These Devices are Pb−Free and are RoHS Compliant
Applications
• USB Devices Data Port Protection
• General High−Speed Data Line ESD Protection
*Standard test condition is IEC61000−4−2 level 4 test circuit with each (A
/B
) pin subjected to 12 kV contact discharge for 1000 pulses.
OUT OUT
Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
February, 2011 − Rev. 3
CM1231−02SO/D
CM1231−02SO
ELECTRICAL SCHEMATIC
Positive Supply Rail
V
P
V
CC
V
P
CM1231
A
B
1 W
A
OUT
IN
IN
Circuitry
Under
Protection
Connector
1 W
B
OUT
V
N
V
N
Ground Rail
PACKAGE / PINOUT DIAGRAMS
Table 1. PIN DESCRIPTIONS
Pin
Name
Description
B
V
B
IN
OUT
P
1
A
OUT
Bidirectional clamp to Connector
(Outside the system)
6
5
4
2
3
4
5
6
V
Ground return to Shield
N
D312
A
IN
B
IN
Bidirectional clamp to ASIC (Inside the system)
Bidirectional clamp to ASIC (Inside the system)
Bias voltage (optional)
1
2
3
V
P
A
V
N
A
IN
OUT
B
OUT
Bidirectional clamp to Connector
(Outside the system)
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
6.0
Units
V
Operating Supply Voltage (V )
P
Diode Forward DC Current (A
/B
Side)
8.0
mA
mA
°C
OUT OUT
Continuous Current through Signal Pins (IN to OUT) 1000 hours
Operating Temperature Range
125
−40 to +85
−65 to +150
Storage Temperature Range
°C
DC Voltage at any channel input
(V − 0.5) to (V + 0.5)
V
N
P
Package Power Rating (SOT23−6)
225
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
CM1231−02SO
Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Operating Supply Voltage
Conditions
Min
Typ
Max
5.5
1
Units
V
V
P
5
I
Operating Supply Current
V = 5 V
mA
V
CC5
P
V
F
Diode Forward Voltage
Top Diode
Bottom Diode
I = 8 mA, T = 25°C
F A
0.60
0.60
0.80
0.80
0.95
0.95
V
ESD
ESD Protection, Contact Discharge per IEC
T = 25°C
A
kV
61000−4−2 Standard
OUT−to−V Contact
12
4
N
IN−to−V Contact
N
I
Residual ESD Peak Current on RDUP
(Resistance of Device Under Protection)
IEC 61000−4−2 8 kV
A
V
RES
RDUP = 5 W, T = 25°C
2.3
A
V
Channel Clamp Voltage
Positive Transients
Negative Transients
I = 1 A, T = 25°C, t = 8/20 ms,
PP A P
CL
Zap at OUT, Measure at IN
= 1 A, T = 25°C, t = 8/20 ms,
+9
–1.4
R
C
Dynamic Resistance
Positive Transients
Negative Transients
I
PP
W
DYN
A
P
Zap at OUT, Measure at IN
0.4
0.3
OUT Capacitance
f = 1 MHz, V = 5.0 V, V = 2.5 V,
1.5
pF
OUT
P
IN
V
OSC
= 30 mV
(Note 2)
DC
Channel to Channel Capacitance Match
f = 1 MHz, V = 5.0 V, V = 2.5 V,
OSC
0.02
pF
OUT
P
IN
V
= 30 mV
R
Series Resistance
1
W
S
DR
Channel to Channel Resistance Match
10
30
mW
S
1. All parameters specified at T = –40°C to +85°C unless otherwise noted.
A
2. Capacitance measured from OUT to V with IN floating.
N
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3
CM1231−02SO
SINGLE AND DUAL CLAMP ESD PROTECTION
The following sections describe the standard single clamp ESD protection device and the dual clamp ESD protection
architecture of the CM1231−02SO.
Single Clamp ESD Protection
Conceptually, an ESD protection device performs the following actions upon a strike of ESD discharge into the protected
ASIC (see Figure 1).
1. When an ESD potential is applied to the system
under test (contact or air−discharge), Kirchoff’s
Current Law (KCL) dictates that the Electrical
Overstress (EOS) currents will immediately divide
throughout the circuit, based on the dynamic
impedance of each path
2. Ideally, the classic shunt ESD clamp will switch
within 1 ns to a low−impedance path and return the
majority of the EOS current to the chassis
shield/reference ground. In actuality, if the ESD
Resistance (R
) is not significantly lower than
DYN
the ASIC’s I/O cell circuitry, then the ASIC will have
to absorb a large amount of the EOS energy, and may
be more likely to fail.
3. Subsequent to the ESD/EOS event, both devices
must immediately return to their original
specifications, ready for an additional strike. Any
deterioration in parasitics or clamping capability
should be considered a failure, as it can affect signal
integrity or subsequent protection capability (this is
known as “multi−strike” capability.)
component’s response time (t ) is slower than
CLAMP
the ASIC it is protecting, or if the Dynamic
ESD Strike
ESD
Protection
Device
ASIC
I/O Connector
I
SHUNT
I
RESIDUAL
Figure 1. Single Clamp ESD Protection Block Diagram
Dual Clamp ESD Protection
In the CM1231−02SO dual clamp PicoGuard XPt
architecture, the first stage begins clamping immediately, as
it does in the single clamp case. The dramatically reduced
This disconnection between the outside node and the
inside ASIC node allows the stage one clamps to turn on and
remain in the shunt mode before the ASIC begins to shunt
the reduced residual pulse. This gives the advantage to the
ESD component in the current division equation, and
dramatically reduces the residual energy that the ASIC must
dissipate.
I
current from stage one passes through the 1 W series
RES
element and then gradually feeds into the stage two ESD
device (see Figure 2). The series inductive and resistive
elements further limit the current into the second stage, and
greatly attenuate the resultant peak incident pulse presented
at the ASIC side of the device.
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4
CM1231−02SO
ESD Strike
1 W
ESD
ESD
Protection
Stage 1
Protection
Stage 2
I/O Connector
ASIC
I
I
SHUNT2
SHUNT1
I
RESIDUAL
Figure 2. Dual Clamp ESD Protection Block Diagram
CM1231−02SO ARCHITECTURE OVERVIEW
The PicoGuard XPt two−stage per channel matched
current pulse to either the positive (V ) or negative (V )
P N
clamp architecture with isolated clamp rails features a series
supply rail.
A zener diode is embedded between V and V , offering
element to radically reduce the residual ESD current (I
)
RES
P
N
that enters the ASIC under protection (see Figure 3). From
stage 1 to stage 2, the signal lines go through matched dual
1 W resistors.
The function of the series element (dual 1 W resistors for
the CM1231−02SO) is to optimize the operation of the stage
two advantages. First, it protects the V rail against ESD
CC
strikes. Second, it eliminates the need for an additional
bypass capacitor to shunt the positive ESD strikes to ground.
The CM1231−02SO therefore replaces as many as seven
discrete components, while taking advantage of precision
internal component matching for improved signal integrity,
which is not otherwise possible with discrete components at
the system level.
two diodes to reduce the final I
current to a minimum
RES
while maintaining an acceptable insertion impedance that is
negligible for the associated signaling levels.
Each stage consists of a traditional low−cap Dual Rail
Clamp structure which steer the positive or negative ESD
V
CC
Positive Supply Rail
V
P
1 W
Circuitry
Under
I
ESD
Protection
I
RESIDUAL
V
N
Ground Rail
Figure 3. CM1231−02SO Block Diagram (IESD Flow During a Positive Strike)
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5
CM1231−02SO
Advantages of the CM1231−02SO Dual Stage ESD Protection Architecture
Figure 4 illustrates a single stage ESD protection device. The inductor element represents the parasitic inductance arising
from the bond wire and the PCB trace leading to the ESD protection diodes.
Connector
ASIC
Bond Wire
Inductance
ESD
Stage
Figure 4. Single Stage ESD Protection Model
Figure 5 illustrates one of the two CM1231−02SO channels. Similarly, the inductor elements represent the parasitic
inductance arising from the bond wire and PCB traces leading to the ESD protection diodes as well.
Bond Wire
Inductance
Bond Wire
Inductance
Series
Element
Connector
ASIC
st
nd
1
2
Stage
Stage
Figure 5. CM1231−02SO Dual Stage ESD Protection Model
CM1231−02SO Inductor Elements
In the CM1231−02SO dual stage PicoGuard XPt
architecture, the inductor elements and ESD protection
diodes interact differently compared to the single stage
model.
In the single stage model, the inductive element presents
high impedance at high frequency, i.e. during an ESD strike.
The impedance increases the resistance of the conduction
path leading to the ESD protection element. This limits the
speed that the ESD pulse can discharge through the single
stage protection element.
In the PicoGuard XPt architecture, the inductance
elements are in series to the conduction path leading to the
protected device. The elements actually help to limit the
current and voltage striking the protected device.
The reactance of the series and the inductor elements in
the second stage forces more of the ESD strike current to be
shunted through the first stage. At the same time the voltage
drop across series element helps to lower the clamping
voltage at the protected terminal.
The inductor elements also tune the impedance of the
stage by cancelling the capacitive load presented by the ESD
diodes to the signal line. This improves the signal integrity
and makes the ESD protection stages more transparent to the
high bandwidth data signals passing through the channel.
The innovative PicoGuard XPt architecture turns the
disadvantages of the parasitic inductive elements into useful
components that help to limit the ESD current strike to the
protected device and also improves the signal integrity of the
system by balancing the capacitive loading effects of the
ESD diodes.
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6
CM1231−02SO
GRAPHICAL COMPARISON AND TEST SETUP
The following graphs (see Figure 6, Figure 7 and Figure 8) show that the CM1231−02SO (dual stage ESD protector) lowers
the peak voltage and clamping voltage by 40% across a wide range of loading conditions in comparison to a standard single
stage device. This data was derived using the test setups shown in Figure 9 and Figure 10.
Figure 6. IEC 61000−4−2 Vpeak vs. Loading (RDUP*)
Figure 7. IEC 61000−4−2 Vclamp vs. Loading (RDUP*)
*RDUP indicates the amount of Resistance (load) supplied to the Device Under Protection (DUP) through a variable resistor.
Figure 8. IEC 61000−4−2 IRES (Residual ESD Peak Current) vs. Loading (RDUP)
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7
CM1231−02SO
Voltage
Probe
IEC 61000−4−2
Test Standards
Device Under
Protection (DUP)
Single Stage
ESD Device
R
VARIABLE
Current
Probe
I
RESIDUAL
Figure 9. Single Stage ESD Device Test Setup
IEC 61000−4−2
Test Standards
Voltage
Probe
CM1231
Device Under
Protection (DUP)
R
VARIABLE
Current
Probe
I
RESIDUAL
Figure 10. CM1231−02SO Test Setup
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8
CM1231−02SO
PERFORMANCE INFORMATION
Figure 11. Clamping Voltage vs. Peak Current
Figure 12. Capacitance vs. Bias Voltage
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9
CM1231−02SO
PERFORMANCE INFORMATION (Cont‘d)
Typical Filter Performance (Nominal Conditions unless Specified Otherwise, 0 V DC bias, 50 W Environment)
Figure 13. Typical Single−Ended S21 Plot (1 dB/div, 3 MHz to 6 GHz)
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10
CM1231−02SO
APPLICATION INFORMATION
CM1231−02SO Application and Guidelines
The CM1231−02SO has an integrated zener diode
between V and V (for each of the two stages). This greatly
With the CM1231−02SO, this additional bypass capacitor
is generally not required.
P
N
reduces the effect of supply rail inductance L on V by
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor
2
CL
clamping V at the breakdown voltage of the zener diode.
P
However, for the lowest possible V , especially when V
CL
P
is biased at a voltage significantly below the zener
mentioned above should be as close to the V pin of the
P
breakdown voltage, it is recommended that a 0.22 mF
Protection Array as possible, with minimum PCB trace
lengths to the power supply, ground planes and between the
signal input and the ESD device to minimize stray series
inductance.
ceramic chip capacitor be connected between V and the
P
ground plane.
Figure 14. Typical Layout with Optional VP Cap Footprint
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection,” in the Applications section.
PicoGuard XP is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23, 6 Lead
CASE 527AJ
ISSUE B
DATE 29 FEB 2012
SCALE 2:1
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C IS THE SEATING PLANE.
6
1
5
2
4
3
MILLIMETERS
E
E1
L2
GAGE
PLANE
DIM MIN
MAX
1.45
0.15
1.30
0.50
0.26
3.00
3.10
1.80
A
A1
A2
b
---
0.00
0.90
0.20
0.08
2.70
2.50
1.30
SEATING
PLANE
6X b
0.20
L
c
e
M
S
S
D
C A
B
DETAIL A
E
TOP VIEW
E1
e
0.95 BSC
A2
A
L
0.20
0.60
L2
0.25 BSC
c
GENERIC
MARKING DIAGRAM*
6X
0.10 C
DETAIL A
SEATING
PLANE
END VIEW
C
A1
SIDE VIEW
XXX MG
G
RECOMMENDED
SOLDERING FOOTPRINT*
1
XXX
M
= Specific Device Code
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
3.30
6X
0.85
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
6X
0.56
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34321E
SOT−23, 6 LEAD
PAGE 1 OF 1
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