CM1215-02SO [ONSEMI]
1-, 2- and 4-Channel Low Capacitance ESD Arrays;
| 型号： | CM1215-02SO |
| 厂家： | 
ONSEMI |
| 描述： | 1-, 2- and 4-Channel Low Capacitance ESD Arrays 局域网 光电二极管 |
| 文件： | 总10页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Is Now
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www.onsemi.com
onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdonsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
CM1215
1, 2 and 4-Channel
Low Capacitance
ESD Arrays
Product Description
http://onsemi.com
The CM1215 family of diode arrays provides ESD protection for
electronic components or sub−systems requiring minimal capacitive
loading. These devices are ideal for protecting systems with high data
and clock rates or for circuits requiring low capacitive loading. Each
ESD channel consists of a pair of diodes in series which steer the
positive or negative ESD current pulse to either the positive (VP) or
negative (VN) supply rail. The CM1215 protects against ESD pulses
up to 15 kV per the IEC 61000−4−2 standard.
SOT23−3
SO SUFFIX
SOT143
SR SUFFIX
CASE 527AF
CASE 419AH
This device is particularly well−suited for protecting systems using
high−speed ports such as USB2.0, IEEE1394 (Firewire®, iLinkt),
Serial ATA, DVI, HDMI and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
SOT23−5
SO SUFFIX
CASE 527AH
SOT23−6
SO SUFFIX
CASE 527AJ
MARKING DIAGRAM
Features
• One, two, and four channels of ESD Protection
• Provides 15 kV ESD Protection on Each Channel Per the IEC
61000−4−2 ESD Requirements
• Channel Loading Capacitance of 1.6 pF Typical
• Channel I/O to GND Capacitance Difference of 0.04 pF Typical
• Mutual Capacitance of 0.13 pF Typical
E151 MG
E152 MG
G
G
1
E153 MG
E154 MG
• Minimal Capacitance Change with Temperature and Voltage
• Each I/O Pin Can Withstand Over 1000 ESD Strikes
• SOT Packages
G
G
1
1
• These Devices are Pb−Free and are RoHS Compliant
XXXX = Specific Device Code
M
= Date Code
= Pb−Free Package
Applications
G
• IEEE1394 Firewire® Ports at 400 Mbps / 800 Mbps
(Note: Microdot may be in either location)
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
ORDERING INFORMATION
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
†
Device
Package
Shipping
• PCI Express Ports
CM1215−01SO
SOT23−3 3000/Tape & Reel
(Pb−Free)
• General Purpose High−Speed Data Line ESD Protection
CM1215−02SR
SOT143
3000/Tape & Reel
(Pb−Free)
CM1215−02SO
CM1215−04SO
SOT23−5 3000/Tape & Reel
(Pb−Free)
SOT23−6 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
July, 2011 − Rev. 3
CM1215/D
CM1215
BLOCK DIAGRAM
V
V
V
CH4
CH1
V
V
CH3
CH2
P
P
P
CH1
CH1
CH2
V
N
N
N
CM1215−04SO
CM1215−01SO
CM1215−02SO
CM1215−02SR
PACKAGE / PINOUT DIAGRAMS
Top View
Top View
Top View
Top View
V
1
4
V
P
CH1
1
NC
1
2
3
5
V
CH1
1
2
3
6
5
4
CH4
N
P
V
N
3
V
N
V
N
V
P
V
P
2
CH2
CH3
CH1
2
3
CH2
CH1
4
CH2
3−Pin SOT23−3
4−Pin SOT143
5−Lead SOT23−5
6−Pin SOT23−6
Table 1. PACKAGE PIN DESCRIPTIONS
SOT23−3
SOT143
SOT23−5
SOT23−6
Pin No.
Pin No.
Pin No.
Pin No.
Pin Name
Type
I/O
Description
CH1
1
3
−
−
2
−
−
2
1
3
−
4
−
−
3
2
4
−
5
−
1
1
2
3
4
5
6
−
ESD Channel
V
N
GND
I/O
Negative voltage supply rail
ESD Channel
CH2
CH3
I/O
ESD Channel
V
P
PWR
I/O
Positive voltage supply rail
ESD Channel
CH4
N/C
−
No Connection
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2
CM1215
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
V
Operating Supply Voltage (V −V )
6
P
N
Diode Forward DC Current (Note 1)
DC Voltage at any Channel Input
Operating Temperature Range
Ambient
20
mA
V
(V −0.5) to (V +0.5)
N
P
−40 to +85
−40 to +125
−40 to +150
°C
°C
°C
Junction
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Rating
Units
°C
–40 to +85
Package Power Rating
mW
SOT23−3 Package (CM1215−01SO)
SOT143 Package (CM1215−02SR)
SOT23−5 Package (CM1215−02SO)
SOT23−6 Package (CM1215−04SO)
225
225
225
225
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Operating Supply Voltage (V −V )
Conditions
Min
Typ
Max
5.5
8
Unit
V
V
P
3.3
P
N
I
P
Operating Supply Current
(V −V ) = 3.3 V
mA
V
P
N
V
F
Diode Forward Voltage
Top Diode
Bottom Diode
I = 20 mA; T = 25°C
F A
0.6
0.6
0.8
0.8
0.95
0.95
I
Channel Leakage Current
Channel Input Capacitance
T = 25°C; V = 5 V, V = 0 V
0.1
1.6
1.0
2.0
mA
LEAK
A
P
N
C
At 1 MHz, V = 3.3 V,
pF
IN
P
IN
V
N
= 0 V, V = 1.65V;
ΔC
Channel I/O to GND Capacitance Difference
Mutual Capacitance
0.04
0.13
pF
pF
kV
IN
C
(V −V ) = 3.3 V
P N
MUTUAL
V
ESD
ESD Protection
Peak Discharge Voltage at any channel input, T = 25°C
15
A
in system, contact discharge
(Notes 2 and 3)
per IEC 61000−4−2 standard
V
CL
Channel Clamp Voltage
Positive Transients
Negative Transients
I
= 1 A, t = 8/20 mS;
V
PP
A
P
T = 25°C;
V +1.5
P
N
V −1.5
R
Dynamic Resistance
Positive transients
Negative transients
I
= 1 A, t = 8/20 mS;
W
DYN
PP
A
P
T = 25°C;
0.4
0.4
1. All parameters specified at T = −40°C to +85°C unless otherwise noted.
A
2. Standard IEC 61000−4−2 with C
= 150 pF, R = 330 W, V = 3.3 V, V grounded.
Discharge P N
Discharge
3. From I/O pins to V or V only. V bypassed to V with low ESR 0.2 mF ceramic capacitor.
P
N
P
N
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3
CM1215
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of CIN vs. VIN
(f = 1 MHz, VP= 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN, TA =
255C)
Figure 2. Typical Filter Performance (Nominal Conditions unless
Specified Otherwise, 50 Ohm Environment)
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4
CM1215
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking
an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on
the line being protected is:
V
CL
= Fwd voltage drop of D + V
+ L1 x d(I
) / dt+ L2 x d(IESD) / dt
1
SUPPLY
ESD
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be
approximated by d(
increment in VCL!
)/dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
ESD
Similarly for negative ESD pulses, parasitic series inductance from the V pin to the ground rail will lead to drastically
N
increased negative voltage on the line being protected.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V pin of the Protection
P
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.
L1
POSITIVE SUPPLY
PATH OF ESD CURRENT
PULSE (IESD)
D1
SYSTEM OR
CIRCUITRY
BEING
LINE BEING
ONE
PROTECTED
C1
CHANNEL
PROTECTED
D2
CHANNEL
IMPUT
GROUND RAIL
CHASSI‘S GROUND
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
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5
CM1215
PACKAGE DIMENSIONS
SOT−23 3−Lead (TO−236AA)
CASE 419AH−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
3X b
E1
L2
3
GAUGE
PLANE
E
1
2
L
5. PIN ONE INDICATOR MUST BE LOCATED IN THE IN-
DICATED ZONE.
SEATING
C
PLANE
M
MILLIMETERS
e
e
DETAIL Z
DIM
A
A1
b
c
D
E
E1
e
L
L2
MIN
0.75
0.05
0.30
0.08
2.80
2.10
1.20
MAX
1.17
0.15
0.50
0.20
3.05
2.64
1.40
A
c
0.05
A1
SEATING
PLANE
0.95 BSC
DETAIL Z
C
0.40
0.60
0.25 BSC
M
0°
8°
RECOMMENDED
SOLDERING FOOTPRINT*
3X
0.56
3X
0.82
2.74
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
CM1215
PACKAGE DIMENSIONS
SOT−143, 4 Lead
CASE 527AF−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.22
0.15
1.07
0.50
0.89
0.20
3.04
2.64
1.40
0.80
0.05
0.75
0.30
0.76
0.08
2.80
2.10
1.20
D
e
0.90
4
1
3
2
b2
c
D
2.90
E1
E
E
E1
e
1.30
1.92 BSC
0.20 BSC
0.50
e1
L
0.40
0.60
e1
b
L1
L2
θ
0.54 REF
0.25
TOP VIEW
0°
8°
L2
q
c
A2
A1
A
L
b2
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC TO-253.
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7
CM1215
PACKAGE DIMENSIONS
SOT−23, 5 Lead
CASE 527AH−01
ISSUE O
D
SYMBOL
MIN
NOM
MAX
1.45
0.15
1.30
0.50
0.22
A
A1
A2
b
0.90
0.00
0.90
0.30
0.08
1.15
c
E
E1
D
2.90 BSC
2.80 BSC
1.60 BSC
0.95 BSC
0.45
E
E1
e
e
L
0.30
0.60
L1
0.60 REF
PIN #1 IDENTIFICATION
L2
θ
0.25 REF
4°
0°
5°
5°
8°
15°
15°
TOP VIEW
θ1
10°
θ2
10°
θ1
A2
A
θ
b
L1
L
θ2
c
A1
L2
SIDE VIEW
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-178.
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8
CM1215
PACKAGE DIMENSIONS
SOT−23, 6 Lead
CASE 527AJ−01
ISSUE A
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C IS THE SEATING PLANE.
6
1
5
2
4
3
MILLIMETERS
E
E
L2
GAGE
PLANE
DIM MIN
MAX
1.45
0.15
1.30
0.50
0.26
3.00
3.10
1.80
A
A1
A2
b
---
0.00
0.90
0.20
0.08
2.70
2.50
1.30
SEATING
PLANE
6X b
L
c
e
M
S
S
B
D
0.20
C
A
DETAIL A
E
TOP VIEW
E1
e
0.95 BSC
A2
A
L
0.20
0.60
L2
0.25 BSC
c
6X
0.10
C
DETAIL A
SEATING
PLANE
END VIEW
C
A1
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
3.30
6X
0.85
6X
0.56
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
FireWire is a registered trademark of Apple Computer, Inc.
iLink is a trademark of S. J. Electro Systems, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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CM1215/D
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