CAT93C66KI-1.8 [ONSEMI]
256X16 MICROWIRE BUS SERIAL EEPROM, PDSO8, EIAJ, SOIC-8;型号: | CAT93C66KI-1.8 |
厂家: | ONSEMI |
描述: | 256X16 MICROWIRE BUS SERIAL EEPROM, PDSO8, EIAJ, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
文件: | 总16页 (文件大小:168K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CAT93C66, CAT93W66
4 kb Microwire Serial CMOS
EEPROM
Description
The CAT93C66 is a 4 kb CMOS Serial EEPROM device which is
organized as either 256 registers of 16 bits (ORG pin at V ) or 512
CC
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registers of 8 bits (ORG pin at GND). The CAT93W66 features x16
memory organization only. Each register can be written (or read)
serially by using the DI (or DO) pin. The device features sequential
read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
SOIC−8
V, W* SUFFIX
CASE 751BD
UDFN−8
HU4 SUFFIX
CASE 517AZ
TDFN−8*
VP2 SUFFIX
CASE 511AK
Features
• High Speed Operation: 4 MHz (5 V), 2 MHz (1.8 V)
• 1.8 V to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization: CAT93C66
• Self−timed Write Cycle with Auto−clear
• Sequential Read
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
• Software Write Protection
• Power−up Inadvertent Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
SOIC−8
X SUFFIX
CASE 751BE
SOT23−6
TB SUFFIX
CASE 527AJ
• 100 Year Data Retention
• Industrial and Extended Temperature Ranges
• 8−lead PDIP, SOIC, TSSOP, 6−lead SOT−23, 8−pad TDFN and
UDFN Packages
PIN CONFIGURATION
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
1
2
3
4
8
7
6
5
1
8
CS
SK
DI
V
NC
ORG
GND
DO
CC
V
CC
V
CC
NC
V
2
3
4
7
6
5
CC
CS
SK
ORG
GND
DO
DI
ORG
CS
SK
CS
SK
DI
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2)*,
UDFN (HU4)
SOIC (W)*
CAT93C66
CAT93W66
DO
DO
1
2
3
6
5
4
DO
GND
DI
V
CC
DI
1
2
3
4
8
7
6
5
CS
SK
DI
V
CC
CS
SK
NC
NC
GND
GND
SOT−23 (TB)**
DO
GND
Figure 1. Functional Symbols
TDFN (VP2)
CAT93W66
CAT93C66 Selectable Organization:
* Not recommended for new designs
** CAT93C66 available in SOT−23 6−pin for x8
Organization. Contact factory for availability.
When the ORG pin is connected to V , the x16 organization is
CC
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
CAT93W66:
The device works in x16 mode only.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
April, 2012 − Rev. 11
CAT93C66/D
CAT93C66, CAT93W66
Table 1. PIN FUNCTION
Pin Name
Function
Pin Name
Function
Power Supply
CS
SK
DI
Chip Select
V
CC
Clock Input
GND
ORG (Note 1)
NC
Ground
Serial Data Input
Serial Data Output
Memory Organization
No Connection
DO
1. ORG Pin available for the CAT93C66 only.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 2)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 3. RELIABILITY CHARACTERISTICS (Note 3)
Symbol
(Note 4)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
3. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
4. Block Mode, V = 5 V, 25°C.
CC
Table 4. D.C. OPERATING CHARACTERISTICS − MATURE PRODUCT
(V = +1.8 V to +5.5 V, T = −40°C to +125°C unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
= 1 MHz, V = 5.0 V
Min
Max
Units
I
Power Supply Current
(Write)
f
f
1
mA
CC1
SK
CC
I
Power Supply Current
(Read)
= 1 MHz, V = 5.0 V
500
mA
mA
CC2
SK
CC
I
I
Power Supply Current
(Standby) (x8 Mode)
V
= GND or V
,
T = −40°C to +85°C
2
4
SB1
IN
CC
A
CS = GND ORG = GND
T = −40°C to +125°C
A
Power Supply Current
(Standby) (x16 Mode)
V
= GND or V , CS = GND
T = −40°C to +85°C
1
mA
mA
mA
SB2
IN
CC
A
ORG = Float or V
CC
T = −40°C to +125°C
A
2
I
LI
Input Leakage Current
Output Leakage Current
V
= GND to V
T = −40°C to +85°C
A
1
IN
CC
T = −40°C to +125°C
A
2
I
LO
V
= GND to V
,
T = −40°C to +85°C
1
OUT
CC
A
CS = GND
T = −40°C to +125°C
A
2
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
4.5 V ≤ V < 5.5 V
−0.1
2
0.8
V
V
V
V
V
V
V
V
IL1
CC
V
IH1
4.5 V ≤ V < 5.5 V
V
+ 1
CC
CC
V
1.8 V ≤ V < 4.5 V
0
V
x 0.2
IL2
IH2
CC
CC
V
1.8 V ≤ V < 4.5 V
V
V
x 0.7
V
+ 1
CC
CC
CC
V
4.5 V ≤ V < 5.5 V, I = 2.1 mA
0.4
OL1
OH1
CC
OL
V
4.5 V ≤ V < 5.5 V, I = −400 mA
2.4
CC
OH
V
1.8 V ≤ V < 4.5 V, I = 1 mA
0.2
OL2
OH2
CC
OL
V
1.8 V ≤ V < 4.5 V, I = −100 mA
− 0.2
CC
CC
OH
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2
CAT93C66, CAT93W66
Table 5. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (REV H)
(V = +1.8 V to +5.5 V, T =−40°C to +125°C unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
Min
Max
1
Units
mA
mA
I
I
Supply Current (Write)
Supply Current (Read)
Write, V = 5.0 V
CC
CC1
CC2
Read, DO open, f = 2 MHz, V = 5.0 V
500
2
SK
CC
I
Standby Current
(x8 Mode)
V
IN
= GND or V
T = −40°C to +85°C
mA
SB1
CC
A
CS = GND, ORG = GND
T = −40°C to +125°C
A
5
I
Standby Current
(x16 Mode)
V
= GND or V
T = −40°C to +85°C
1
mA
SB2
IN
CC
A
CS = GND,
ORG = Float or V
T = −40°C to +125°C
A
3
CC
I
Input Leakage Current
V
= GND to V
T = −40°C to +85°C
1
mA
mA
LI
IN
CC
A
T = −40°C to +125°C
A
2
I
LO
Output Leakage
Current
V
OUT
= GND to V
T = −40°C to +85°C
A
1
CC
CS = GND
T = −40°C to +125°C
A
2
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
4.5 V ≤ V < 5.5 V
−0.1
2
0.8
V
V
V
V
V
V
V
V
IL1
CC
V
IH1
4.5 V ≤ V < 5.5 V
V
+ 1
CC
CC
V
1.8 V ≤ V < 4.5 V
0
V
x 0.2
IL2
IH2
CC
CC
V
1.8 V ≤ V < 4.5 V
V
V
x 0.7
V
+ 1
CC
CC
CC
V
4.5 V ≤ V < 5.5 V, I = 3 mA
0.4
OL1
OH1
CC
OL
V
4.5 V ≤ V < 5.5 V, I = −400 mA
2.4
CC
OH
V
1.8 V ≤ V < 4.5 V, I = 1 mA
0.2
OL2
OH2
CC
OL
V
1.8 V ≤ V < 4.5 V, I = −100 mA
− 0.2
CC
CC
OH
Table 6. PIN CAPACITANCE (T = 25°C, f = 1.0 MHz, V = +5.0 V)
A
CC
Symbol
(Note 5)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
= 0 V
Min
Typ
Max
5
Units
pF
C
V
OUT
OUT
C
(Note 5)
V
IN
= 0 V
5
pF
IN
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 7. POWER−UP TIMING (Notes 6, 7)
Symbol
Parameter
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. t
and t are the delays required from the time V is stable until the specified operation can be initiated.
PUW CC
PUR
Table 8. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
4.5 V ≤ V ≤ 5.5 V
CC
Timing Reference Voltages
Input Pulse Voltages
4.5 V ≤ V ≤ 5.5 V
CC
0.2 V to 0.7 V
1.8 V ≤ V ≤ 4.5 V
CC
CC
CC
Timing Reference Voltages
Output Load
0.5 V
1.8 V ≤ V ≤ 4.5 V
CC
CC
Current Source I
/I
; CL = 100 pF
OLmax OHmax
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3
CAT93C66, CAT93W66
Table 9. A.C. CHARACTERISTICS − MATURE PRODUCT
(V = +1.8 V to +5.5 V, T = −40°C to +125°C, unless otherwise specified.) (Note 8)
CC
A
Limits
Min
50
Max
Symbol
Parameter
Units
ns
t
CS Setup Time
CSS
t
CS Hold Time
0
ns
CSH
t
DI Setup Time
100
100
ns
DIS
DIH
PD1
PD0
t
DI Hold Time
ns
t
t
Output Delay to 1
0.25
0.25
100
5
ms
Output Delay to 0
ms
t
(Note 9)
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
HZ
t
ms
ms
EW
t
0.25
0.25
0.25
CSMIN
t
ms
SKHI
t
ms
SKLOW
t
0.25
ms
SV
SK
DC
2000
kHz
MAX
8. Test conditions according to “A.C. Test Conditions” table.
9. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
Table 10. A.C. CHARACTERISTICS − NEW PRODUCT (Rev H)
(V = +1.8 V to +5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
CC
V
CC
= 1.8 V − 5.5 V
V
CC
= 4.5 V − 5.5 V
Min
50
Max
Min
50
0
Max
Symbol
Parameter
Units
ns
t
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
CSS
t
0
ns
CSH
t
100
100
50
50
ns
DIS
t
ns
DIH
t
Output Delay to 1
Output Delay to 0
0.25
0.25
100
5
0.1
0.1
100
5
ms
PD1
PD0
t
ms
t
(Note 10)
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
HZ
t
ms
ms
EW
t
0.25
0.25
0.25
0.1
0.1
0.1
CSMIN
t
ms
SKHI
t
ms
SKLOW
t
0.25
0.1
ms
SV
SK
DC
2000
DC
4000
kHz
MAX
10.This parameter is tested initially and after a design or process change that affects the parameter.
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4
CAT93C66, CAT93W66
Device Operation
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The CAT93C66 is a 4096−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C66 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 11−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
12−bit instructions control the reading, writing and erase
operations of the device. The CAT93W66 works in x16
mode only. The device operates on a single power supply
and will generate on chip, the high voltage required during
any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The instruction format is shown in Instruction Set table.
Table 11. INSTRUCTION SET
Address
Data
x8 (Note 11)
A8−A0
x16
x8 (Note 11)
x16
Instruction
READ
Start Bit
Opcode
10
Comments
Read Address AN – A0
Clear Address AN – A0
Write Address AN – A0
Write Enable
1
1
1
1
1
1
1
A7−A0
ERASE
WRITE
EWEN
EWDS
ERAL
11
A8−A0
A7−A0
01
A8−A0
A7−A0
D7−D0
D15−D0
00
11XXXXXXX
00XXXXXXX
10XXXXXXX
01XXXXXXX
11XXXXXX
00XXXXXX
10XXXXXX
01XXXXXX
00
Write Disable
00
Clear All Addresses
Write All Addresses
WRAL
00
D7−D0
D15−D0
11. The x8 memory organization is available for the CAT93C66 only.
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5
CAT93C66, CAT93W66
Read
Upon receiving a READ command and an address
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 3.
(clocked into the DI pin), the DO pin of the CAT93C66,
CAT93W66 will come out of the high impedance state and,
after sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable after
Erase/Write Enable and Disable
The device powers up in the write disable state. Any
writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C66,
CAT93W66 write and erase instructions, and will prevent
any accidental writing or clearing of the device. Data can be
read normally from the device regardless of the write
enable/disable status. The EWEN and EWDS instructions
timing is shown in Figure 4.
the specified time delay (t
or t ).
PD0
PD1
For the CAT93C66, CAT93W66 after the initial data word
has been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
t
t
SKLOW
t
SKHI
CSH
SK
t
t
DIH
DIS
VALID
VALID
DI
t
CSS
CS
t
, t
t
CSMIN
t
PD0 PD1
DIS
DO
DATA VALID
Figure 2. Synchronous Data Timing
SK
CS
DI
Don’t Care
A
N
A
N−1
A
0
1
1
0
t
PD0
HIGH−Z
DO
Dummy 0
D
D
0
Address + 1 Address + 2 Address + n
15 . . .
or
D
D
0
D
D
0
D
15 . . .
15 . . .
15 . . .
D
D
0
or
or
or
7 . . .
D
D
0
D
D
0
D
7 . . .
7 . . .
7 . . .
Figure 3. READ Instruction Timing
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6
CAT93C66, CAT93W66
Write
Erase
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t . The falling edge of CS will start the
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
t
(Figure 6). The falling edge of CS will start the self
CSMIN
CSMIN
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAT93C66,
CAT93W66 can be determined by selecting the device and
polling the DO pin. Since this device features Auto−Clear
before write, it is NOT necessary to erase a memory location
before it is written into.
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C66, CAT93W66 can be determined by selecting the
device and polling the DO pin. Once cleared, the content of
a cleared location returns to a logical “1” state.
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 4. EWEN/EWDS Instruction Timing
SK
t
CSMIN
STANDBY
CS
DI
STATUS
VERIFY
A
N
A
N−1
A
0
D
D
0
N
1
0
1
t
SV
t
HZ
BUSY
HIGH−Z
DO
READY
HIGH−Z
t
EW
Figure 5. Write Instruction Timing
SK
STANDBY
CS
DI
STATUS
VERIFY
t
CS
A
N
A
N−1
A
0
1
1
1
t
t
SV
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 6. Erase Instruction Timing
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7
CAT93C66, CAT93W66
Erase All
Write All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
t
(Figure 8). The falling edge of CS will start the self
CSMIN
CSMIN
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
device can be determined by selecting the device and polling
the DO pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the device can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STATUS VERIFY
STANDBY
t
CS
DI
1
0
0
1
0
t
SV
t
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 7. ERAL Instruction Timing
SK
CS
DI
STANDBY
STATUS VERIFY
t
CSMIN
1
0
0
0
1
D
D
0
N
t
SV
t
HZ
DO
BUSY
READY
HIGH−Z
t
EW
Figure 8. WRAL Instruction Timing
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8
CAT93C66, CAT93W66
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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9
CAT93C66, CAT93W66
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
http://onsemi.com
10
CAT93C66, CAT93W66
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
b
2.03
0.25
0.48
0.25
5.33
8.26
5.38
0.05
0.36
0.19
5.13
7.75
5.13
c
E
E1
D
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
e
b
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
http://onsemi.com
11
CAT93C66, CAT93W66
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
http://onsemi.com
12
CAT93C66, CAT93W66
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
0.45
NOM
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.75
0.02
A2
0.55
0.20 REF
0.25
A3
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
http://onsemi.com
13
CAT93C66, CAT93W66
PACKAGE DIMENSIONS
SOT−23, 6 Lead
CASE 527AJ−01
ISSUE O
D
SYMBOL
MIN
NOM
MAX
1.45
0.15
1.30
0.50
0.22
e
A
0.90
0.00
0.90
0.30
0.08
A1
A2
1.15
b
c
E
E1
D
E
2.90 BSC
2.80 BSC
1.60 BSC
0.95 BSC
0.45
E1
e
L
0.30
0.60
L1
0.60 REF
PIN #1 IDENTIFICATION
L2
θ
0.25 REF
4°
TOP VIEW
0°
5°
5°
8°
15°
15°
θ1
10°
θ2
10°
θ1
A2
A
θ
b
L1
L
θ2
c
A1
L2
SIDE VIEW
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-178.
http://onsemi.com
14
CAT93C66, CAT93W66
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ−01
ISSUE O
b
D
e
A
L
DAP SIZE 1.8 x 1.8
E2
E
PIN #1
IDENTIFICATION
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.45
0.00
NOM
MAX
A
A1
A3
b
0.50
0.02
0.55
0.05
0.127 REF
0.25
A3
A
DETAIL A
0.065 REF
0.20
1.95
1.35
2.95
1.25
0.30
2.05
1.45
3.05
1.35
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 REF
0.30
L
0.25
0.35
0.065 REF
Copper Exposed
A3 0.0 - 0.05
DETAIL A
Notes:
(1) ꢀAll dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
http://onsemi.com
15
CAT93C66, CAT93W66
Table 12. ORDERING INFORMATION
Specific
Device
Marking*
Lead
Finish
Device Order Number
Package Type
Temperature Range
Shipping
CAT93C66LI−G
93C66H
PDIP−8
SOIC−8, JEDEC
SOIC−8, JEDEC
SOIC−8, JEDEC
SOIC−8, JEDEC
TDFN−8
I = Industrial
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
NiPdAu
Matte−Tin
NiPdAu
NiPdAu
Tube, 50 Units / Tube
(−40°C to +85°C)
CAT93C66VE−G
93C66H
93C66H
93C66H
93C66H
M2T
E = Extended
(−40°C to +125°C)
Tube, 100 Units / Tube
CAT93C66VE−GT3
CAT93C66VI−G
E = Extended
(−40°C to +125°C)
Tape & Reel,
3,000 Units / Reel
I = Industrial
(−40°C to +85°C)
Tube, 100 Units / Tube
CAT93C66VI−GT3
CAT93C66VP2E−GT3
CAT93C66VP2I−GT3
CAT93C66YI−G
I = Industrial
(−40°C to +85°C)
Tape & Reel,
3,000 Units / Reel
E = Extended
(−40°C to +125°C)
Tape & Reel,
3,000 Units / Reel
M2T
TDFN−8
I = Industrial
(−40°C to +85°C)
Tape & Reel,
3,000 Units / Reel
M66
TSSOP−8
I = Industrial
(−40°C to +85°C)
Tube, 100 Units / Tube
CAT93C66YI−GT3
CAT93C66YE−GT3
CAT93W66VP2I−GT3
CAT93C66XI−T2
M66
TSSOP−8
I = Industrial
(−40°C to +85°C)
Tape & Reel,
3,000 Units / Reel
M66
TSSOP−8
E = Extended
(−40°C to +125°C)
Tape & Reel,
3,000 Units / Reel
M2C
TDFN−8
I = Industrial
(−40°C to +85°C)
Tape & Reel,
3,000 Units / Reel
93C66H
M2U
SOIC−8, EIAJ
UDFN−8
E = Extended
(−40°C to +125°C)
Tape & Reel,
2,000 Units / Reel
CAT93C66HU4I−GT3
CAT93C66HU4E−GT3
I = Industrial
(−40°C to +85°C)
Tape & Reel,
3,000 Units / Reel
M2U
UDFN−8
E = Extended
(−40°C to +125°C)
Tape & Reel,
3,000 Units / Reel
* Marking for New Product (Rev H)
12.All packages are RoHS−compliant (Lead−free, Halogen−free).
13.The standard lead finish is NiPdAu.
14.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
15.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
16.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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For additional information, please contact your local
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CAT93C66/D
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