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CAT5419B-00 [ONSEMI]

DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PBGA24, BGA-24;
CAT5419B-00
型号： CAT5419B-00
厂家： ONSEMI    ONSEMI
描述：

DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PBGA24, BGA-24
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CAT5419  
Dual Digital  
Potentiometer (POT)  
with 64 Taps  
and 2‐wire Interface  
Description  
http://onsemi.com  
The CAT5419 is two digital POTs integrated with control logic and  
16 bytes of NVRAM memory.  
A separate 6-bit control register (WCR) independently controls the  
wiper tap position for each digital POT. Associated with each wiper  
control register are four 6-bit non-volatile memory data registers (DR)  
used for storing up to four wiper settings. Writing to the wiper control  
register or any of the non-volatile data registers is via a 2-wire serial  
TSSOP24  
Y SUFFIX  
CASE 948AR  
SOIC−24  
W SUFFIX  
CASE 751BK  
2
bus (I C-like). On power-up, the contents of the first data register  
(DR0) for each of the two potentiometers is automatically loaded into  
its respective wiper control registers (WCR).  
The Write Protection (WP) pin protects against inadvertent  
programming of the data register.  
PIN CONNECTIONS  
NC  
NC  
NC  
NC  
V
CC  
1
The CAT5419 can be used as a potentiometer or as a two terminal,  
variable resistor. It is intended for circuit level or system level  
adjustments in a wide variety of applications.  
R
L0  
R
H0  
R
W0  
A
A2  
0
Features  
NC  
WP  
CAT5419  
Two Linear-taper Digital Potentiometers  
A
3
SDA  
64 Resistor Taps per Potentiometer  
SCL  
NC  
NC  
NC  
NC  
A
1
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW  
Potentiometer Control and Memory Access via 2-wire Interface  
R
R
L1  
H1  
2
R
W1  
(I C like)  
GND  
Low Wiper Resistance, Typically 80 W  
Four Non-volatile Wiper Settings for Each Potentiometer  
Recall of Wiper Settings at Power Up  
2.5 to 6.0 Volt Operation  
SOIC−24 (W)  
(Top View)  
SDA  
WP  
1
A
R
R
R
A
2
1
Standby Current less than 1 mA  
R
W0  
R
H0  
R
L0  
L1  
H1  
1,000,000 Nonvolatile WRITE Cycles  
100 Year Nonvolatile Memory Data Retention  
24-lead SOIC and 24-lead TSSOP  
Write Protection for Data Register  
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS  
Compliant  
W1  
GND  
NC  
NC  
NC  
NC  
V
CC  
CAT5419  
NC  
NC  
NC  
NC  
SCL  
A
0
A
3
NC  
TSSOP24 (Y)  
(Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 13 of this data sheet.  
Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
July, 2013 − Rev. 11  
CAT5419/D  
CAT5419  
R
R
H1  
H0  
WIPER  
SCL  
SDA  
2−WIRE BUS  
INTERFACE  
CONTROL  
REGISTERS  
R
R
W0  
W1  
WP  
A0  
A1  
A2  
A3  
NONVOLATILE  
DATA  
REGISTERS  
CONTROL  
LOGIC  
R
R
L1  
L0  
Figure 1. Functional Diagram  
PIN DESCRIPTIONS  
SCL: Serial Clock  
The CAT5419 serial clock input pin is used to clock all  
data transfers into or out of the device.  
Table 1. PIN CONNECTIONS  
Pin  
Pin  
SOIC  
TSSOP  
Name  
Function  
Supply Voltage  
1
2
19  
20  
V
SDA: Serial Data  
CC  
The CAT5419 bidirectional serial data pin is used to  
transfer data into and out of the device. The SDA pin is an  
open drain output and can be wire-OR’d with the other open  
drain or open collector outputs.  
R
Low Reference Terminal  
for Potentiometer 0  
L0  
H0  
W0  
3
4
21  
22  
R
High Reference Terminal  
for Potentiometer 0  
R
Wiper Terminal for  
Potentiometer 0  
A0, A1, A2, A3: Device Address Inputs  
These inputs set the device address when addressing  
multiple devices. A total of sixteen devices can be addressed  
on a single bus. A match in the slave address must be made  
with the address input in order to initiate communication  
with the CAT5419.  
5
6
7
8
9
23  
24  
1
A2  
Device Address  
WP  
SDA  
A1  
Write Protection  
Serial Data Input/Output  
Device Address  
2
3
R
Low Reference Terminal  
for Potentiometer 1  
L1  
H1  
W1  
RH, RL: Resistor End Points  
The R and R pins are equivalent to the terminal  
H
L
10  
11  
4
5
R
High Reference Terminal  
for Potentiometer 1  
connections on a mechanical potentiometer.  
R
Wiper Terminal for  
Potentiometer 1  
RW: Wiper  
The R pins are equivalent to the wiper terminal of a  
W
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
6
GND  
NC  
NC  
NC  
NC  
SCL  
A3  
Ground  
mechanical potentiometer.  
7
No Connect  
No Connect  
No Connect  
No Connect  
Bus Serial Clock  
Device Address  
No Connect  
Device Address, LSB  
No Connect  
No Connect  
No Connect  
No Connect  
WP: Write Protect Input  
8
The WP pin when tied low prevents non-volatile writes to  
the data registers (change of wiper control register is  
allowed) and when tied high or left floating normal  
read/write operations are allowed. See page 8, Write  
Protection for more details.  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
NC  
A0  
NC  
NC  
NC  
NC  
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2
CAT5419  
DEVICE OPERATION  
The CAT5419 is two resistor arrays integrated with 2wire  
point for each potentiometer is connected to its wiper  
terminal at a time and is determined by the value of the wiper  
control register. Data can be read or written to the wiper  
control registers or the non-volatile memory data registers  
via the 2-wire bus. Additional instructions allow data to be  
transferred between the wiper control registers and each  
respective potentiometer’s non-volatile data registers. Also,  
the device can be instructed to operate in an  
“increment/decrement” mode.  
serial interface logic, four 6-bit wiper control registers and  
sixteen 6-bit, non-volatile memory data registers. Each  
resistor array contains 63 separate resistive elements  
connected in series. The physical ends of each array are  
equivalent to the fixed terminals of a mechanical  
potentiometer (R and R ). R and R are symmetrical and  
H
L
H
L
may be interchanged. The tap positions between and at the  
ends of the series resistors are connected to the output wiper  
terminals (R ) by a CMOS transistor switch. Only one tap  
W
Table 2. ABSOLUTE MAXIMUM RATINGS  
Parameters  
Ratings  
Units  
C  
C  
V
Temperature Under Bias  
−55 to +125  
−65 to +150  
Storage Temperature Range  
Voltage to any Pins with Respect to V (Notes 1, 2)  
−2.0 to V +2.0  
SS  
CC  
V
with Respect to GND  
−2.0 to +7.0  
1.0  
V
CC  
Package Power Dissipation Capability (T = 25C)  
W
A
Lead Soldering Temperature (10 s)  
Wiper Current  
300  
C  
mA  
12  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC  
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.  
CC  
CC  
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V + 1 V.  
CC  
Table 3. RECOMMENDED OPERATING CONDITIONS  
Parameters  
Ratings  
+2.5 to 6.0  
−40 to +85  
Units  
V
V
CC  
Industrial Temperature  
C  
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3
 
CAT5419  
Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
100  
50  
Max  
Units  
kW  
kW  
kW  
kW  
%
R
R
R
R
Potentiometer Resistance (−00)  
Potentiometer Resistance (−50)  
Potentiometer Resistance (−10)  
Potentiometer Resistance (−25)  
Potentiometer Resistance Tolerance  
POT  
POT  
POT  
POT  
10  
2.5  
20  
1
R
Matching  
%
POT  
Power Rating  
25C, each pot  
50  
mW  
mA  
W
I
W
Wiper Current  
6  
R
Wiper Resistance  
Wiper Resistance  
I
I
= 3 mA @ V = 3 V  
300  
150  
W
W
W
CC  
R
= 3 mA @ V = 5 V  
80  
W
W
CC  
V
TERM  
Voltage on any R or R Pin  
V
SS  
= 0 V  
GND  
V
CC  
V
H
L
V
N
Noise  
(Note 3)  
TBD  
1.6  
nV/Hz  
%
Resolution  
Absolute Linearity (Note 4)  
Relative Linearity (Note 5)  
Temperature Coefficient of R  
R
−R  
1  
LSB  
W(n)(actual)  
(n)(expected)  
(Note 7)  
(Note 6)  
R
W(n+1)  
−[R ]  
W(n)+LSB  
0.2  
LSB  
(Note 6)  
(Note 7)  
(Note 3)  
(Note 3)  
(Note 3)  
TC  
300  
ppm/C  
ppm/C  
pF  
RPOT  
POT  
TC  
Ratiometric Temp. Coefficient  
Potentiometer Capacitances  
Frequency Response  
20  
RATIO  
C /C /C  
H
10/10/25  
0.4  
L
W
fc  
R
= 50 kW (Note 3)  
MHz  
POT  
3. This parameter is tested initially and after a design or process change that affects the parameter.  
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a  
potentiometer.  
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.  
It is a measure of the error in step size.  
6. LSB = R  
/ 63 or (R − R ) / 63, single pot  
TOT  
H L  
7. n = 0, 1, 2, ..., 63  
Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)  
Symbol  
Parameter  
Power Supply Current  
Test Conditions  
= 400 kHz  
Min  
Max  
1
Units  
mA  
mA  
mA  
mA  
V
I
f
SCL  
CC  
I
SB  
Standby Current (V = 5 V)  
V
IN  
= GND or V ; SDA Open  
1
CC  
CC  
I
LI  
Input Leakage Current  
Output Leakage Current  
Input Low Voltage  
V
IN  
= GND to V  
CC  
10  
10  
I
LO  
V
= GND to V  
CC  
OUT  
V
IL  
−1  
V
x 0.3  
CC  
CC  
V
IH  
Input High Voltage  
V
x 0.7  
V
+ 1.0  
V
CC  
V
OL1  
Output Low Voltage (V = 3 V)  
I
OL  
= 3 mA  
0.4  
V
CC  
Table 6. PIN CAPACITANCE (Note 8)  
(Applicable over recommended operating range from T = 25C, f = 1.0 MHz, V = +5.0 V (unless otherwise noted).)  
A
CC  
Symbol  
Test Conditions  
Output Capacitance (SDA)  
Input Capacitance (A0, A1, A2, A3, SCL, WP)  
Min  
Typ  
Max  
8
Units  
pF  
Conditions  
= 0 V  
C
V
I/O  
I/O  
C
6
pF  
V
IN  
= 0 V  
IN  
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CAT5419  
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)  
Symbol  
Parameter  
Min  
Typ  
Max  
400  
50  
Units  
kHz  
ns  
f
Clock Frequency  
SCL  
T (Note 8)  
I
Noise Suppression Time Constant at SCL, SDA Inputs  
SLC Low to SDA Data Out and ACK Out  
Time the bus must be free before a new transmission can start  
Start Condition Hold Time  
t
AA  
0.9  
ms  
t
(Note 8)  
1.2  
0.6  
1.2  
0.6  
0.6  
0
ms  
BUF  
t
ms  
HD:STA  
t
Clock Low Period  
ms  
LOW  
t
Clock High Period  
ms  
HIGH  
t
Start Condition Setup Time (for a Repeated Start Condition)  
Data in Hold Time  
ms  
SU:STA  
HD:DAT  
t
ns  
t
Data in Setup Time  
100  
ns  
SU:DAT  
t
R
(Note 8)  
SDA and SCL Rise Time  
0.3  
ms  
t (Note 8)  
F
SDA and SCL Fall Time  
300  
ns  
t
Stop Condition Setup Time  
0.6  
50  
ms  
SU:STO  
t
Data Out Hold Time  
ns  
DH  
Table 8. POWER UP TIMING (Note 8) (Over recommended operating conditions unless otherwise stated.)  
Symbol Parameter Min Typ  
Power-up to Read Operation  
Power-up to Write Operation  
Max  
1
Units  
ms  
t
PUR  
t
1
ms  
PUW  
8. This parameter is tested initially and after a design or process change that affects the parameter.  
Table 9. WRITE CYCLES LIMITS (Note 9)  
Symbol  
Parameter  
Max  
Units  
t
Write Cycle Time  
5
ms  
WR  
9. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write  
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.  
Table 10. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)  
Symbol  
(Note 10)  
Parameter  
Endurance  
Reference Test Method  
MIL−STD−883, Test Method 1033  
MIL−STD−883, Test Method 1008  
MIL−STD−883, Test Method 3015  
JEDEC Standard 17  
Min  
1,000,000  
100  
Typ  
Max  
Units  
Cycles/Byte  
Years  
N
END  
T
(Note 10)  
(Note 10)  
Data Retention  
ESD Susceptibility  
Latch-up  
DR  
V
2,000  
100  
Volts  
ZAP  
I
(Notes 10, 11)  
mA  
LTH  
10.This parameter is tested initially and after a design or process change that affects the parameter.  
11. t  
and t  
are the delays required from the time V is stable until the specified operation can be initiated.  
PUR  
PUW  
CC  
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CAT5419  
t
F
t
HIGH  
t
R
t
t
LOW  
LOW  
SCL  
t
t
HD:DAT  
SU:STA  
t
t
t
SU:STO  
SU:DAT  
HD:STA  
SDA IN  
t
BUF  
t
t
AA  
DH  
SDA OUT  
Figure 2. Bus Timing  
SCL  
SDA  
8TH BIT  
BYTE n  
ACK  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
Figure 3. Write Cycle Timing  
SDA  
SCL  
START BIT  
STOP BIT  
Figure 4. Start/Stop Timing  
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6
CAT5419  
SERIAL BUS PROTOCOL  
The following defines the features of the 2-wire bus  
protocol:  
1. Data transfer may be initiated only when the bus is  
Therefore, the CAT5419 will be considered a slave device  
in all applications.  
START Condition  
not busy.  
The START Condition precedes all commands to the  
device, and is defined as a HIGH to LOW transition of SDA  
when SCL is HIGH. The CAT5419 monitors the SDA and  
SCL lines and will not respond until this condition is met.  
2. During a data transfer, the data line must remain  
stable whenever the clock line is high. Any  
changes in the data line while the clock is high  
will be interpreted as a START or STOP condition.  
STOP Condition  
The device controlling the transfer is a master, typically a  
processor or controller, and the device being controlled is the  
slave. The master will always initiate data transfers and  
provide the clock for both transmit and receive operations.  
A LOW to HIGH transition of SDA when SCL is HIGH  
determines the STOP condition. All operations must end  
with a STOP condition.  
DEVICE ADDRESSING  
Acknowledge  
The bus Master begins a transmission by sending a  
START condition. The Master then sends the address of the  
particular slave device it is requesting. The four most  
significant bits of the 8-bit slave address are fixed as 0101  
for the CAT5419 (see Figure 5). The next four significant  
bits (A3, A2, A1, A0) are the device address bits and define  
which device the Master is accessing. Up to sixteen devices  
may be individually addressed by the system. Typically,  
+5 V and ground are hard-wired to these pins to establish the  
device’s address.  
After a successful data transfer, each receiving device is  
required to generate an acknowledge. The Acknowledging  
device pulls down the SDA line during the ninth clock cycle,  
signaling that it received the 8 bits of data.  
The CAT5419 responds with an acknowledge after  
receiving a START condition and its slave address. If the  
device has been selected along with a write operation, it  
responds with an acknowledge after receiving each 8-bit  
byte.  
When the CAT5419 is in a READ mode it transmits 8 bits  
of data, releases the SDA line, and monitors the line for an  
acknowledge. Once it receives this acknowledge, the  
CAT5419 will continue to transmit data. If no acknowledge  
is sent by the Master, the device terminates data transmission  
and waits for a STOP condition.  
After the Master sends a START condition and the slave  
address byte, the CAT5419 monitors the bus and responds  
with an acknowledge (on the SDA line) when its address  
matches the transmitted slave address.  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
START  
ACKNOWLEDGE  
Figure 5. Acknowledge Timing  
Write Operations  
from the Slave, the Master device transmits the data to be  
written into the selected register. The CAT5419  
acknowledges once more and the Master generates the  
STOP condition, at which time if a nonvolatile data register  
is being selected, the device begins an internal programming  
cycle to non-volatile memory. While this internal cycle is in  
progress, the device will not respond to any request from the  
Master device.  
In the Write mode, the Master device sends the START  
condition and the slave address information to the Slave  
device. After the Slave generates an acknowledge, the  
Master sends the instruction byte that defines the requested  
operation of CAT5419. The instruction byte consist of a  
four-bit opcode followed by two register selection bits and  
two pot selection bits. After receiving another acknowledge  
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CAT5419  
Acknowledge Polling  
Write Protection  
The disabling of the inputs can be used to take advantage  
of the typical write cycle time. Once the stop condition is  
issued to indicate the end of the host’s write operation, the  
CAT5419 initiates the internal write cycle. ACK polling can  
be initiated immediately. This involves issuing the start  
condition followed by the slave address. If the CAT5419 is  
still busy with the write operation, no ACK will be returned.  
If the CAT5419 has completed the write operation, an ACK  
will be returned and the host can then proceed with the next  
instruction operation.  
The Write Protection feature allows the user to protect  
against inadvertent programming of the non-volatile data  
registers. If the WP pin is tied to LOW, the data registers are  
protected and become read only. Similarly, WP pin going  
LOW after Start will interrupt non-volatile write to data  
registers, while WP pin going LOW after internal write  
cycle has started will have no effect on any write operation.  
The CAT5419 will accept both slave addresses and  
instructions, but the data registers are protected from  
programming by the device’s failure to send an  
acknowledge after data is received.  
CAT5419  
0
1
0
1
A3  
A2  
A1  
A0  
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.  
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.  
Figure 6. Slave Address Bits  
INSTRUCTION  
BYTE  
S
T
A
R
T
SLAVE  
S
T
O
P
ADDRESS  
BUS ACTIVITY:  
MASTER  
Fixed Variable  
DR1 WCR DATA  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Write Timing  
INSTRUCTIONS AND REGISTER DESCRIPTION  
Instruction Byte  
Instructions  
The next byte sent to the CAT5419 contains the  
instruction and register pointer information. The four most  
significant bits used provide the instruction opcode I [3:0].  
The R1 and R0 bits point to one of the four data registers of  
each associated potentiometer. The least two significant bits  
point to one of two Wiper Control Registers. The format is  
shown in Figure 9.  
Slave Address Byte  
The first byte sent to the CAT5419 from the master/  
processor is called the Slave Address Byte. The most  
significant four bits of the slave address are a device type  
identifier. These bits for the CAT5419 are fixed at 0101[B]  
(refer to Figure 8).  
The next four bits, A3 − A0, are the internal slave address  
and must match the physical device address which is defined  
by the state of the A3 − A0 input pins for the CAT5419 to  
successfully continue the command sequence. Only the  
device which slave address matches the incoming device  
address sent by the master executes the instruction. The A3  
− A0 inputs can be actively driven by CMOS input signals  
Table 11. DATA REGISTER SELECTION  
Data Register Selected  
R1  
0
R0  
0
DR0  
DR1  
DR2  
DR3  
0
1
1
0
or tied to V or V  
.
CC  
SS  
1
1
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CAT5419  
Device Type Identifier  
Slave Address  
ID3  
0
ID2  
1
ID1  
ID0  
A3  
A2  
A1  
A0  
0
1
(LSB)  
(MSB)  
Figure 8. Identification Byte Format  
Data Register  
Selection  
Instruction  
Opcode  
WCR/Pot Selection  
I3  
I2  
I1  
I0  
R1  
R0  
0
P0  
(MSB)  
(LSB)  
Figure 9. Instruction Byte Format  
WIPER CONTROL AND DATA REGISTERS  
Wiper Control Register (WCR)  
Data can also be transferred between any of the four Data  
Registers and the associated Wiper Control Register. Any  
data changes in one of the Data Registers is a non-volatile  
operation and will take a maximum of 5 ms.  
If the application does not require storage of multiple  
settings for the potentiometer, the Data Registers can be used  
as standard memory locations for system parameters or user  
preference data.  
The CAT5419 contains two 6-bit Wiper Control  
Registers, one for each potentiometer. The Wiper Control  
Register output is decoded to select one of 64 switches along  
its resistor array. The contents of the WCR can be altered in  
four ways: it may be written by the host via Write Wiper  
Control Register instruction; it may be written by  
transferring the contents of one of four associated Data  
Registers via the XFR Data Register instruction, it can be  
modified one step at a time by the Increment/Decrement  
instruction (see Instruction section for more details).  
Finally, it is loaded with the content of its data register zero  
(DR0) upon power-up.  
The Wiper Control Register is a volatile register that loses  
its contents when the CAT5419 is powered-down. Although  
the register is automatically loaded with the value in DR0  
upon power-up, this may be different from the value present  
at power-down.  
Instructions  
Four of the nine instructions are three bytes in length.  
These instructions are:  
Read Wiper Control Register – read the current wiper  
position of the selected potentiometer in the WCR  
Write Wiper Control Register – change current wiper  
position in the WCR of the selected potentiometer  
Read Data Register – read the contents of the selected  
Data Register  
Write Data Register – write a new value to the  
selected Data Register.  
Data Registers (DR)  
Each potentiometer has four 6-bit non-volatile Data  
Registers. These can be read or written directly by the host.  
http://onsemi.com  
9
CAT5419  
Table 12. INSTRUCTION SET (Note: 1/0 = data is one or zero)  
Instruction Set  
I3  
I2  
I1  
I0  
R1  
R0  
0
WCR0/ P0  
Instruction  
Operation  
Read Wiper Control  
Register  
1
0
0
1
0
0
0
1/0  
Read the contents of the Wiper Control  
Register pointed to by P0  
Write Wiper Control  
Register  
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
0
0
0
0
0
1/0  
1/0  
1/0  
1/0  
Write new value to the Wiper Control  
Register pointed to by P0  
Read Data Register  
1/0  
1/0  
1/0  
1/0  
1/0  
1/0  
Read the contents of the Data Register  
pointed to by P0 and R1−R0  
Write Data Register  
Write new value to the Data Register  
pointed to by P0 and R1−R0  
XFR Data Register to  
Wiper Control Register  
Transfer the contents of the Data  
Register pointed to by P0 and R1−R0 to  
its associated Wiper Control Register  
XFR Wiper Control  
1
0
1
0
1
0
0
1
1/0  
1/0  
1/0  
1/0  
0
0
1/0  
0
Transfer the contents of the Wiper  
Control Register pointed to by P0 to the  
Data Register pointed to by R1−R0  
Register to Data Register  
Gang XFR Data Registers  
to Wiper Control Registers  
Transfer the contents of the Data  
Registers pointed to by R1−R0 of both  
pots to their respective Wiper Control  
Registers  
Gang XFR Wiper Control  
Registers to Data Register  
1
0
0
0
0
1
0
0
1/0  
0
1/0  
0
0
0
0
Transfer the contents of both Wiper  
Control Registers to their respective data  
Registers pointed to by R1−R0 of both  
four pots  
Increment/Decrement  
Wiper Control Register  
1/0  
Enable Increment/decrement of the  
Control Latch pointed to by P0  
The basic sequence of the three byte instructions is  
illustrated in Figure 11. These three-byte instructions  
exchange data between the WCR and one of the Data  
Registers. The WCR controls the position of the wiper. The  
Global XFR Data Register to Wiper Control  
Register  
This transfers the contents of all specified Data Registers  
to the associated Wiper Control Registers.  
Global XFR Wiper Counter Register to Data  
Register  
response of the wiper to this action will be delayed by t  
.
WRL  
A transfer from the WCR (current wiper position), to a Data  
Register is a write to non-volatile memory and takes a  
This transfers the contents of all Wiper Control Registers  
to the specified associated Data Registers.  
maximum of t  
to complete. The transfer can occur  
WR  
between one of the potentiometers and one of its associated  
registers; or the transfer can occur between all  
potentiometers and one associated register.  
Four instructions require a two-byte sequence to  
complete, as illustrated in Figure 10. These instructions  
transfer data between the host/processor and the CAT5419;  
either between the host and one of the data registers or  
directly between the host and the Wiper Control Register.  
These instructions are:  
Increment/Decrement Command  
The final command is Increment/Decrement (Figure 6  
and 12). The Increment/Decrement command is different  
from the other commands. Once the command is issued and  
the CAT5419 has responded with an acknowledge, the  
master can clock the selected wiper up and/or down in one  
segment steps; thereby providing a fine tuning capability to  
the host. For each SCL clock pulse (t  
) while SDA is  
HIGH  
HIGH, the selected wiper will move one resistor segment  
XFR Data Register to Wiper Control Register  
This transfers the contents of one specified Data  
Register to the associated Wiper Control Register.  
XFR Wiper Control Register to Data Register  
This transfers the contents of the specified Wiper  
Control Register to the specified associated Data  
Register.  
towards the R terminal. Similarly, for each SCL clock  
H
pulse while SDA is LOW, the selected wiper will move one  
resistor segment towards the R terminal.  
L
See Instructions format for more detail.  
http://onsemi.com  
10  
CAT5419  
0
1
0
1
SDA  
ID3 ID2 ID1 ID0  
S
T
A3 A2 A1 A0  
A
C
K
S
T
A
R
T
A
C
K
I3 I2 I1 I0  
0
P0  
R1 R0  
O
P
Internal  
Address  
Instruction  
Opcode  
Device ID  
Register  
Address  
Pot/WCR  
Address  
Figure 10. Two-byte Instruction Sequence  
SDA  
0
1
0
1
S
T
A
R
T
A
ID3 ID2 ID1 ID0  
Device ID  
A
C
K
I3 I2 I1 I0 R1 R0  
0
P0  
D7 D6 D5 D4 D3 D2 D1 D0  
A
C
K
S
T
A3 A2 A1 A0  
C
K
O
P
Internal  
Address  
WCR[7:0]  
or  
Instruction  
Data  
Pot/WCR  
Address  
Opcode  
Register  
Data Register D[7:0]  
Address  
Figure 11. Three-byte Instruction Sequence  
0
1
0
1
SDA  
ID3 ID2 ID1 ID0  
Device ID  
I1  
A3 A2 A1 A0  
I3  
I2  
I0  
A
C
K
R1 R0  
0
P0  
S
A
C
K
I
I
D
E
C
1
S
I
D
E
C
n
T
A
R
T
T
O
P
N
C
1
N
C
2
N
C
n
Internal  
Address  
Instruction  
Opcode  
Pot/WCR  
Address  
Data  
Register  
Address  
Figure 12. Increment/Decrement Instruction Sequence  
INC/DEC  
Command  
Issued  
t
WRID  
SCL  
SDA  
Voltage Out  
R
W
Figure 13. Increment/Decrement Timing Limits  
http://onsemi.com  
11  
CAT5419  
INSTRUCTION FORMAT  
Table 13. READ WIPER CONTROL REGISTER (WCR)  
S
T
A
R
T
DEVICE ADDRESSES  
A3 A2 A1 A0  
A
C
K
INSTRUCTION  
A
C
K
DATA  
A
C
K
S
T
O
P
0
1
0
1
1
0
0
1
0
0
0
0
0
0
P0  
P0  
P0  
P0  
7
0
6
0
5
5
5
5
4
3
2
2
2
2
1
1
1
1
0
0
0
0
Table 14. WRITE WIPER CONTROL REGISTER (WCR)  
S
T
A
R
T
DEVICE ADDRESSES  
A3 A2 A1 A0  
A
C
K
INSTRUCTION  
A
C
K
DATA  
A
C
K
S
T
O
P
0
1
0
1
1
1
1
0
0
1
1
1
0
0
0
0
7
0
6
0
4
3
Table 15. READ DATA REGISTER (DR)  
S
T
A
R
T
DEVICE ADDRESSES  
A3 A2 A1 A0  
A
C
K
INSTRUCTION  
R1 R0  
A
C
K
DATA  
A
C
K
S
T
O
P
0
1
0
1
1
7
0
6
0
4
3
Table 16. WRITE DATA REGISTER (DR)  
S
T
A
R
T
DEVICE ADDRESSES  
A3 A2 A1 A0  
A
C
K
INSTRUCTION  
R1 R0  
A
C
K
DATA  
A
C
K
S
T
O
P
0
1
0
1
0
7
0
6
0
4
3
Table 17. GLOBAL TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)  
S
T
A
R
T
DEVICE ADDRESSES  
A3 A2 A1 A0  
A
C
K
INSTRUCTION  
R1 R0  
A
C
K
S
T
O
P
0
1
0
1
0
0
0
1
0
0
Table 18. GLOBAL TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)  
S
T
A
R
T
DEVICE ADDRESSES  
A3 A2 A1 A0  
A
C
K
INSTRUCTION  
R1 R0  
A
C
K
S
T
O
P
0
1
0
1
1
0
0
0
0
0
Table 19. TRANSFER WIPER CONTROL REGISTER (WCR) TO DATA REGISTER (DR)  
S
T
A
R
T
DEVICE ADDRESSES  
A3 A2 A1 A0  
A
C
K
INSTRUCTION  
R1 R0  
A
C
K
S
T
O
P
0
1
0
1
1
1
1
0
0
P0  
http://onsemi.com  
12  
CAT5419  
Table 20. TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)  
S
T
A
R
T
DEVICE ADDRESSES  
A3 A2 A1 A0  
A
C
K
INSTRUCTION  
R1 R0  
A
C
K
S
T
O
P
0
1
0
1
1
1
0
1
0
P0  
Table 21. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR)  
S
T
A
R
T
DEVICE ADDRESSES  
A3 A2 A1 A0  
A
C
K
INSTRUCTION  
A
C
K
DATA  
S
T
O
P
0
1
0
1
0
0
1
0
0
0
0
P0  
I/D  
I/D  
. . .  
I/D  
I/D  
NOTE: Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.  
Table 22. ORDERING INFORMATION  
†
Orderable Part Number  
CAT5419WI−25−T1  
CAT5419WI−10−T1  
CAT5419WI−50−T1  
CAT5419WI−00−T1  
CAT5419YI−25−T2  
CAT5419YI−10−T2  
CAT5419YI−50−T2  
CAT5419YI−00−T2  
CAT5419WI25  
Resistance (kW)  
Lead Finish  
Package  
Shipping  
2.5  
10  
SOIC−24  
(Pb-Free)  
1,000 / Tape & Reel  
2,000 / Tape & Reel  
31 Units / Tube  
50  
100  
2.5  
10  
TSSOP24  
(Pb-Free)  
50  
100  
2.5  
10  
Matte-Tin  
CAT5419WI10  
SOIC−24  
(Pb-Free)  
CAT5419WI50  
50  
CAT5419WI00  
100  
2.5  
10  
CAT5419YI25  
CAT5419YI10  
TSSOP24  
(Pb-Free)  
62 Units / Tube  
CAT5419YI50  
50  
CAT5419YI00  
100  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
12.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device  
Nomenclature document, TND310/D, available at www.onsemi.com.  
13.All packages are RoHS-compliant (Pb-Free, Halogen Free).  
14.The standard lead finish is Matte-Tin.  
http://onsemi.com  
13  
CAT5419  
PACKAGE DIMENSIONS  
SOIC−24, 300 mils  
CASE 751BK  
ISSUE O  
SYMBOL  
MIN  
NOM  
MAX  
2.65  
0.30  
2.55  
0.51  
0.33  
15.40  
10.51  
7.60  
2.35  
A
A1  
A2  
b
0.10  
2.05  
0.31  
0.20  
15.20  
10.11  
7.34  
E1  
E
c
D
E
E1  
e
1.27 BSC  
h
0.25  
0.40  
0º  
0.75  
1.27  
8º  
L
b
e
θ
PIN#1 IDENTIFICATION  
5º  
15º  
θ1  
TOP VIEW  
h
D
h
q1  
A2  
q
A
q1  
L
c
A1  
SIDE VIEW  
END VIEW  
Notes:  
(1) All dimensions are in millimeters. Angles in degrees.  
(2) Complies with JEDEC MS-013.  
http://onsemi.com  
14  
CAT5419  
PACKAGE DIMENSIONS  
TSSOP24, 4.4x7.8  
CASE 948AR  
ISSUE A  
b
SYMBOL  
MIN  
NOM  
MAX  
A
A1  
A2  
b
1.20  
0.15  
1.05  
0.30  
0.20  
7.90  
6.55  
4.50  
0.05  
0.80  
0.19  
0.09  
7.70  
6.25  
4.30  
c
E1  
E
D
7.80  
6.40  
E
E1  
e
4.40  
0.65 BSC  
0.60  
L
0.50  
0.70  
L1  
1.00 REF  
0º  
8º  
θ
e
TOP VIEW  
D
c
A2  
A
θ1  
L
A1  
L1  
SIDE VIEW  
END VIEW  
Notes:  
(1) All dimensions are in millimeters. Angles in degrees.  
(2) Complies with JEDEC MO-153.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,  
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC  
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any  
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without  
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications  
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC  
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for  
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where  
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and  
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,  
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture  
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PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
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USA/Canada  
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Phone: 421 33 790 2910  
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ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
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CAT5419/D  

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