CAT5259WI-00-TE13_技术文档

CAT5259

Quad Digital

Potentiometer (POT)

with 256 Taps

and I²C Interface

Description

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The CAT5259 is four digital POTs integrated with control logic and

16 bytes of NVRAM memory. Each digital POT consists of a series of

resistive elements connected between two externally accessible end

points. The tap points between each resistive element are connected to

the wiper outputs with CMOS switches. A separate 8-bit control

register (WCR) independently controls the wiper tap switches for each

digital POT. Associated with each wiper control register are four 8-bit

non-volatile memory data registers (DR) used for storing up to four

wiper settings. Writing to the wiper control register or any of the

TSSOP−24

Y SUFFIX

CASE 948AR

SOIC−24

W SUFFIX

CASE 751BK

2

non-volatile data registers is via a I C serial bus. On power-up, the

PIN CONNECTIONS

contents of the first data register (DR0) for each of the four

potentiometers is automatically loaded into its respective wiper

control registers.

A3

NC

A0

1

SCL

The CAT5259 can be used as a potentiometer or as a two terminal,

variable resistor. It is intended for circuit level or system level

adjustments in a wide variety of applications. It is available in the 0C

to 70C commercial and −40C to 85C industrial operating

temperature ranges and offered in a 24-lead SOIC and TSSOP

package.

R

L2

W3

R

H2

H3

R

W2

R

L3

NC

CAT5259

GND

V

CC

R

W1

R

L0

R

H1

H0

Features

R

L1

W0

 Four Linear Taper Digital Potentiometers

 256 Resistor Taps per Potentiometer

 End to End Resistance 50 kW or 100 kW

 Potentiometer Control and Memory Access via I C Interface

 Low Wiper Resistance, Typically 100 W

A1

A2

SDA

WP

SOIC−24 (W)

TSSOP−24 (Y)

(Top View)

2

 Nonvolatile Memory Storage for up to Four Wiper Settings for

Each Potentiometer

ORDERING INFORMATION

 Automatic Recall of Saved Wiper Settings at Power Up

 2.5 to 6.0 V Operation

See detailed ordering and shipping information in the package

dimensions section on page 13 of this data sheet.

 Standby Current less than 1 mA

 1,000,000 Nonvolatile WRITE Cycles

 100 Year Nonvolatile Memory Data Retention

 24-lead SOIC and 24-lead TSSOP Packages

 Industrial Temperature Range

 These Devices are Pb-Free, Halogen Free/BFR Free and are

RoHS Compliant

 Semiconductor Components Industries, LLC, 2013

1

Publication Order Number:

July, 2013 − Rev. 11

CAT5259/D

CAT5259

MARKING DIAGRAMS

(SOIC−24)

(TSSOP−24)

L3B

CAT5259WT

−RRYMXXXX

RLB

CAT5259YT

3YMXXX

L = Assembly Location

R = Resistance

4 = 50 KW

5 = 100 KW

L = Assembly Location

B = Product Revision (Fixed as “B”)

CAT5259Y = Device Code

3 = Lead Finish − Matte-Tin

B = Product Revision (Fixed as “B”)

CAT5259W = Device Code

T = Temperature Range (I = Industrial)

− = Dash

RR = Resistance

T = Temperature Range (I = Industrial)

3 = Lead Finish − Matte-Tin

50 = 50 KW

00 = 100 KW

Y = Production Year (Last Digit)

M = Production Month (1−9, O, N, D)

XXX = Last Three Digits of Assembly Lot Number

Y = Production Year (Last Digit)

M = Production Month (1−9, O, N, D)

XXXX = Last Four Digits of Assembly Lot Number

R

H3

H0

H1

H2

WIPER

SCL

SDA

2

I C BUS

CONTROL

REGISTERS

R

W0

W1

W2

W3

INTERFACE

WP

A

0

A

1

A

2

A

3

NONVOLATILE

DATA

REGISTERS

CONTROL

LOGIC

R

L3

L0

L1

L2

Figure 1. Functional Diagram

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2

CAT5259

PIN DESCRIPTIONS

SCL: Serial Clock

The CAT5259 serial clock input pin is used to clock all

data transfers into or out of the device.

Table 1. PIN DESCRIPTIONS

Pin #

Name

NC

Function

1

2

3

4

No Connect

SDA: Serial Data

A0

Device Address, LSB

The CAT5259 bidirectional serial data pin is used to

transfer data into and out of the device. The SDA pin is an

open drain output and can be wire-Ored with the other open

drain or open collector I/Os.

R

W3

Wiper Terminal for Potentiometer 3

R

High Reference Terminal for

Potentiometer 3

H3

A0, A1, A2, A3: Device Address Inputs

5

6

7

8

9

R

Low Reference Terminal for Potentiometer 3

No Connect

L3

These inputs set the device address when addressing

multiple devices. A total of sixteen devices can be addressed

on a single bus. A match in the slave address must be made

with the address input in order to initiate communication

with the CAT5259.

NC

V

CC

Supply Voltage

R

Low Reference Terminal for Potentiometer 0

L0

R

High Reference Terminal for

Potentiometer 0

H0

R , R : Resistor End Points

H

L

The four sets of R and R pins are equivalent to the

terminal connections on a mechanical potentiometer.

H

L

10

11

12

13

14

15

16

R

Wiper Terminal for Potentiometer 0

Device Address

W0

A2

R : Wiper

W

WP

SDA

A1

Write Protection

The four R pins are equivalent to the wiper terminal of

W

Serial Data Input/Output

Device Address

a mechanical potentiometer.

WP: Write Protect Input

The WP pin when tied low prevents non-volatile writes to

the device (change of wiper control register is allowed) and

when tied high or left floating normal read/write operations

are allowed. See Write Protection on page 7 for more details.

R

Low Reference Terminal for Potentiometer 1

L1

R

High Reference Terminal for

Potentiometer 1

H1

17

18

19

20

21

R

W1

Wiper Terminal for Potentiometer 1

Ground

GND

NC

No Connect

R

W2

Wiper Terminal for Potentiometer 2

R

High Reference Terminal for

Potentiometer 2

H2

22

23

24

R

Low Reference Terminal for Potentiometer 2

Bus Serial Clock

L2

SCL

A3

Device Address

DEVICE OPERATION

2

The CAT5259 is four resistor arrays integrated with a I C

serial interface logic, four 8-bit wiper control registers and

sixteen 8-bit, non-volatile memory data registers. Each

resistor array contains 255 separate resistive elements

connected in series. The physical ends of each array are

equivalent to the fixed terminals of a mechanical

one tap point for each potentiometer is connected to its wiper

terminal at a time and is determined by the value of the wiper

control register. Data can be read or written to the wiper

control registers or the non-volatile memory data registers

2

via the I C bus. Additional instructions allow data to be

transferred between the wiper control registers and each

respective potentiometer’s non-volatile data registers. Also,

the device can be instructed to operate in an “increment/

decrement” mode.

potentiometer (R and R ). The tap positions between and

H

L

at the ends of the series resistors are connected to the output

wiper terminals (R ) by a CMOS transistor switch. Only

W

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3

CAT5259

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameters

Ratings

Units

C

V

Temperature Under Bias

Storage Temperature

−55 to +125

−65 to +150

Voltage on Any Pin with Respect to V (Notes 1, 2)

−2.0 to +V + 2.0

SS

CC

V

CC

with Respect to Ground

−2.0 to +7.0

V

Package Power Dissipation Capability (T = 25C)

1.0

300

6

W

A

Lead Soldering Temperature (10 s)

Wiper Current

C

mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.

CC

2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V +1 V.

CC

Table 3. RECOMMENDED OPERATING CONDITIONS

Parameters

Ratings

Units

V

CC

+2.5 to +6

Industrial Temperature

−40 to +85

C

Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Min

Typ

100

50

Max

Symbol

Parameter

Test Conditions

Units

kW

%

R

Potentiometer Resistance (100 kW)

Potentiometer Resistance (50 kW)

Potentiometer Resistance Tolerance

POT

20

1

R

Matching

%

POT

Power Rating

25C, each pot

50

mW

mA

W

I

W

Wiper Current

+3

R

Wiper Resistance

I

= 3 mA @ V = 3 V

200

100

300

150

W

CC

R

= 3 mA @ V = 5 V

W

CC

V

TERM

Voltage on any R or R Pin

V

SS

= 0 V

V

SS

V

CC

V

H

L

V

N

Noise

(Note 3)

nVHz

%

Resolution

0.4

Absolute Linearity (Note 4)

Relative Linearity (Note 5)

Temperature Coefficient of R

R

−R

1

LSB

W(n)(actual)

(n)(expected)

(Note 7)

(Note 6)

R

W(n+1)

−[R ]

W(n)+LSB

0.2

LSB

(Note 6)

(Note 7)

(Note 3)

TC

300

ppm/C

pF

RPOT

POT

TC

Ratiometric Temp. Coefficient

Potentiometer Capacitances

Frequency Response

20

RATIO

C /C /C

H

10/10/25

0.4

L

W

fc

R

= 50 kW (Note 3)

MHz

POT

3. This parameter is tested initially and after a design or process change that affects the parameter.

4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.

It is a measure of the error in step size.

6. LSB = R

/ 255 or (R − R ) / 255, single pot

TOT

H L

7. n = 0, 1, 2, ..., 255

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CAT5259

Table 5. D.C. OPERATING CHARACTERISTICS (V = +2.5 V to +6.0 V, unless otherwise specified.)

CC

Symbol

Parameter

Test Conditions

Min

Max

Units

I

Power Supply Current

f

V

= 400 kHz, SDA = Open

= 6 V, Inputs = GND

1

mA

CC1

CC2

SCL

CC

I

Power Supply Current

Non-volatile WRITE

f

= 400 kHz, SDA Open

= 6 V, Input = GND

5

mA

SCK

V

CC

I

Standby Current (V = 5 V)

= GND or V , SDA = Open

5

mA

V

SB

CC

IN

CC

I

LI

Input Leakage Current

Output Leakage Current

Input Low Voltage

= GND to V

CC

10

IN

I

= GND to V

CC

LO

OUT

V

IL

−1

V

x 0.3

CC

V

Input High Voltage

V

x 0.7

V

+ 1.0

V

IH

CC

V

OL1

Output Low Voltage (V = 3 V)

I = 3 mA

OL

0.4

V

CC

Table 6. CAPACITANCE (T = 25C, f = 1.0 MHz, V = 5 V)

A

CC

Symbol

(Note 8)

Test

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, A2, A3, SCL, WP)

Conditions

Max

8

Units

pF

C

V

I/O

= 0 V

I/O

(Note 8)

V

IN

6

pF

IN

Table 7. A.C. CHARACTERISTICS

2.5 V − 6.0 V

Min

Max

Symbol

Parameter

Units

kHz

ns

f

Clock Frequency

400

200

1

SCL

T (Note 8)

I

Noise Suppression Time Constant at SCL, SDA Inputs

SLC Low to SDA Data Out and ACK Out

t

AA

ms

t

(Note 8)

Time the bus must be free before a new transmission can start

Start Condition Hold Time

1.2

0.6

1.2

0.6

0

ms

BUF

t

ms

HD:STA

t

Clock Low Period

ms

LOW

t

Clock High Period

ms

HIGH

t

Start Condition SetupTime (for a Repeated Start Condition)

Data in Hold Time

ms

SU:STA

HD:DAT

t

ns

t

Data in Setup Time

50

ns

SU:DAT

t

R

(Note 8)

SDA and SCL Rise Time

0.3

ms

t (Note 8)

F

SDA and SCL Fall Time

300

ns

t

Stop Condition Setup Time

Data Out Hold Time

0.6

ms

SU:STO

t

100

ns

DH

Table 8. POWER UP TIMING (Notes 8, 9)

Symbol

Parameter

Max

1

Units

ms

t

Power-up to Read Operation

Power-up to Write Operation

PUR

t

1

ms

PUW

8. This parameter is tested initially and after a design or process change that affects the parameter.

9. t_PURand t_PUWare delays required from the time V is stable until the specified operation can be initiated.

CC

Table 9. WIPER TIMING

Symbol

Parameter

Wiper Response Time After Power Supply Stable

Wiper Response Time After Instruction Issued

Min

5

Max

10

Units

ms

t

WRPO

t

5

10

ms

WRL

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CAT5259

Table 10. WRITE CYCLE LIMITS (Note 10)

Symbol

Parameter

Max

Units

t

Write Cycle Time

5

ms

WR

Table 11. RELIABILITY CHARACTERISTICS

Symbol

(Note 11)

Parameter

Endurance

Reference Test Method

MIL−STD−883, Test Method 1033

MIL−STD−883, Test Method 1008

MIL−STD−883, Test Method 3015

JEDEC Standard 17

Min

1,000,000

100

Max

Units

N

Cycles/Byte

END

T

(Note 11)

Data Retention

ESD Susceptibility

Latch-up

Years

V

DR

ZAP

LTH

V

2000

I

100

mA

10.The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write

cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

11. This parameter is tested initially and after a design or process change that affects the parameter.

t

F

t

HIGH

t

R

t

LOW

SCL

t

HD:DAT

SU:STA

t

SU:STO

t

SU:DAT

HD:STA

SDA IN

t

BUF

t

AA

t

DH

SDA OUT

Figure 2. Bus Timing

SERIAL BUS PROTOCOL

2

The following defines the features of the I C bus protocol:

1. Data transfer may be initiated only when the bus is

not busy.

Therefore, the CAT5259 will be considered a slave device

in all applications.

START Condition

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high

will be interpreted as a START or STOP condition.

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The CAT5259 monitors the SDA and

SCL lines and will not respond until this condition is met.

The device controlling the transfer is a master, typically a

processor or controller, and the device being controlled is the

slave. The master will always initiate data transfers and

provide the clock for both transmit and receive operations.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address of the

particular slave device it is requesting. The four most

significant bits of the 8-bit slave address are fixed as 0101

for the CAT5259 (see Figure 6). The next four significant

bits (A3, A2, A1, A0) are the device address bits and define

which device the Master is accessing. Up to sixteen devices

may be individually addressed by the system. Typically,

+5 V and ground are hard-wired to these pins to establish the

device’s address.

After the Master sends a START condition and the slave

address byte, the CAT5259 monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address.

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CAT5259

Acknowledge

responds with an acknowledge after receiving each 8-bit

byte.

After a successful data transfer, each receiving device is

required to generate an acknowledge. The Acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data.

The CAT5259 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

When the CAT5259 is in a READ mode it transmits 8 bits

of data, releases the SDA line, and monitors the line for an

acknowledge. Once it receives this acknowledge, the

CAT5259 will continue to transmit data. If no acknowledge

is sent by the Master, the device terminates data transmission

and waits for a STOP condition.

WRITE OPERATIONS

In the Write mode, the Master device sends the START

condition and the slave address information to the Slave

device. After the Slave generates an acknowledge, the

Master sends the instruction byte that defines the requested

operation of CAT5259. The instruction byte consist of a

four-bit opcode followed by two register selection bits and

two pot selection bits. After receiving another acknowledge

from the Slave, the Master device transmits the data to be

written into the selected register. The CAT5259

acknowledges once more and the Master generates the

STOP condition, at which time if a non-volatile data register

is being selected, the device begins an internal programming

cycle to non-volatile memory. While this internal cycle is in

progress, the device will not respond to any request from the

Master device.

CAT5259 initiates the internal write cycle. ACK polling can

be initiated immediately. This involves issuing the start

condition followed by the slave address. If the CAT5259 is

still busy with the write operation, no ACK will be returned.

If the CAT5259 has completed the write operation, an ACK

will be returned and the host can then proceed with the next

instruction operation.

Write Protection

The Write Protection feature allows the user to protect

against inadvertent programming of the non-volatile data

registers. If the WP pin is tied to LOW, the data registers are

protected and become read only. Similarly, the WP pin is

going low after start will interrupt non-volatile write to data

registers, while WP pin going low after an internal write

cycle has started will have no effect on any write operation.

The CAT5259 will accept both slave addresses and

instructions, but the data registers are protected from

programming by the device’s failure to send an

acknowledge after data is received.

Acknowledge Polling

The disabling of the inputs can be used to take advantage

of the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write operation, the

SCL

8TH BIT

BYTE n

SDA

ACK

t

WR

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 3. Write Cycle Timing

SDA

SCL

START CONDITION

STOP CONDITION

Figure 4. Start/Stop Condition

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CAT5259

SCL FROM

MASTER

1

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 5. Acknowledge Condition

CAT5259

0

1

0

1

A3

A2

A1

A0

* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

Figure 6. Slave Address Bits

INSTRUCTION AND REGISTER DESCRIPTION

Instruction Byte

Slave Address Byte

The first byte sent to the CAT5259 from the

master/processor is called the Slave Address Byte. The most

significant four bits of the slave address are a device type

identifier. These bits for the CAT5259 are fixed at 0101[B]

(refer to Figure 8).

The next four bits, A3 − A0, are the internal slave address

and must match the physical device address which is defined

by the state of the A3 − A0 input pins for the CAT5259 to

successfully continue the command sequence. Only the

device which slave address matches the incoming device

address sent by the master executes the instruction. The A3

− A0 inputs can be actively driven by CMOS input signals

The next byte sent to the CAT5259 contains the

instruction and register pointer information. The four most

significant bits used provide the instruction opcode I3 − I0.

The R1 and R0 bits point to one of the four data registers of

each associated potentiometer. The least two significant bits

point to one of four Wiper Control Registers. The format is

shown in Figure 9.

Table 12. DATA REGISTER SELECTION

Data Register Selected

R1

0

R0

0

DR0

DR1

DR2

DR3

0

1

or tied to V or V

.

SS

CC

1

0

1

INSTRUCTION

BYTE

S

T

A

R

T

SLAVE

S

T

ADDRESS

BUS ACTIVITY:

MASTER

O

P

Fixed Variable

DR1 WCRDATA

SDA LINE

S

P

ACK

Figure 7. Write Timing

Device Type Identifier

Slave Address

ID3

0

ID2

1

ID1

ID0

A3

A2

A1

A0

0

1

(MSB)

(LSB)

Figure 8. Identification Byte Format

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CAT5259

Instruction

Opcode

Data Register

Selection

WCR/Pot Selection

I3

I2

I1

I0

R1

R0

P1

P0

(MSB)

(LSB)

Figure 9. Instruction Byte Format

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

Data can also be transferred between any of the four Data

Registers and the associated Wiper Control Register. Any

data changes in one of the Data Registers is a non-volatile

operation and will take a maximum of 10 ms.

If the application does not require storage of multiple

settings for the potentiometer, the Data Registers can be used

as standard memory locations for system parameters or user

preference data.

The CAT5259 contains four 8-bit Wiper Control

Registers, one for each potentiometer. The Wiper Control

Register output is decoded to select one of 256 switches

along its resistor array. The contents of the WCR can be

altered in four ways: it may be written by the host via Write

Wiper Control Register instruction; it may be written by

transferring the contents of one of four associated Data

Registers via the XFR Data Register instruction, it can be

modified one step at a time by the Increment/decrement

instruction (see Instruction section for more details).

Finally, it is loaded with the content of its data register zero

(DR0) upon power-up.

The Wiper Control Register is a volatile register that loses

its contents when the CAT5259 is powered-down. Although

the register is automatically loaded with the value in DR0

upon power-up, this may be different from the value present

at power-down.

Instructions

Four of the nine instructions are three bytes in length.

These instructions are:

 Read Wiper Control Register – read the current wiper

position of the selected potentiometer in the WCR

 Write Wiper Control Register – change current wiper

position in the WCR of the selected potentiometer

 Read Data Register – read the contents of the selected

Data Register

 Write Data Register – write a new value to the

selected Data Register

Data Registers (DR)

Each potentiometer has four 8-bit non-volatile Data

Registers. These can be read or written directly by the host.

Table 13. INSTRUCTION SET (Note: 1/0 = data is one or zero.)

Instruction Set

I3 I2 I1 I0 R1

R0 WCR1/P1 WCR0/P0

Instruction

Operation

Read Wiper Control

Register

1

0

1

0

1

0

1

0

1

0

1

0

1/0

Read the contents of the Wiper Control

Register pointed to by P1−P0

Write Wiper Control

Register

0

Write new value to the Wiper Control Register

pointed to by P1−P0

Read Data Register

1/0 1/0

Read the contents of the Data Register pointed

to by P1−P0 and R1−R0

Write Data Register

Write new value to the Data Register pointed to

by P1−P0 and R1−R0

XFR Data Register to

Wiper Control Register

Transfer the contents of the Data Register

pointed to by P1−P0 and R1−R0 to its

associated Wiper Control Register

XFR Wiper Control

Register to Data

Register

1

0

1

0

1

0

1

0

1

0

1

0

1/0 1/0

1/0

0

1/0

0

Transfer the contents of the Wiper Control

Register pointed to by P1−P0 to the Data

Register pointed to by R1−R0

Gang XFR Data

Registers to Wiper

Control Registers

Transfer the contents of the Data Registers

pointed to by R1−R0 of all four pots to their

respective Wiper Control Registers

Gang XFR Wiper Control

Registers to Data

Register

0

Transfer the contents of both Wiper Control

Registers to their respective data Registers

pointed to by R1−R0 of all four pots

Increment/Decrement

Wiper Control Register

0

1/0

Enable Increment/decrement of the Control

Latch pointed to by P1−P0

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CAT5259

The basic sequence of the three byte instructions is

Control Register to the specified associated Data

Register.

 Gang XFR Data Register to Wiper Control Register

This transfers the contents of all specified Data

Registers to the associated Wiper Control Registers.

 Gang XFR Wiper Counter Register to Data Register

This transfers the contents of all Wiper Control

illustrated in Figure 11. These three-byte instructions

exchange data between the WCR and one of the Data

Registers. The WCR controls the position of the wiper. The

response of the wiper to this action will be delayed by t

.

WR

A transfer from the WCR (current wiper position), to a Data

Register is a write to non-volatile memory and takes a

minimum of t

to complete. The transfer can occur

WR

Registers to the specified associated Data Registers.

between one of the four potentiometers and one of its

associated registers; or the transfer can occur between all

potentiometers and one associated register.

Four instructions require a two-byte sequence to

complete, as illustrated in Figure 10. These instructions

transfer data between the host/processor and the CAT5259;

either between the host and one of the data registers or

directly between the host and the Wiper Control Register.

These instructions are:

Increment/Decrement Command

The final command is Increment/Decrement (Figures 12

and 13). The Increment/Decrement command is different

from the other commands. Once the command is issued and

the CAT5259 has responded with an acknowledge, the

master can clock the selected wiper up and/or down in one

segment steps; thereby providing a fine tuning capability to

the host. For each SCL clock pulse (t

) while SDA is

HIGH

HIGH, the selected wiper will move one resistor segment

 XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data

Register to the associated Wiper Control Register.

towards the R terminal. Similarly, for each SCL clock

H

pulse while SDA is LOW, the selected wiper will move one

resistor segment towards the RL terminal.

See Instructions format for more detail.

 XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper

SDA

0

1

0

1

ID3 ID2 ID1 ID0

A

C

K

S

T

O

P

A3 A2 A1 A0

S

T

A

R

T

A

C

K

I3 I2 I1 I0

R1 R0 P1 P0

Internal

Address

Instruction

Opcode

Device ID

Register

Pot/WCR

Address Address

Figure 10. Two-byte Instruction Sequence

0

1

0

1

SDA

S

T

A

R

T

A

C

K

A

C

K

I3 I2 I1 I0 R1 R0 P1 P0

Instruction

D7 D6 D5 D4 D3 D2 D1 D0

A

C

K

S

T

ID3 ID2 ID1 ID0

Device ID

A3 A2 A1 A0

O

P

Internal

Address

WCR[7:0]

or

Pot/WCR

Data

Opcode

Address

Register

Address

Data Register D[7:0]

Figure 11. Three-byte Instruction Sequence

0

1

0

1

SDA

ID3 ID2 ID1 ID0

Device ID

A

C

K

A3 A2 A1 A0

I3 I2 I1 I0

R1 R0 P1 P0

S

T

A

R

T

A

C

K

I

D

E

C

1

S

I

D

N

C

1

N

C

2

T

O

P

N

C

n

E

C

n

Internal

Address

Instruction

Opcode

Pot/WCR

Data

Address

Register

Address

Figure 12. Increment/Decrement Instruction Sequence

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10

CAT5259

INC/DEC

Command

Issued

t

WRID

SCL

SDA

Voltage Out

R

W

Figure 13. Increment/Decrement Timing Limits

INSTRUCTION FORMAT

Table 14. READ WIPER CONTROL REGISTER (WCR)

S

T

A

R

T

DEVICE ADDRESSES

A3 A2 A1 A0

A

C

K

INSTRUCTION

A

C

K

DATA

A

C

K

S

T

O

P

0

1

0

1

0

1

0

P1

P0

7

6

5

4

3

2

1

0

Table 15. WRITE WIPER CONTROL REGISTER (WCR)

S

T

A

R

T

DEVICE ADDRESSES

A3 A2 A1 A0

A

C

K

INSTRUCTION

A

C

K

DATA

A

C

K

S

T

O

P

0

1

0

1

0

1

0

4

3

Table 16. READ DATA REGISTER (DR)

S

T

A

R

T

DEVICE ADDRESSES

A3 A2 A1 A0

A

C

K

INSTRUCTION

R1 R0

A

C

K

DATA

A

C

K

S

T

O

P

0

1

0

1

4

3

Table 17. WRITE DATA REGISTER (DR)

S

T

A

R

T

DEVICE ADDRESSES

A3 A2 A1 A0

A

C

K

INSTRUCTION

R1 R0

A

C

K

DATA

A

C

K

S

T

O

P

0

1

0

1

0

4

3

Table 18. GANG TRANSFER DATA REGISTER (DR)

TO WIPER CONTROL REGISTER (WCR)

S

T

A

R

T

DEVICE ADDRESSES

A3 A2 A1 A0

A

C

K

INSTRUCTION

R1 R0

A

C

K

S

T

O

P

0

1

0

1

0

1

0

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11

CAT5259

Table 19. GANG TRANSFER WIPER CONTROL REGISTER (WCR)

TO DATA REGISTER (DR)

S

T

A

R

T

DEVICE ADDRESSES

A3 A2 A1 A0

A

C

K

INSTRUCTION

R1 R0

A

C

K

S

T

O

P

0

1

0

1

0

Table 20. TRANSFER WIPER CONTROL REGISTER (WCR)

TO DATA REGISTER (DR)

S

T

A

R

T

DEVICE ADDRESSES

A3 A2 A1 A0

A

C

K

INSTRUCTION

R1 R0

A

C

K

S

T

O

P

0

1

0

1

0

P1

P0

Table 21. TRANSFER DATA REGISTER (DR)

TO WIPER CONTROL REGISTER (WCR)

S

T

A

R

T

DEVICE ADDRESSES

A3 A2 A1 A0

A

C

K

INSTRUCTION

R1 R0

A

C

K

S

T

O

P

0

1

0

1

0

1

P1

P0

Table 22. INCREMENT (I)/DECREMENT (D) WIPER CONTROL REGISTER (WCR)

S

T

A

R

T

DEVICE ADDRESSES

A3 A2 A1 A0

A

C

K

INSTRUCTION

A

C

K

DATA

S

T

O

P

0

1

0

1

0

1

0

P1

P0

I/D

. . .

I/D

NOTE: Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.

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12

CAT5259

Table 23. ORDERING INFORMATION

†

Orderable Part Number

CAT5259WI−50−T1

CAT5259WI−00−T1

CAT5259YI−50−T2

CAT5259YI−00−T2

CAT5259WI50

Resistance (kW)

Lead Finish

Package

Shipping

50

100

50

SOIC

(Pb−Free)

1000 / Tape & Reel

2000 / Tape & Reel

31 Units / Tube

TSSOP

(Pb−Free)

100

50

Matte−Tin

SOIC

(Pb−Free)

CAT5259WI00

100

50

CAT5259YI50

TSSOP

(Pb−Free)

62 Units / Tube

CAT5259YI00

100

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

12.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device

Nomenclature document, TND310/D, available at www.onsemi.com.

13.All packages are RoHS-compliant (Lead-Free, Halogen-Free).

14.The standard lead finish is Matte-Tin.

15.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.

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13

CAT5259

PACKAGE DIMENSIONS

SOIC−24, 300 mils

CASE 751BK

ISSUE O

SYMBOL

MIN

NOM

MAX

2.65

0.30

2.55

0.51

0.33

15.40

10.51

7.60

2.35

A

A1

A2

b

0.10

2.05

0.31

0.20

15.20

10.11

7.34

E1

E

c

D

E

E1

e

1.27 BSC

h

0.25

0.40

0º

0.75

1.27

8º

L

b

e

θ

PIN#1 IDENTIFICATION

5º

15º

θ1

TOP VIEW

h

D

h

q1

A2

q

A

q1

L

c

A1

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-013.

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14

CAT5259

PACKAGE DIMENSIONS

TSSOP24, 4.4x7.8

CASE 948AR

ISSUE A

b

SYMBOL

MIN

NOM

MAX

A

A1

A2

b

1.20

0.15

1.05

0.30

0.20

7.90

6.55

4.50

0.05

0.80

0.19

0.09

7.70

6.25

4.30

c

E1

E

D

7.80

6.40

E

E1

e

4.40

0.65 BSC

0.60

L

0.50

0.70

L1

1.00 REF

0º

8º

θ

e

TOP VIEW

D

c

A2

A

θ1

L

A1

L1

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

CAT5259/D

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15


型号：	CAT5259WI-00-TE13
厂家：	ONSEMI
描述：	QUAD 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24, LEAD-FREE, SOIC-24 光电二极管
文件：	总15页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT5259WI-00-TE13 [ONSEMI]

相关型号：

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CAT5259WI-50-TE13

CAT5259WI-50TE13

CAT5259WI00

CAT5259WI50

CAT5259YI-00

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CAT5259YI-00-T2