CAT28F001L-12TT_技术文档

CAT28F001

1 Megabit CMOS Boot Block

Flash Memory

Licensed Intel

second source

FEATURES

■ Deep Powerdown Mode

— 0.05 µA I_CCTypical

■ Fast Read Access Time: 90/120 ns

■ On-Chip Address and Data Latches

■ Blocked Architecture

— 0.8 µA I_PPTypical

■ Hardware Data Protection

■ Electronic Signature

— One 8 KB Boot Block w/ Lock Out

• Top or Bottom Locations

■ 100,000 Program/Erase Cycles and 10 Year

Data Retention

— Two 4 KB Parameter Blocks

— One 112 KB Main Block

■ JEDEC Standard Pinouts:

— 32 pin DIP

■ Low Power CMOS Operation

■ 12.0V ± 5% Programming and Erase Voltage

■ Automated Program & Erase Algorithms

■ High Speed Programming

— 32 pin PLCC

— 32 pin TSOP

■ Reset/Deep Power Down Mode

■ "Green" Package Options Available

■ Commercial, Industrial and Automotive

Temperature Ranges

DESCRIPTION

The CAT28F001 is a high speed 128K X 8 bit electrically

erasable and reprogrammable Flash memory ideally

suited for applications requiring in-system or after sale

code updates.

The CAT28F001 is designed with a signature mode

whichallowstheusertoidentifytheICmanufacturerand

device type. The CAT28F001 is also designed with on-

ChipAddressLatches, DataLatches, Programmingand

Erase Algorithms.

The CAT28F001 has a blocked architecture with one 8

KB Boot Block, two 4 KB Parameter Blocks and one 112

KB Main Block. The Boot Block section can be at the top

orbottomofthememorymapandincludesareprogram-

ming write lock out feature to guarantee data integrity. It

is designed to contain secure code which will bring up

the system minimally and download code to other loca-

tions of CAT28F001.

The CAT28F001 is manufactured using Catalyst’s ad-

vanced CMOS floating gate technology. It is designed

to endure 100,000 program/erase cycles and has a data

retention of 10 years. The device is available in JEDEC

approved 32-pin plastic DIP, PLCC or TSOP packages.

BLOCK DIAGRAM

I/O –I/O

0

7

ADDRESS

COUNTER

I/O BUFFERS

WRITE STATE

MACHINE

ERASE VOLTAGE

SWITCH

STATUS

RP

REGISTER

WE

DATA

LATCH

SENSE

AMP

COMMAND

REGISTER

PROGRAM VOLTAGE

SWITCH

CE, OE LOGIC

CE

OE

Y-GATING

Y-DECODER

A –A

0

16

8K-BYTE BOOT BLOCK

4K-BYTE PARAMETER BLOCK

112K-BYTE MAIN BLOCK

X-DECODER

VOLTAGE VERIFY

SWITCH

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

1

CAT28F001

PIN CONFIGURATION

PLCC Package (N, G)

DIP Package (L)

V

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V

CC

WE

PP

A

2

16

15

12

A

3

RP

4

3 2 1 32 31 30

A

4

A

5

6

7

8

9

29

28

27

26

25

24

23

14

A

7

6

5

4

3

2

1

0

14

13

8

A

5

A

7

6

13

8

6

A

7

5

9

A

9

A

8

4

11

A

11

A

9

OE

3

10

11

12

13

A

OE

A

10

11

12

13

14

15

16

A

2

10

CE

A

10

CE

A

1

₂2_8F2_{001 F02}

A

I/O

0

7

6

5

4

3

21

I/O

7

I/O

0

14 15 16 17 18 19 20

1

2

V

SS

TSOP Package (Standard Pinout) (T, H)

A

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

A

10

CE

11

9

8

A

RP

I/O

13

14

7

6

5

4

3

WE

V

A

CC

PP

16

15

12

9

V

SS

10

11

12

13

14

15

16

I/O

2

1

0

A

0

A

1

A

2

A

3

7

6

5

4

PIN FUNCTIONS

Pin Name

Type

Function

A₀–A₁₆

Input

Address Inputs for

memory addressing

I/O₀–I/O₇

CE

I/O

Data Input/Output

Chip Enable

Output Enable

Write Enable

Voltage Supply

Ground

Input

OE

WE

V_CC

V_SS

V_PP

Program/Erase

Voltage Supply

RP

Input

Power Down

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

2

CAT28F001

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias ................... –55°C to +95°C

Storage Temperature....................... –65°C to +150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

Voltage on Any Pin with

Respect to Ground⁽¹⁾........... –2.0V to +V_CC+ 2.0V

(Except A₉, RP, OE, V_CCand V_PP)

Voltage on Pin A₉, RP AND OE with

Respect to Ground⁽¹⁾................... –2.0V to +13.5V

V

_PPwith Respect to Ground

during Program/Erase⁽¹⁾.............. –2.0V to +14.0V

V_CCwith Respect to Ground⁽¹⁾............ –2.0V to +7.0V

Package Power Dissipation

Capability (T_A= 25°C) .................................. 1.0 W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current⁽²⁾........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Min.

100K

10

Max.

Units

Cycles/Byte

Years

Test Method

(3)

N_END

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(3)

T_DR

Data Retention

ESD Susceptibility

Latch-Up

(3)

V_ZAP

2000

100

Volts

(3)(4)

I_LTH

mA

CAPACITANCE T = 25°C, f = 1.0 MHz

A

Limits

Max.

8

Symbol

Test

Min

Units

pF

Conditions

V_IN= 0V

(3)

C_IN

Input Pin Capacitance

Output Pin Capacitance

V_PPSupply Capacitance

(3)

C_OUT

12

25

pF

V_OUT= 0V

V_PP= 0V

(3)

C_VPP

pF

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.

CC

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

CC

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

3

CAT28F001

D.C. OPERATING CHARACTERISTICS

V

CC

= +5V ±10%, unless otherwise specified

Limits

Max.

±1.0

Symbol

Parameter

Min.

Unit

Test Conditions

V_IN= V_CCor V_SS

I_LI

Input Leakage Current

µA

V_CC= 5.5V

I_LO

Output Leakage Current

±10

µA

V_OUT= V_CCor V_SS

V_CC= 5.5V

,

I_SB1

V_CCStandby Current CMOS

100

CE = V_CC±0.2V = RP

V_CC= 5.5V

I_SB2

I_PPD

I_CC1

V_CCStandby Current TTL

V_PPDeep Powerdown Current

V_CCActive Read Current

1.5

1.0

30

mA

µA

CE = RP = V_IH, V_CC= 5.5V

RP = GND±0.2V

mA

V_CC= 5.5V, CE = V_IL,

I_OUT= 0mA, f = 8 MHz

(1)

I_CC2

V_CCProgramming Current

V_CCErase Current

20

mA

V_CC= 5.5V,

Programming in Progress

(1)

I_CC3

V_CC= 5.5V,

Erase in Progress

I_PPS

I_PP1

V_PPStandby Current

±10

200

µA

V_PP< V_CC

V_PP> V_CC

V_PPRead Current

200

30

µA

V_PP= V_PPH

(1)

I_PP2

V_PPProgramming Current

mA

V_PP= V_PPH

Programming in Progress

V_PP= V_PPH

,

(1)

I_PP3

V_PPErase Current

30

mA

,

Erase in Progress

V_IL

Input Low Level

–0.5

0.8

0.45

V

V_OL

V_IH

Output Low Level

I_OL= 5.8mA, V_CC= 4.5V

Input High Level

2.0

2.4

V_CC+0.5

V

V_OH

V_ID

Output High Level

V

I_OH= 2.5mA, V_CC= 4.5V

A₉= V_ID

A₉Signature Voltage

A₉Signature Current

V_CCDeep Powerdown Current

V_CCErase Suspend Current

V_PPErase Suspend Current

11.5

13.0

500

1.0

V

I_ID

µA

mA

µA

A₉= V_ID

I_CCD

I_CCES

I_PPES

RP = GND±0.2V

10

Erase Suspended CE = V_IH

Erase Suspended V_PP=V_PPH

300

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

4

CAT28F001

SUPPLY CHARACTERISTICS

Symbol

Limits

Parameter

Min

2.5

4.5

0

Max.

Unit

V

V_LKO

V_CC

V_CCErase/Write Lock Voltage

V_CCSupply Voltage

5.5

6.5

V

V_PPL

V_PPH

V_HH

V_PPDuring Read Operations

V_PPDuring Erase/Program

RP, OE Unlock Voltage

V

11.4

12.6

V

A.C. CHARACTERISTICS, Read Operation

V

CC

= +5V ±10%, unless otherwise specified

28F001-90⁽⁷⁾

28F001-12⁽⁷⁾

JEDEC

Standard

Symbol

Symbol Parameter

Min

Max

Min

Max

Units

t_AVAV

t_ELQV

t_AVQV

t_GLQV

-

t_RC

t_CE

Read Cycle Time

90

120

ns

90

35

120

50

ns

CE Access Time

t_ACC

t_OE

t_OH

Address Access Time

OE Access Time

Output Hold from Address OE/CE Change

OE to Output in Low-Z

CE to Output in Low-Z

OE High to Output High-Z

CE High to Output High-Z

RP High to Output Delay

0

(1)(6)

t_GLQX

t_ELQX

t_GHQZ

t_EHQZ

t_PHQV

t_OLZ

(1)(6)

t_LZ

t_DF

t_HZ

(1)(2)

30

35

30

55

t_PWH

600

(3)(4)(5)

Figure 2. Highspeed A.C. Testing Input/Output

Waveform(3)(4)(5)

Figure 1. A.C. Testing Input/Output Waveform

V

- 0.3V

0.0 V

3.0 V

CC

2.0 V

0.8 V

INPUT PULSE LEVELS

REFERENCE POINTS

INPUT PULSE LEVELS

1.5 V

REFERENCE POINTS

0.0 V

Testing Load Circuit (example)

1.3V

1N914

3.3K

DEVICE

UNDER

TEST

DEVICE

UNDER

TEST

OUT

C

= 100 pF

L

C

= 30 pF

L

C

INCLUDES JIG CAPACITANCE

L

C

INCLUDES JIG CAPACITANCE

L

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.

(3) Input Rise and Fall Times (10% to 90%) < 10 ns.

(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.

(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.

(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.

(7) For load and reference points, see Fig. 1

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

5

CAT28F001

A.C. CHARACTERISTICS, Program/Erase Operation

V

CC

= +5V ±10%

28F001-90

28F001-12

JEDEC

Standard

Symbol

Symbol Parameter

Min

Max

Min

Max

Units

t_AVAV

t_WC

t_AS

t_AH

Write Cycle Time

90

120

ns

t_AVWH

t_WHAX

t_DVWH

t_WHDX

Address Setup to WE Going High

40

10

40

10

ns

Address Hold Time from WE Going High

t_DS

t_DH

Data Setup Time to WE Going High

Data Hold Time from WE Going High

40

10

40

10

ns

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_CS

t_CH

t_WP

t_WPH

—

0

ns

µs

CE Setup Time to WE Going Low

CE Hold Time from WE Going High

WE Pulse Width

40

10

0

40

10

0

WE High Pulse Width

t_WHG

L

Write Recovery Time Before Read

(1)

t_PHWL

t_PS

480

100

15

480

100

15

ns

RP High Recovery to WE Going Low

RP V_HHSetup to WE Going High

V_PPSetup to WE Going High

(1)

t_PHHWH

t_VPWH

t_WHQV1

t_PHS

t_VPS

—

(1)

ns

µs

Duration of Programming Operations

t_WHQV2

t_WHQV3

t_WHQV4

t_QVVL

—

Duration of Erase Operations (Boot)

Duration of Erase Operations (Parameter)

Duration of Erase Operations (Main)

V_PPHold from Valid Status Reg Data

RP V_HHHold from Status Reg Data

Boot Block Relock Delay

1.3

3

1.3

3

Sec

ns

—

(1)

t_VPH

0

t_QVPH

t_PHH

—

0

ns

(1)

t_PHBR

100

ns

t_GHHWL

t_WHGH

Note:

—

480

OE V_HHSetup to WE Going Low

OE V_HHHold from WE High

—

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

6

CAT28F001

ERASE AND PROGRAMMING PERFORMANCE

28F001-90

28F001-12

Typ

Parameter

Min

Typ

Max

Min

Max

Units

Boot Block Erase Time

2.10

14.9

2.10

14.9

Sec

Boot Block Program Time

0.15

2.10

0.52

14.6

0.15

2.10

0.52

14.6

Sec

Parameter Block Erase Time

Parameter Block Program Time

Main Block Erase Time

0.07

3.80

0.26

20.9

0.07

3.80

0.26

20.9

Sec

Main Block Program Time

Chip Erase Time

2.10

10.10

2.39

7.34

65

2.10

10.10

2.39

7.34

65

Sec

Chip Program Time

8.38

(1)

FUNCTION TABLE

Pins

WE

Mode

RP

V_IH

CE

V_IL

V_IH

V_IL

OE

V_IL

V_IH

X

V_PP

X

I/O

Notes

Read

V_IH

X

D_OUT

High-Z

31H

Output Disable

Standby

X

Signature (MFG)

Signature (Device)

V_IL

V_IH

X

A₀= V_IL, A₉= 12V

X

94H-28F001T A₀= V_IH, A₉= 12V

95H-28F001B

Write Cycle

V_IH

V_IL

X

V_IH

X

V_IL

X

D_IN

During Write Cycle

Deep Power Down

HIGH-Z

WRITE COMMAND TABLE

Commands are written into the command register in one or two write cycles. Write cycles also internally latch

addresses and data required for programming and erase operations.

First Bus Cycle

Operation Address D_IN

Second Bus Cycle

Mode

Operation Address

D_IN

D_OUT

Read Array/Reset

Write

X

FFH

Program Setup/

Program

A_IN

40H

10H

Write

Read

A_IN

X

D_IN

Read Status Reg.

Clear Status Reg.

Write

X

70H

St. Reg. Data

Write

X

50H

20H

Erase Setup/Erase

Confirm

Block ad

Write

Block ad

X

D0H

Erase Suspend/

Erase Resume

Write

X

B0H

Read Sig (Mfg)

Read Sig (Dev)

Write

X

90H

Read

0000H

0001H

31H

94H-28F001T

95H-28F001B

Note:

(1) Logic Levels: X = Logic ‘Do not care’ (V , V , V

, V )

PPL PPH

IH

IL

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

7

CAT28F001

READ OPERATIONS

Read Mode

applying the required high voltage on address pin A9

while the other address line are held at VIL.

The CAT28F001 memory can be read from any of its

Blocks (Boot Block, Main Block or Parameter Block),

Status Register and Signature Information by sending

the Read Command Mode to the Command Register.

A Read cycle from address 0000H retrieves the binary

code for the IC manufacturer on outputs I/O₇to I/O₀:

CAT28F001 automatically resets to Read Array mode

upon initial device power up or after exit from deep

power down. A Read operation is performed with both

CE and OE low and with RP and OE high. Vpp can be

either high or low. The data retrieved from the I/O pins

reflectsthecontentsofthememorylocationcorrespond-

ing to the state of the 17 address pins. The respective

timing waveforms for the read operation are shown in

Figure 3. Refer to the AC Read characteristics for

specific timing parameters.

Catalyst Code = 0011 0001 (31H)

A Read cycle from address 0001H retrieves the binary

code for the device on outputs I/O₇to I/O₀:

CAT28F001T = 1001 0100 (94H)

CAT28F001B = 1001 0101 (95H)

Standby Mode

With CE at a logic-high level, the CAT28F001 is placed

in a standby mode where most of the device circuitry is

disabled, thereby substantially reducing power con-

sumption. Theoutputsareplacedinahigh-impendance

state independent of the OE status.

Signature Mode

The signature mode allows the user to identify the IC

manufacturerandthetypeofthedevicewhilethedevice

residesinthetargetsystem. Thismodecanbeactivated

in either of two ways; through the conventional method

of applying a high voltage (12V) to address pin A9 or by

sending an instruction to the command register (see

Write Operations).

Deep Power-Down

When RP is at logic-low level, the CAT28F001 is placed

in a Deep Power-Down mode where all the device

circuitry are disabled, thereby reducing the power con-

sumption to 0.25µW.

The conventional method is entered as a regular read

mode by driving the CE and OE low (with WE high), and

Figure 3. A.C. Timing for Read Operation

STANDBY

DEVICE AND

OUPUTS

DATA VALID

STANDBY

POWER DOWN

POWER UP

ADDRESS SELECTION

ENABLED

ADDRESS STABLE

ADDRESSES

CE (E)

t

(t )

AVAV RC

t

EHQZ

OE (G)

t

(t

)

GHQZ DF

t

(t )

GLQV OE

WE (W)

t

(t )

ELQV CE

t

(t

)

t

GLQX OLZ

OH

t

(t

)

ELQX LZ

HIGH-Z

OUTPUT VALID

DATA (I/O)

t

(t

)

AVQV ACC

)

t

(t

PHQV PWH

RP (P)

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

8

CAT28F001

block erasure. During the first write cycle, a Command

20H (Erase Setup) is first written to the Command

Register, followed by the Command D0H (Erase Con-

firm). These commands require both appropriate com-

mand data and an address within Block to be erased.

Also, Block erasure can only occur when VPP= VPPH.

WRITE OPERATIONS

The following operations are initiated by observing the

sequence specified in the Write Command Table.

Read Array

The device can be put into a Read Array Mode by

initiating a write cycle with FFH on the data bus. The

device is also in a standard Read Array Mode after the

initial device power up and when comes out of the Deep

Power-Down mode.

Block preconditioning, erase and verify are all handled

internally by the Write State Machine, invisible to the

system. After receiving the two command erase se-

quence the CAT28F001 automatically outputs Status

Register data when read (Fig.5). The CPU can detect

the completion of the erase event by checking if the

SR.7 of the Status Register is set.

Signature Mode

An alternative method for reading device signature (see

Read Operations Signature Mode), is initiated by writing

the code 90H into the command register. A read cycle

from address 0000H with CE and OE low (and WE high)

will output the device signature.

SR.5 will indicate whether the erase was successful. If

aneraseerrorisdetected, theStatusRegistershouldbe

cleared. The device will be in the Status Register Read

Mode until another command is issued.

ERASE SUSPEND/ERASE RESUME

Catalyst Code = Catalyst Code = 0011 0001 (31H)

The Erase Suspend Command allows erase sequence

interruption in order to read data from another block of

memory. Once the erase sequence is started, writing

the Erase Suspend command (B0H) to the Command

Register requests that the WSM suspend the erase

sequence at a predetermined point in the erase algo-

rithm. The CAT28F001 continues to output Status Reg-

isterdatawhenread,aftertheEraseSuspendcommand

is written to it. Polling the WSM Status and Erase

Suspend Status bits will determine when the erase

operation has been suspended (both will be set to “1s”).

A Read cycle from address 0001H retrieves the

binary code for the device on outputs I/O₇to I/O₀:

CAT28F001T = 1001 0100 (94H)

CAT28F001B = 1001 0101 (95H)

To terminate the operations, it is necessary to write

another valid command into the register.

STATUS REGISTER

The device may now be given a Read ARRAY Com-

mand, which allows any locations 'not within the block

being erased' to be read. Also, you can either perform

a Read Status Register or resume the Erase Operation

by sending Erase Resume (D0H), at which time the

WSM will continue with the erase sequence. The Erase

Suspend Status and WSM Status bits of the Status

Register will be cleared.

The 28F001 contains an 8-bit Status Register. The

Status Register is polled to check for write or erase

completion or any related errors. The Status Register

may be read at any time by issuing a Read Status

Register (70H) command. All subsequent read opera-

tions output data from the Status Register, until another

valid command is issued. The contents of the Status

Register are latched on the falling edge of OE or CE ,

whichever occurs last in the read cycle. OE or CE must

be toggled to VIH before further reads to update the

status register latch.

PROGRAM SETUP/PROGRAM COMMANDS

Programmingisexecutedbyatwo-writesequence. The

program Setup command (40H) is written to the Com-

mand Register, followed by a second write specifying

the address and data (latched on the rising edge of WE)

to be programmed. The WSM then takes over, control-

ling the program and verify algorithms internally. After

the two-command program sequence is written to it, the

CAT28F001 automatically outputs Status Register data

when read (see figure 4; Byte Program Flowchart). The

CPU can detect the completion of the program event by

analyzing the WSM Status bit of the Status Register.

Only the Read Status Register Command is valid while

programming is active.

TheEraseStatus(SR.5)andProgramStatus(SR.4)are

set to 1 by the WSM and can only be reset issuing Clear

Status Register (50H) These two bits can be polled for

failures, thus allowing more flexibility to the designer

when using the CAT28F001. Also, VPP Status (SR.3)

when set to 1 must be reset by system software before

anyfurtherbyteprogramsorblockerasesareattempted.

ERASE SETUP/ERASE CONFIRM

Erase is executed one block at a time, initiated by a two

cycle command sequence. The two cycle command

sequence provides added security against accidental

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

9

CAT28F001

WSMS

7

ESS

6

ES

5

PS

4

VPPS

3

R

2

R

1

R

0

SR.7 = WRITE STATE MACHINE STATUS

1 = Ready

NOTES:

The Write State Machine Status Bit must first be checked to

determine program or erase completion, before the

Program or Erase Status bits are checked for success.

If the Program AND Erase Status bits are set to “1s” during an

erase attempt, an improper command sequence was

entered. Attempt the operation again.

0 = Busy

SR.6 = ERASE SUSPEND STATUS

1 = Erase Suspended

0 = Erase in Progress/Completed

SR.5 = ERASE STATUS

1 = Error in Block Erasure

0 = Successful Block Erase

SR.4 = PROGRAM STATUS

1 = Error in Byte Program

0 = Successful Byte Program

SR.3 = VPP STATUS

If V low status is detected, the Status Register must be

PP

cleared before another program or erase operation is

attempted.

The V Status bit, unlike an A/D converter, does not provide

PP

continuous indication of V level. The WSM interrogates

the V level only after the program or erase command

PP

1 = V Low Detect; Operation Abort

sequences have been entered and informs the system if

PP

0 = V Okay

V

has not been switched on. The V Status bit is not

PP PP

PP

SR.2 -SR.0 = RESERVED FOR FUTURE ENHANCEMENTS

These bits are reserved for future use and should be masked

out when polling the Status Register.

guaranteed to report accurate feedback between V

and

PPL

V

.

PPH

When the Status Register indicates that programming is

complete, the Program Status bit should be checked. If

programerrorisdetected, theStatusRegistershouldbe

cleared. The internal WSM verify only detects errors for

“1s” that do not successfully program to “0s”. The

Command Register remains in Read Status Register

mode until further commands are issued to it.

bits will be set to “1”. When issuing the Erase Setup and

Erase Confirm commands, they should be written to an

address within the address range of the block to be

erased. Figure 5 shows a system software flowchart for

block erase.

The entire sequence is performed with V_PPat V_PPH

.

Abort occurs when RP transitions to V_IL, or V_PPdrops to

V_PPL. Although the WSM is halted, byte data is partially

programmed or Block data is partially erased at the

location where it was aborted. Block erasure or a repeat

of byte programming will initialize this data to a known

value.

If erase/byte program is attempted while V_PP= V_PPL, the

Status bit (SR.5/SR.4) will be set to “1”. Erase/Program

attempts while V_PPL< V_PP< V_PPHproduce spurious

results and should not be attempted.

EMBEDDED ALGORITHMS

The CAT28F001 integrates the Quick Pulse program-

ming algorithm on-chip, using the Command Register,

Status Register and Write State Machine (WSM). On-

chip integration dramatically simplifies system software

and provides processor-like interface timings to the

Command and Status Registers. WSM operation, inter-

nal program verify, and V_PPhigh voltage presence are

monitored and reported via appropriate Status Register

bits. Figure 4 shows a system software flowchart for

device programming.

BOOT BLOCK PROGRAM AND ERASE

The boot block is intended to contain secure code which

will minimally bring up a system and control program-

ming and erase of other blocks of the device, if needed.

Therefore, additional “lockout” protection is provided to

guarantee data integrity. Boot block program and erase

operations are enabled through high voltage V_HHon

either RP or OE, and the normal program and erase

command sequences are used. Reference the AC

Waveforms for Program/Erase.

As above, the Quick Erase algorithm is now imple-

mented internally, including all preconditioning of block

data. WSM operation, erase verify and V_PPhigh voltage

presencearemonitoredandreportedthroughtheStatus

Register. Additionally, if a command other than Erase

Confirm is written to the device after Erase Setup has

been written, both the Erase Status and Program Status

If boot block program or erase is attempted while RP is

at V_IH, either the Program Status or Erase Status bit will

be set to “1”, reflective of the operation being attempted

and indicating boot block lock. Program/erase attempts

while V_IH< RP < V_HHproduce spurious results and

should not be attempted.

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

10

CAT28F001

IN-SYSTEM OPERATION

For on-board programming, the RP pin is the most

convenient means of altering the boot block. Before

issuingProgramorEraseconfirmscommands,RPmust

transitiontoV_HH.HoldRPatthishighvoltagethroughout

the program or erase interval (until after Status Register

confirm of successful completion). At this time, it can

return to V_IHor V_IL.

Figure 4 Byte Programming Flowchart

START

Bus

Operation Command Comments

WRITE 40H,

BYTE ADDRESS

Write

Read

Program

Setup

Data = 40H

Address = Bytes to be Programmed

Program

Data to be programmed

Address = Byte to be Programmed

WRITE BYTE

ADDRESS/DATA

Status Register Data.

Toggle OE or CE to update

Status Register

READ STATUS

REGISTER

Check SR.7

NO

SR.7 = 1?

Standby

1 = Ready, 0 = Busy

Repeat for subsequent bytes.

YES

FULL STATUS

CHECK IF DESIRED

Full Status check can be done after each byte or after a sequence

of bytes.

Write FFH after the last byte programming operation to reset the

device to Read Array Mode.

BYTE PROGRAM

COMPLETED

FULL STATUS CHECK PROCEDURE

STATUS REGISTER DATA

READ (SEE ABOVE)

Bus

Operation Command Comments

Standby

Check SR.3

NO

V

RANGE

PP

ERROR

SR.3 = 0?

1 = V Low Detect

PP

YES

BYTE PROGRAM

ERROR

Standby

Check SR.3

1 = Byte Program Error

SR.4 = 0?

YES

SR.3 MUST be cleared, if set during a program attempt, before

further attempts are allowed by the Write State Machine.

BYTE PROGRAM

SUCCESSFUL

SR.3 is only cleared by the Clear Status Register Command, in

case where multiple bytes are programmed before full status is

checked.

If error is detected, clear the Status Register before attempting retry

or other error recovery.

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

11

CAT28F001

Figure 5 Block Erase Flowchart

START

Bus

Operation Command Comments

WRITE 20H,

BLOCK ADDRESS

Write

Erase

Setup

Data = 20H

Address = Within Block to be erased

WRITE D0H

BLOCK ADDRESS

Write

Read

Erase

Data - D0H

Address = Within Block to be erased

READ STATUS

REGISTER

Status Register Data.

Toggle OE or CE to update

Status Register

ERASE SUSPEND

LOOP

NO

YES

SUSPEND

ERASE?

Standby

Check SR.7

1 = Ready, 0 = Busy

SR.7 = 1?

YES

Repeat for subsequent blocks.

FULL STATUS

CHECK IF DESIRED

Full Status check can be done after each block or after a sequence

of blocks.

Write FFH after the last block erase operation to reset the device to

Read Array Mode.

BLOCK ERASE

COMPLETED

FULL STATUS CHECK PROCEDURE

STATUS REGISTER DATA

READ (SEE ABOVE)

Bus

Operation Command Comments

NO

V RANGE

PP

ERROR

Standby

Check SR.3

SR.3 = 0?

YES

1 = V Low Detect

PP

Standby

Check SR.4

Both 1 = Command Sequence Error

COMMAND SEQUENCE

ERROR

YES

SR.4,5 = 1?

NO

Standby

Check SR.5

1 = Block Erase Error

BLOCK ERASE

ERROR

NO

SR.5 = 0?

SR.3 MUST be cleared, if set during a erase attempt, before further

attempts are allowed by the Write State Machine.

BLOCK ERASE

SUCCESSFUL

SR.3 is only cleared by the Clear Status Register Command, in

cases where multiple blocks are erased before full status is

checked.

If error is detected, clear the Status Register before attempting retry

or other error recovery.

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

12

CAT28F001

Figure 6 Block Erase Suspend/Resume Flowchart

START

Bus

Operation Command

Comments

Write

Erase

Data = B0H

Suspend

WRITE B0H

Standby/

Ready

Read Status Register

Check SR.7

1 = Ready, 0 = Busy

Toggle OE or CE to Update

Status Register

READ STATUS

REGISTER

NO

SR.7 = 1?

YES

Standby

Check SR.6

NO

1 = Suspended

SR.6 = 1?

ERASE HAS

COMPLETED

YES

Write

Read

Read Array

Data = FFH

WRITE FFH

Read array data from block other

than that being erased.

DONE

NO

READING?

YES

Write

Erase Resume Data = D0H

WRITE D0H

CONTINUE

ERASE

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

13

CAT28F001

Figure 7. A.C. Timing for Program/Erase Operation

WRITE

V

POWER-UP

WRITE PROGRAM OR

ERASE SETUP COMMAND

AUTOMATED PROGRAM

OR ERASE DELAY

READ STATUS

REGISTER DATA

WRITE READ ARRAY

COMMAND

CC

& STANDBY

VALID ADDRESS & DATA (PROGRAM)

OR ERASE CONFIRM COMMAND

V

IH

ADDRESSES (A)

A

IN

V

IL

t

AVAV

AVWH

WHAX

IH

CE (E)

V

IL

t

ELWL

t

WHEH

t

WHGL

V

IH

OE (G)

V

IL

t

1, 2, 3, 4

t

WHQV

WHWL

IH

WE (W)

V

IL

t

WLWH

t

DVWH

WHDX

V

IH

HIGH Z

VALID

SRD

DATA (I/O)

D

IN

t

V

PHWL

IL

t

PHHWH

QVPH

V

HH

6.5V

V

IH

RP (P)

V

IL

t

VPWH

t

QVVL

V

PPH

V

PPL

V

(V)

PP

V

IH

V

IL

POWER UP/DOWN PROTECTION

POWER SUPPLY DECOUPLING

The CAT28F001 offers protection against inadvertent

programming during V_PPand V_CCpower transitions.

When powering up the device there is no power-on

sequencing necessary. In other words, V_PPand V_CC

may power up in any order. Additionally V_PPmay be

hardwired to V_PPHindependent of the state of V_CCand

any power up/down cycling. The internal command

register of the CAT28F001 is reset to the Read Mode on

power up.

To reduce the effect of transient power supply voltage

spikes, it is good practice to use a 0.1µF ceramic

capacitorbetweenV_CCandV_SSandV_PPandV_SS.These

high-frequency capacitors should be placed as close as

possible to the device for optimum decoupling.

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

14

CAT28F001

ALTERNATE CE-CONTROLLED WRITES

= +5V ±10%, unless otherwise specified

V

CC

28F001-90

28F001-12

JEDEC

Symbol

Standard

Symbol Parameter

Min

Max

Min

Max

Units

t_AVAV

t_AVEH

t_EHAX

t_WC

t_AS

t_AH

Write Cycle Time

90

120

ns

Address Setup to CE Going High

40

10

40

10

ns

Address Hold Time from CE Going High

t_DVEH

t_EHDX

t_DS

t_DH

Data Setup Time to CE Going High

Data Hold Time from CE Going High

40

10

40

10

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

0

ns

µs

ns

µs

WE Setup Time to CE Going Low

WE Hold Time from CE Going High

CE Pulse Width

40

10

40

10

t_EPH

CE High Pulse Width

t_EHGL

t_PHEL

t_PHHEH

t_VPEH

—

Write Recovery Time Before Read

RP High Recovery to CE Going Low

RP V_HHSetup to CE Going High

V_PPSetup to CE Going High

0

(1)

t_PS

480

100

480

100

(1)

t_PHS

t_VPS

t_EHQV1

—

Duration of Programming Operations

15

t_EHQV2

t_EHQV3

t_EHQV4

t_QVVL

—

Duration of Erase Operations (Boot)

Duration of Erase Operations (Parameter)

Duration of Erase Operations (Main)

V_PPHold from Valid Status Reg Data

1.3

3

1.3

3

Sec

ns

t_VPH⁽¹⁾

0

(1)

t_QVPH

t_PHH

0

ns

RP V_HHHold from Status Reg Data

Boot Block Relock Delay

(1)

t_PHBR

—

100

ns

t_GHHWL

480

OE V_HHSetup to WE Going Low

OE V_HHHold from WE High

t_WHGH

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

15

CAT28F001

Figure 8. Alternate Boot Block Access Method Using OE

WRITE

VALID ADDRESS AND DATA (PROGRAM)

WRITE PROGRAM OR

ERASE SETUP COMMAND

AUTOMATED PROGRAM

OR ERASE DELAY

READ STATUS

REGISTER DATA

OR ERASE CONFIRM COMMAND

V

HH

OE

WE

V

IH

V

IL

t

WHGH

t

GHHWL

V

IH

V

IL

V

IH

VALID

SR DATA

D

DATA

IN

V

IL

Figure 9. Alternate AC Waveform for Write Operations

WRITE

V

POWER-UP

WRITE PROGRAM OR

ERASE SETUP COMMAND

AUTOMATED PROGRAM

OR ERASE DELAY

READ STATUS

REGISTER DATA

WRITE READ ARRAY

COMMAND

CC

& STANDBY

VALID ADDRESS & DATA (PROGRAM)

OR ERASE CONFIRM COMMAND

V

IH

ADDRESSES

A

IN

V

IL

t

EHAX

t

AVEH

AVAV

IH

WE (W)

V

IL

t

WLEL

EHWH

t

EHGL

V

IH

OE (a)

V

IL

t

1, 2, 3, 4

EHQV

EHEL

IH

CE (E)

V

IL

t

ELEH

t

DVEH

EHDX

V

IH

HIGH Z

VALID

SRD

DATA I/O

D

IN

t

V

PHEL

IL

t

PHHEH

QVPH

V

HH

6.5V

V

IH

RP (P)

V

IL

t

VPEH

QVVL

V

PPH

V

PPL

V

(V)

PP

V

IH

V

IL

Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

16

CAT28F001

ORDERING INFORMATION

Prefix

Device #

Suffix

28F001

CAT

P

-90

I

B

T

Product

Number

Temperature Range

Tape & Reel

Optional

Company ID

Boot Block

B: Bottom

T: Top

Blank = Commercial (0˚ - 70˚C)

I = Industrial (-40˚ - 85˚C)

A = Automotive (-40˚ - 105˚C)*

Package

Speed

90: 90 ns

12: 120 ns

N: PLCC

T: TSOP(8mmx20mm)

G: PLCC (Lead free, Halogen free)

L: PDIP (Lead free, Halogen free)

H: TSOP (Lead free, Halogen free)

* -40˚ to +125˚C is available upon request

Note:

(1) The device used in the above example is a CAT28F001PI-90BT (PDIP, Industrial Temperature, 90ns access time, Bottom Boot Block,

Tape & Reel)

Doc. No. MD-1078, Rev. K

17

Characteristics subject to change without notice

CAT28F001

REVISION HISTORY

Date

Revision Description

20-Apr-04

G

Delete data sheet designation

Update Features

Update Pin Configuration

Update Ordering Information

Update A. C. Tables

Update Erase Table

Update Alternate Table

Update Ordering Information

Update Revision History

Update Rev Number

2-Sep-04

29-Mar-05

15-Oct-08

17-Nov-08

H

I

Update Ordering Information

J

K

Eliminate PDIP SnPb package.

Change logo and fine print to ON Semiconductor

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to

any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising

out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights

of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800-282-9855

ON Semiconductor Website: www.onsemi.com

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada

Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

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Order Literature: http://www.onsemi.com/orderlit

Europe, Middle East and Africa Technical Support:

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For additional information, please contact your local

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Characteristics subject to change without notice

Doc. No. MD-1078, Rev. K

18


型号：	CAT28F001L-12TT
厂家：	ONSEMI
描述：	1 Megabit CMOS Boot Block Flash Memory 1兆位的CMOS引导块闪存闪存
文件：	总18页 (文件大小：113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT28F001L-12TT [ONSEMI]

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