CAT25128XE-T2 [ONSEMI]
EEPROM Serial 128-Kb SPI;型号: | CAT25128XE-T2 |
厂家: | ONSEMI |
描述: | EEPROM Serial 128-Kb SPI 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总22页 (文件大小:388K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CAT25128
EEPROM Serial 128-Kb SPI
Description
The CAT25128 is a 128−Kb Serial CMOS EEPROM device
internally organized as 16Kx8 bits. This features a 64−byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the CAT25128 device. The device features
software and hardware write protection, including partial as well as
full array protection.
www.onsemi.com
SOIC−8
UDFN−8
V SUFFIX
CASE 751BD
HU4 SUFFIX
CASE 517AZ
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.*
Features
• 20 MHz SPI Compatible
• 1.8 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8 WIDE
X SUFFIX
CASE 751BE
• 64−byte Page Write Buffer
• Additional Identification Page with Permanent Write Protection
• Self−timed Write Cycle
PIN CONFIGURATION
• Hardware and Software Protection
• Block Write Protection
1
CS
SO
WP
V
CC
HOLD
SCK
SI
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
V
SS
SOIC (X, V), TSSOP (Y), UDFN (HU4)
• Industrial and Extended Temperature Range
• 8−lead SOIC, TSSOP and 8−pad, UDFN Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
PIN FUNCTION
V
CC
†
Pin Name
Function
Chip Select
CS
SO
WP
SI
Serial Data Output
Write Protect
CS
CAT25128
SO
WP
V
Ground
SS
HOLD
SCK
SI
Serial Data Input
Serial Clock
SCK
V
HOLD
Hold Transmission Input
Power Supply
SS
V
CC
Figure 1. Functional Symbol
†The exposed pad for the TDFN/UDFN packages can
be left floating or connected to Ground.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
June, 2018 − Rev. 9
CAT25128/D
CAT25128
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Operating Temperature
−45 to +130
−65 to +150
−0.5 to +6.5
Storage Temperature
°C
Voltage on any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Notes 3, 4)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C.
CC
4. The new product revision (E) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when
a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order
to benefit from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS − MATURE PRODUCT
(V = 1.8 V to 5.5 V, T = −40°C to +85°C and V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
CC
A
Symbol
Parameter
Test Conditions
Min
Max
2
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
I
Supply Current
(Read Mode)
Read, V = 5.5 V,
10 MHz / −40°C to 85°C
CCR
CC
SO open
5 MHz / −40°C to 125°C
10 MHz / −40°C to 85°C
5 MHz / −40°C to 125°C
2
I
Supply Current
(Write Mode)
Write, V = 5.5 V,
4
CCW
CC
SO open
4
I
Standby Current
V
IN
= GND or V , CS = V
,
,
T = −40°C to +85°C
1
SB1
CC
CC
A
WP = V , HOLD = V
,
CC
= 5.5 V
CC
T = −40°C to +125°C
A
3
V
CC
I
Standby Current
V
IN
= GND or V , CS = V
T = −40°C to +85°C
A
4
SB2
CC
CC
WP = GND, HOLD = GND,
T = −40°C to +125°C
A
5
V
CC
= 5.5 V
I
L
Input Leakage Current
V
IN
= GND or V
CC
−2
−1
2
I
LO
Output Leakage
Current
CS = V
OUT
,
T = −40°C to +85°C
A
1
CC
V
= GND or V
CC
T = −40°C to +125°C
A
−1
2
V
IL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
−0.5
0.3 V
CC
V
IH
0.7 V
V + 0.5
CC
V
CC
V
V
CC
V
CC
V
CC
V
CC
> 2.5 V, I = 3.0 mA
0.4
V
OL1
OH1
OL
V
> 2.5 V, I = −1.6 mA
V
V
− 0.8 V
− 0.2 V
V
OH
CC
V
> 1.8 V, I = 150 mA
0.2
V
OL2
OH2
OL
V
> 1.8 V, I = −100 mA
V
OH
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
2
CAT25128
Table 4. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (Rev E)
(V = 1.8 V to 5.5 V, T = −40°C to +85°C and V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
CC
A
Symbol
Parameter
Test Conditions
Min
Max
0.8
1.2
3.0
2.0
Units
I
Supply Current
(Read Mode)
Read, SO open /
V
CC
V
CC
V
CC
= 1.8 V, f
SCK
= 5 MHz
=10 MHz
= 20 MHz
mA
CCR
−40°C to +85°C
= 2.5 V, f
SCK
SCK
= 5.5 V, f
Read, SO open /
−40°C to +125°C
2.5 V< V < 5.5 V,
CC
f
= 10 MHz
= 1.8 V
= 2.5 V
= 5.5 V
SCK
I
Supply Current
(Write Mode)
Write, CS = V
/
V
V
V
1.5
2
mA
CCW
CC
CC
CC
CC
−40°C to +85°C
2
Write, CS = V
/
2.5 V< V < 5.5 V
2
CC
CC
−40°C to +125°C
I
Standby Current
V
= GND or V
CC
= 5.5 V
,
T = −40°C to +85°C
1
3
3
5
2
1
2
mA
mA
SB1
IN
CC
A
CS = V , WP = V
,
CC
T = −40°C to +125°C
A
V
CC
I
Standby Current
V
IN
= GND or V
,
T = −40°C to +85°C
A
SB2
CC
CS = V , WP = GND,
CC
= 5.5 V
T = −40°C to +125°C
A
V
CC
I
L
Input Leakage Current
V
IN
= GND or V
CC
−2
−1
mA
mA
I
Output Leakage
Current
CS = V
T = −40°C to +85°C
A
LO
CC
V
OUT
= GND or V
CC
T = −40°C to +125°C
A
−1
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
≥ 2.5 V
≥ 2.5 V
< 2.5 V
< 2.5 V
−0.5
0.3 V
CC
V
V
V
V
V
V
V
V
IL1
V
IH1
0.7 V
V
CC
+ 0.5
CC
V
−0.5
0.75 V
0.25 V
CC
IL2
IH2
V
V
CC
+ 0.5
CC
V
≥ 2.5 V, I = 3.0 mA
0.4
OL1
OH1
OL
V
≥ 2.5 V, I = −1.6 mA
V
V
− 0.8 V
− 0.2 V
OH
CC
V
< 2.5 V, I = 150 mA
0.2
OL2
OH2
OL
V
< 2.5 V, I = −100 mA
OH
CC
Table 5. PIN CAPACITANCE (Note 5) (T = 25°C, f = 1.0 MHz, V = +5.0 V)
A
CC
Symbol
Test
Conditions
= 0 V
Min
Typ
Max
8
Units
pF
C
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
V
OUT
OUT
C
V
IN
= 0 V
8
pF
IN
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
www.onsemi.com
3
CAT25128
Table 6. A.C. CHARACTERISTICS − MATURE PRODUCT
(T = −40°C to +85°C (Industrial) and T = −40°C to +125°C (Extended).) (Notes 6, 9)
A
A
V
= 1.8 V − 5.5 V / −405C to +855C
= 2.5 V − 5.5 V / −405C to +1255C
V
= 2.5 V − 5.5 V
CC
CC
V
CC
−405C to +855C
Min
DC
40
Max
Min
Max
Symbol
Parameter
Units
MHz
ns
f
Clock Frequency
5
DC
10
SCK
t
Data Setup Time
Data Hold Time
20
20
40
40
SU
t
H
40
ns
t
SCK High Time
75
ns
WH
t
SCK Low Time
75
ns
WL
t
HOLD to Output Low Z
Input Rise Time
50
2
25
2
ns
LZ
t
RI
(Note 7)
(Note 7)
ms
t
FI
Input Fall Time
2
2
ms
t
t
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
0
0
ns
HD
CD
10
10
ns
t
V
75
40
ns
t
0
0
ns
HO
t
50
20
25
ns
DIS
t
100
ns
HZ
t
140
30
70
15
15
15
15
10
60
ns
CS
t
CS Setup Time
ns
CSS
CSH
CNS
CNH
WPS
WPH
t
t
CS Hold Time
30
ns
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
20
ns
t
20
ns
t
10
ns
t
WP Hold Time
100
ns
t
(Note 8)
Write Cycle Time
5
5
ms
WC
6. AC Test Conditions:
Input Pulse Voltages: 0.3 V to 0.7 V
CC
CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
/I
; C = 50 pF
OL max OH max L
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. t is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
9. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). t
timing specification is valid
CSH
for die revision D and higher. The die revision D is identified by letter “D” or a dedicated marking code on top of the package. For
previous product revision (Rev.C) the t
is defined relative to the negative clock edge.
CSH
Table 7. POWER−UP TIMING (Notes 7, 10)
Symbol
Parameter
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
10.t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
www.onsemi.com
4
CAT25128
Table 8. A.C. CHARACTERISTICS – NEW PRODUCT (Rev E) (V = 1.8 V to 5.5 V, T = −40°C to +85°C (Industrial) and
CC
A
V
CC
= 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.) (Note 11)
A
V
CC
= 1.8 V − 5.5 V
V
CC
= 2.5 V − 5.5 V
V
CC
= 4.5 V − 5.5 V
−405C to +855C
−405C to +1255C
−405C to +855C
Min
DC
20
Max
Min
DC
10
Max
Min
DC
5
Max
Symbol
Parameter
Clock Frequency
Units
MHz
ns
f
5
10
20
SCK
t
Data Setup Time
Data Hold Time
SU
t
H
20
10
5
ns
t
SCK High Time
75
40
20
20
ns
WH
t
SCK Low Time
75
40
ns
WL
t
HOLD to Output Low Z
Input Rise Time
50
2
25
2
25
2
ns
LZ
t
RI
(Note 12)
(Note 12)
ms
t
FI
Input Fall Time
2
2
2
ms
t
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
0
0
0
5
ns
HD
CD
t
10
10
ns
t
V
75
40
20
ns
t
0
0
0
ns
HO
t
50
20
25
20
25
ns
DIS
t
100
ns
HZ
t
80
30
30
20
20
10
10
40
30
30
20
20
10
10
20
15
20
15
15
10
10
ns
CS
t
CS Setup Time
ns
CSS
CSH
CNS
CNH
WPS
WPH
t
t
CS Hold Time
ns
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
ns
t
ns
t
ns
t
WP Hold Time
ns
t
(Note 13)
Write Cycle Time
5
5
5
ms
WC
11. AC Test Conditions:
Input Pulse Voltages: 0.3 V to 0.7 V
CC
CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
/I
; C = 30 pF
OL max OH max L
12.This parameter is tested initially and after a design or process change that affects the parameter.
13.t is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
Table 9. POWER−UP TIMING (Notes 12, 14)
Symbol Parameter
Min
0.1
0.1
Max
1
Units
t
Power−up to Read Operation
Power−up to Write Operation
ms
ms
PUR
t
1
PUW
14.t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
www.onsemi.com
5
CAT25128
Pin Description
Functional Description
The CAT25128 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 10.
Reading data stored in the CAT25128 is accomplished by
simply providing the READ command and an address.
Writing to the CAT25128, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25128.
CS: The chip select input pin is used to enable/disable the
CAT25128. When CS is high, the SO output is tri−stated (high
impedance) and the device is in Standby Mode (unless an
internal write operation is in progress). Every communication
session between host and CAT25128 must be preceded by a
high to low transition and concluded with a low to high
transition of the CS input.
After a high to low transition on the CS input pin, the
CAT25128 will accept any one of the six instruction
op−codes listed in Table 10 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
The CAT25128, New Product Rev E features an
additional Identification Page (64 bytes) which can be
accessed for Read and Write operations when the IPL bit
from the Status Register is set to “1”. The user can also
choose to make the Identification Page permanent write
protected.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
Table 10. INSTRUCTION SET
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25128, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, it is recommended the HOLD input to be tied to
Instruction
WREN
WRDI
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
V , either directly or through a resistor.
CC
WRITE
t
CS
CS
t
t
t
WL
CSS
WH
t
t
t
CNH
CSH
CNS
SCK
SI
t
H
t
RI
t
FI
t
SU
VALID
IN
t
V
t
V
t
DIS
t
HO
HI−Z
HI−Z
VALID
OUT
SO
Figure 2. Synchronous Data Timing
www.onsemi.com
6
CAT25128
Status Register
The Status Register, as shown in Table 11, contains a
number of status and control bits.
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 13.
The IPL (Identification Page Latch) bit determines
whether the additional Identification Page (IPL = 1) or main
memory array (IPL = 0) can be accessed both for Read and
Write operations. The IPL bit is set by the user with the
WRSR command and is volatile. The IPL bit is
automatically reset after read/write operations.
The LIP bit is set by the user with the WRSR command
and is non−volatile. When set to 1, the Identification Page is
permanently write protected (locked in Read−only mode).
Note: The IPL and LIP bits cannot be set to 1 using the
same WRSR instruction. If the user attempts to set (“1”)
both the IPL and LIP bit in the same time, these bits cannot
be written and therefore they will remain unchanged.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 12. The protected
blocks then become read−only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
Table 11. STATUS REGISTER
7
6
5
0
4
3
2
1
0
WPEN
IPL*
LIP*
BP1
BP0
WEL
RDY
*The IPL and LIP bits are available for the New Product only. The Status Register bit 6 and bit 4 are set to “0” for the older product revisions.
Table 12. BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address Protected
None
Protection
No Protection
0
0
1
1
0
1
0
1
3000−3FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
2000−3FFF
0000−3FFF
Table 13. WRITE PROTECT CONDITIONS
WPEN
WP
X
WEL
Protected Blocks
Protected
Unprotected Blocks
Status Register
Protected
Writable
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Writable
Protected
Writable
Protected
Writable
X
Protected
Low
Low
High
High
Protected
Protected
Protected
Protected
Writable
Protected
Protected
Protected
www.onsemi.com
7
CAT25128
WRITE OPERATIONS
The CAT25128 device powers up into a write disable
instruction to the CAT25128. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
1
0
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
www.onsemi.com
8
CAT25128
Byte Write
Following completion of the write cycle, the CAT25128 is
automatically returned to the write disable state.
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 14 significant address
bits are used by the CAT25128. The rest are don’t care bits,
as shown in Table 14. Internal programming will start after
the low to high CS transition. During an internal write cycle,
all commands, except for RDSR (Read Status Register) will
be ignored. The RDY bit will indicate if the internal write
cycle is in progress (RDY high), or the device is ready to
accept commands (RDY low).
Write Identification Page
The additional 64−byte Identification Page (IP) can be
written with user data using the same Write commands
sequence as used for Page Write to the main memory array
(Figure 6). The IPL bit from the Status Register must be set
(IPL = 1) using the WRSR instruction, before attempting
to write to the IP.
The address bits [A15:A6] are Don’t Care and the
[A5:A0] bits define the byte address within the
Identification Page. In addition, the Byte Address must point
to a location outside the protected area defined by the BP1,
BP0 bits from the Status Register. When the full memory
array is write protected (BP1, BP0 = 1,1), the write
instruction to the IP is not accepted and not executed.
Also, the write to the IP is not accepted if the LIP bit from
the Status Register is set to 1 (the page is locked in
Read−only mode).
Page Write
After sending the first data byte to the CAT25128, the host
may continue sending data, up to a total of 64 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Table 14. BYTE ADDRESS
Address Significant Bits
Address Don’t Care Bits
A15 − A14
# Address Clock Pulses
Main Memory Array
Identification Page*
*New Product only.
A13 − A0
A5 − A0
16
16
A15 − A6
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SCK
OPCODE
DATA IN
BYTE ADDRESS*
D7 D6 D5 D4 D3 D2 D1 D0
SI
0
0
0
0
0
0
1
0
A
N
A
0
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
SO
* Please check the Byte Address Table (Table 14)
Figure 5. Byte WRITE Timing
CS
24+(N−1)x8−1 .. 24+(N−1)x8
21 22 23 24−31 32−39
0
1
2
3
4
5
6
7
8
24+Nx8−1
SCK
SI
Data Byte N
7..1
BYTE ADDRESS*
OPCODE
DATA IN
A
N
A
0
0
0
0
0
0
0
1
0
0
Data Data Data
Byte 1 Byte 2 Byte 3
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 14)
Figure 6. Page WRITE Timing
www.onsemi.com
9
CAT25128
Write Status Register
Write Protection
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
SI
OPCODE
0
DATA IN
3
0
0
0
0
0
0
7
MSB
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
SO
Figure 7. WRSR Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Dashed Line = mode (1, 1)
Figure 8. WP Timing
www.onsemi.com
10
CAT25128
READ OPERATIONS
Read from Memory Array
address register defined by [A5:A0] bits is automatically
incremented and the next data byte from the IP is shifted out.
The byte address must not exceed the 64−byte page
boundary.
To read from memory, the host sends a READ instruction
followed by a 16−bit address (see Table 14 for the number
of significant address bits).
After receiving the last address bit, the CAT25128 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25128 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at
any time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the full content of the status register (New product,
Rev. E) or the RDY (Ready) bit only (i.e., data out = FFh) for
previous product revisions C, D (Mature product). For easy
detection of the internal write cycle completion, both during
writing to the memory array and to the status register, we
recommend sampling the RDY bit only through the polling
routine. After detecting the RDY bit “0”, the next RDSR
instruction will always output the expected content of the
status register.
Read Identification Page
Reading the additional 64−byte Identification Page (IP) is
achieved using the same Read command sequence as used
for Read from main memory array (Figure 9). The IPL bit
from the Status Register must be set (IPL = 1) before
attempting to read from the IP. The [A5:A0] are the address
significant bits that point to the data byte shifted out on the
SO pin. If the CS continues to be held low, the internal
CS
20 21 22 23 24 25 26 27 28 29 30
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
OPCODE
BYTE ADDRESS*
A
0
A
N
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 14)
MSB
Figure 9. READ Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
3
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
5
7
6
4
2
1
0
SO
MSB
Figure 10. RDSR Timing
www.onsemi.com
11
CAT25128
Hold Operation
The CAT25128 device powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
The HOLD input can be used to pause communication
between host and CAT25128. To pause, HOLD must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is low.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
Design Considerations
The CAT25128 device incorporates Power−On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
below the POR trigger level. This bi−directional POR
behavior protects the device against ‘brown−out’ failure
following a temporary loss of power.
Delivery State
The CAT25128 is shipped erased, i.e., all bytes are FFh.
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Dashed Line = mode (1, 1)
Figure 11. HOLD Timing
www.onsemi.com
12
CAT25128
Table 15. ORDERING INFORMATION (Notes 15 − 18)
Specific De-
vice Mark-
ing*
Package
Type
†
Device Order Number
Temperature Range
Lead Finish
Shipping
CAT25128YI−GT3
S28E
TSSOP−8
TSSOP−8
UDFN−8
UDFN−8
I = Industrial
NiPdAu
Tape & Reel,
(−40°C to +85°C)
3,000 Units / Reel
CAT25128YE−GT3
CAT25128HU4I−GT3
CAT25128HU4E−GT3
CAT25128VI−GT3
CAT25128VE−GT3
CAT25128XI−T2
S28E
E = Extended
(−40°C to +125°C)
NiPdAu
NiPdAu
Tape & Reel,
3,000 Units / Reel
S7U
I = Industrial
(−40°C to +85°C)
Tape & Reel,
3,000 Units / Reel
S7U
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
25128E
25128E
25128E
25128E
SOIC−8,
JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
SOIC−8,
JEDEC
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel,
3,000 Units / Reel
SOIC−8,
EIAJ
I = Industrial
(−40°C to +85°C)
Matte−Tin
Matte−Tin
Tape & Reel,
2,000 Units / Reel
CAT25128XE−T2
SOIC−8,
EIAJ
E = Extended
(−40°C to +125°C)
Tape & Reel,
2,000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
15.All packages are RoHS−compliant (Lead-free, Halogen-free).
16.The standard lead finish is NiPdAu.
17.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
18.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
www.onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A
1
SCALE 2:1
DATE 23 MAR 2015
NOTES:
A
B
E
D
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
0.55
0.05
A
A1
A3
b
0.45
0.00
0.13 REF
0.10 C
A3
EXPOSED Cu
MOLD CMPD
0.10 C
0.20
0.30
TOP VIEW
D
2.00 BSC
D2
E
E2
e
L
L1
1.35
3.00 BSC
1.25
0.50 BSC
0.25
−−−
1.45
DETAIL B
A1
A
1.35
0.10
0.08
C
C
DETAIL B
A3
C
0.35
0.15
ALTERNATE
CONSTRUCTIONS
A1
SIDE VIEW
SEATING
PLANE
NOTE 4
GENERIC
MARKING DIAGRAM*
1
DETAIL A
D2
L
XXXXX
AWLYWG
1
4
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
E2
W
G
= Work Week
= Pb−Free Package
8
5
8X
b
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
e
M
0.10
C A
B
M
0.05
C
NOTE 3
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
1.56
8X
0.68
1.45 3.40
1
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
98AON42552E
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
REFERENCE:
DESCRIPTION: UDFN8, 2X3 EXTENDED PAD
PAGE 1 OF2
DOCUMENT NUMBER:
98AON42552E
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION FROM POD #UDFN8−046−01 TO ON SEMICON-
DUCTOR. REQ. BY B. BERGMAN.
23 JUL 2009
A
REDREW PACKAGE DRAWING TO ON SEMICONDUCTOR/JEDEC STANDARD.
REQ. BY B. BECKER.
23 MAR 2015
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2015
Case Outline Number:
March, 2015 − Rev. A
517AZ
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
98AON34272E
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
REFERENCE:
DESCRIPTION: SOIC 8, 150 MILS
PAGE 1 OF2
DOCUMENT NUMBER:
98AON34272E
PAGE 2 OF 2
ISSUE
REVISION
DATE
19 DEC 2008
O
RELEASED FOR PRODUCTION FROM POD #SOIC8−002−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2008
Case Outline Number:
December, 2008 − Rev. 01O
751BD
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
A
A1
b
2.03
0.25
0.48
0.25
5.33
8.26
5.38
0.05
0.36
0.19
5.13
7.75
5.13
c
E
E1
D
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
e
b
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
98AON34273E
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
REFERENCE:
DESCRIPTION: SOIC−8, 208 MILS
PAGE 1 OF2
DOCUMENT NUMBER:
98AON34273E
PAGE 2 OF 2
ISSUE
REVISION
DATE
19 DEC 2008
O
RELEASED FOR PRODUCTION FROM POD #SOIK8−031−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2008
Case Outline Number:
December, 2008 − Rev. 01O
751BE
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
DATE 19 DEC 2008
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
98AON34428E
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
REFERENCE:
DESCRIPTION: TSSOP8, 4.4X3
PAGE 1 OF2
DOCUMENT NUMBER:
98AON34428E
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION FROM POD #TSSOP8−004−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2008
Case Outline Number:
December, 2008 − Rev. 01O
948AL
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
◊
相关型号:
©2020 ICPDF网 联系我们和版权申明