CAT24C256ZD2I-GT3 [ONSEMI]
256 kb I2C CMOS Serial EEPROM; 256 KB I2C CMOS串行EEPROM
| 型号： | CAT24C256ZD2I-GT3 |
| 厂家： | 
ONSEMI |
| 描述： | 256 kb I2C CMOS Serial EEPROM |
| 文件： | 总14页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C256
256 kb I2C CMOS Serial
EEPROM
Description
The CAT24C256 is a 256 kb Serial CMOS EEPROM, internally
organized as 32,768 words of 8 bits each.
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It features a 64−byte page write buffer and supports both the
2
Standard (100 kHz) as well as Fast (400 kHz) I C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
External address pins make it possible to address up to eight
CAT24C256 devices on the same bus.
SOIC−8
W SUFFIX
CASE 751BD
TDFN−8
ZD2 SUFFIX
CASE 511AM
SOIC−8
X SUFFIX
CASE 751BE
Features
2
• Supports Standard and Fast I C Protocol
• 1.8 V to 5.5 V Supply Voltage Range
• 64−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
PDIP−8
L SUFFIX
CASE 646AA CASE 948AL
TSSOP−8
Y SUFFIX
2
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• PDIP, SOIC, TSSOP and TDFN 8−lead Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
PIN CONFIGURATION
1
A
0
A
1
A
2
V
CC
WP
SCL
SDA
V
SS
PDIP (L), SOIC (W, X),
TSSOP (Y), TDFN (ZD2)
V
CC
For the location of Pin 1, please consult the
corresponding package drawing.
SCL
PIN FUNCTION
CAT24C256
SDA
A , A , A
2
1
0
Pin Name
Function
Device Address
WP
A , A , A
0
1
2
SDA
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
SCL
WP
V
SS
Figure 1. Functional Symbol
V
CC
V
SS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
November, 2009 − Rev. 9
CAT24C256/D
CAT24C256
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
–65 to +150
–0.5 to +6.5
Voltage on any Pin with Respect to Ground (Note 1)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C.
CC
Table 3. D.C. OPERATING CHARACTERISTICS
(V = 1.8 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
= 400 kHz
Min
Max
1
Units
mA
I
Read Current
Read, f
CCR
SCL
I
Write Current
Write, f
= 400 kHz
3
mA
CC
SCL
I
SB
Standby Current
All I/O Pins at GND or V
T = −40°C to +85°C
A
1
mA
CC
T = −40°C to +125°C
A
2
I
L
I/O Pin Leakage
Pin at GND or V
T = −40°C to +85°C
A
1
mA
CC
T = −40°C to +125°C
A
2
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
−0.5
V
x 0.3
V
V
V
V
IL
CC
V
IH
V
x 0.7
V
CC
+ 0.5
CC
V
OL1
V
OL2
V
V
≥ 2.5 V, I = 3.0 mA
0.4
0.2
CC
OL
< 2.5 V, I = 1.0 mA
CC
OL
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V = 1.8 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Conditions
Max
8
Units
pF
C
C
(Note 4)
(Note 4)
(Note 5)
SDA I/O Pin Capacitance
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 0 V
= 0 V
IN
IN
Input Capacitance (other pins)
6
pF
I
WP Input Current
(Product Revision C and higher)
< V , V = 5.5 V
130
120
80
1
mA
WP
IH
CC
< V , V = 3.3 V
IH
CC
< V , V = 1.8 V
IH
IH
CC
> V
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pull−down reverts to a weak current source. The
CC
variable WP input impedance is available only for Die Rev. C and higher.
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2
CAT24C256
Table 5. A.C. CHARACTERISTICS (Note 6)
(V = 1.8 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Fast−Plus (Note 9)
= 2.5 V − 5.5 V
Standard
= 1.8 V − 5.5 V
Fast
= 1.8 V − 5.5 V
V
CC
V
CC
V
T
= −405C to +855C
CC
A
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Units
kHz
ms
F
SCL
Clock Frequency
100
400
1,000
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
0.25
0.55
0.25
0.25
0
HD:STA
t
ms
LOW
t
ms
HIGH
t
4.7
0
ms
SU:STA
HD:DAT
t
ms
t
Data In Setup Time
250
100
50
ns
SU:DAT
t
(Note 7)
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
1,000
300
300
300
100
100
ns
R
t (Note 7)
ns
F
t
4
0.6
1.3
0.25
0.5
ms
SU:STO
t
Bus Free Time Between
STOP and START
4.7
ms
BUF
t
SCL Low to Data Out Valid
Data Out Hold Time
3.5
0.9
0.50
100
ms
ns
ns
AA
t
100
100
50
DH
T (Note 7)
Noise Pulse Filtered at SCL
and SDA Inputs
100
100
i
t
WP Setup Time
0
0
0
1
ms
ms
SU:WP
t
WP Hold Time
2.5
2.5
HD:WP
t
Write Cycle Time
Power-up to Ready Mode
5
1
5
1
5
1
ms
ms
WR
t
(Notes 7, 8)
0.1
PU
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
9. Fast−Plus (1 MHz) speed class available for product revision “D”, identified by letter “D” marked on top of the package.
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x V to 0.8 x V
CC
CC
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
≤ 50 ns
0.3 x V , 0.7 x V
CC
CC
0.5 x V
CC
Current Source: I = 3 mA (V ≥ 2.5 V); I = 1 mA (V < 2.5 V); C = 100 pF
L
CC
L
CC
L
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3
CAT24C256
Power-On Reset (POR)
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
The CAT24C256 Die Rev. C incorporates Power−On
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state.
The device will power up into Standby mode after V
exceeds the POR trigger level and will power down into
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
CC
Reset mode when V drops below the POR trigger level.
CC
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
signal generated by the Master.
STOP
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when following a
Write command) or sends the Slave into standby mode
(when following a Read command).
A , A and A : The Address pins accept the device address.
0
1
2
These pins have on−chip pull−down resistors.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
Functional Description
The CAT24C256 supports the Inter−Integrated Circuit
The next 3 bits, A , A and A , select one of 8 possible Slave
2
1
0
2
(I C) Bus data transmission protocol, which defines a device
devices. The last bit, R/W, specifies whether a Read (1) or
Write (0) operation is to be performed.
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C256 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the byte address and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9th clock cycle. If
the Master acknowledges the data, then the Slave continues
transmitting. The Master terminates the session by not
acknowledging the last data byte (NoACK) and by sending
a STOP to the Slave. Bus timing is illustrated in Figure 5.
the bus as determined by the device address inputs A , A ,
0
1
and A .
2
I2C Bus Protocol
2
The I C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V supply via pull−up
CC
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
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4
CAT24C256
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A
2
A
1
A
0
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4. Acknowledge Timing
t
t
F
t
R
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
SU:DAT
SU:STO
HD:STA
SDA IN
t
BUF
t
AA
t
DH
SDA OUT
Figure 5. Bus Timing
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5
CAT24C256
WRITE OPERATIONS
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address and data to be written
(Figure 6). The Slave acknowledges all 4 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT24C256 is busy writing or is ready to accept commands.
Polling is implemented by interrogating the device with a
‘Selective Read’ command (see READ OPERATIONS).
The CAT24C256 will not acknowledge the Slave address,
as long as internal Write is in progress.
Page Write
Hardware Write Protection
The CAT24C256 contains 32,768 bytes of data, arranged
in 512 pages of 64 bytes each. A two byte address word,
following the Slave address, points to the first byte to be
written. The most significant bit of the address word is ‘don’t
care’, the next 9 bits identify the page and the last 6 bits
identify the byte within the page. Up to 64 bytes can be
written in one Write cycle (Figure 8).
The internal byte address counter is automatically
incremented after each data byte is loaded. If the Master
transmits more than 64 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24C256. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24C256 will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
The CAT24C256 is shipped erased, i.e., all bytes are FFh.
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6
CAT24C256
S
T
A
R
T
S
T
BUS ACTIVITY:
MASTER
SLAVE
BYTE ADDRESS
8
O
P
ADDRESS
DATA
A
15
− A
A − A
7 0
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
* = Don’t Care Bit
Figure 6. Byte Write Timing
SCL
SDA
8th Bit
Byte n
ACK
t
WR
STOP
START
CONDITION
ADDRESS
CONDITION
Figure 7. Write Cycle Timing
S
T
A
R
T
BUS
ACTIVITY:
MASTER
S
T
SLAVE
ADDRESS
BYTE ADDRESS
− A A − A
7 0
O
P
A
15
DATA
DATA n
DATA n+63
8
S
P
SDA LINE
*
A
C
K
A
C
K
A
C
K
A
C
K
A
A
A
C
K
C
K
C
K
* = Don’t Care Bit
Figure 8. Page Write Timing
ADDRESS
BYTE
DATA
BYTE
1
1
8
9
8
d
SCL
SDA
a
a
0
d
7
7
0
t
SU:WP
WP
t
HD:WP
Figure 9. WP Timing
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7
CAT24C256
READ OPERATIONS
The address counter can be initialized by performing a
‘dummy’ Write operation (Figure 11). Here the START is
followed by the Slave address (with the R/W bit set to ‘0’)
and the desired two byte address. Instead of following up
with data, the Master then issues a 2nd START, followed by
the ‘Immediate Address Read’ sequence, as described
earlier.
Immediate Address Read
In standby mode, the CAT24C256 internal address
counter points to the data byte immediately following the
last byte accessed by a previous operation. If that ‘previous’
byte was the last byte in memory, then the address counter
will point to the 1st memory byte, etc.
When, following a START, the CAT24C256 is presented
with a Slave address containing a ‘1’ in the R/W bit position
(Figure 10), it will acknowledge (ACK) in the 9th clock cycle,
and will then transmit data being pointed at by the internal
address counter. The Master can stop further transmission by
issuing a NoACK, followed by a STOP condition.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAT24C256, then the device will continue
transmitting as long as each data byte is acknowledged by
the Master (Figure 12). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap−around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting byte
address.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address counter.
S
T
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
O
P
SDA LINE
S
P
A
C
K
N
O
A
C
K
DATA
SCL
SDA
8
9
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Address Read Timing
S
T
A
R
T
S
T
S
T
BUS ACTIVITY:
MASTER
A
R
T
BYTE ADDRESS
− A A − A
7 0
SLAVE
SLAVE
O
P
ADDRESS
ADDRESS
A
15
DATA
8
S
S
P
SDA LINE
*
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
* = Don’t Care Bit
Figure 11. Selective Read Timing
S
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
O
P
DATA n
DATA n+1
DATA n+2
DATA n+x
P
SDA LINE
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 12. Sequential Read Timing
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8
CAT24C256
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT24C256
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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10
CAT24C256
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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11
CAT24C256
PACKAGE DIMENSIONS
TDFN8, 3x4.9
CASE 511AM−01
ISSUE A
D
A
DETAIL A
DAP SIZE
2.6 x 3.3mm
E
E2
PIN #1
IDENTIFICATION
A1
PIN #1 IDENTIFICATION
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
NOM
MAX
A2
A
A
0.70
0.00
0.45
0.75
0.02
0.55
0.80
0.05
0.65
A1
A2
A1
A3
FRONT VIEW
A3
b
0.20 REF
0.30
0.25
2.90
0.90
4.80
0.90
0.35
3.10
1.10
5.00
1.10
b
D
3.00
D2
E
1.00
4.90
L
E2
e
1.00
0.65 TYP
0.60
e
L
0.50
0.70
DETAIL A
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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12
CAT24C256
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
b
2.03
0.25
0.48
0.25
5.33
8.26
5.38
0.05
0.36
0.19
5.13
7.75
5.13
c
E
E1
D
E
E1
e
1.27 BSC
0.51
0.76
L
0º
8º
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
A
q
e
b
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
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13
CAT24C256
Example of Ordering Information (Note 12)
Prefix
Device #
Suffix
CAT
24C256
W
I
− G
T3
Lead Finish
Temperature Range
Company ID
(Optional)
G: NiPdAu
Blank: Matte−Tin (Note 13)
I = Industrial (−40°C to +85°C)
E = Extended (−40°C to +125°C)
Product Number
24C256
Tape & Reel (Note 17)
T: Tape & Reel
2: 2,000 / Reel (Notes 13, 14)
3: 3,000 / Reel
Package
L: PDIP
W: SOIC, JEDEC
X: SOIC, EIAJ (Note )
Y: TSSOP
ZD2: TDFN (3 x 4.9 mm) (Note 14)
ORDERING INFORMATION
Orderable Part Numbers
CAT24C256LI−G
CAT24C256LE−G
CAT24C256WI−GT3
CAT24C256WE−GT3
CAT24C256XE−T2
CAT24C256XI−T2
CAT24C256YI−GT3
CAT24C256YE−GT3
CAT24C256ZD2EGT2* (Note 16)
CAT24C256ZD2IGT2* (Note 16)
10.All packages are RoHS-compliant (Lead-free, Halogen-free).
11. The standard lead finish is NiPdAu.
12.The device used in the above example is a CAT24C256WI−GT3 (SOIC−JEDEC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel).
13.For SOIC, EIAJ (X) package the standard lead finish is Matte−Tin. This package is available in 2,000 pcs/reel, i.e., CAT24C256XI−T2.
14.The TDFN 3 x 4.9 mm (ZD2) package is available in 2,000 pcs/reel, i.e., CAT24C256ZD2I−GT2.
15.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
16.Part number is not exactly the same as the “Example of Ordering Information” shown above. For part numbers marked with * there are NO
hyphens in the orderable part numbers.
17.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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For additional information, please contact your local
Sales Representative
CAT24C256/D
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