CAT24AA16WI-T10 [ONSEMI]
16-Kb I2C CMOS Serial EEPROM; 16 kb的I²C CMOS串行EEPROM
| 型号： | CAT24AA16WI-T10 |
| 厂家： | 
ONSEMI |
| 描述： | 16-Kb I2C CMOS Serial EEPROM |
| 文件： | 总10页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24AA16
16-Kb I2C CMOS Serial
EEPROM
Description
The CAT24AA16 is a 16−Kb CMOS Serial EEPROM device
internally organized as 2048x8 bits.
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The device features a 16−byte page write buffer and supports
2
100 kHz, 400 kHz and 1 MHz I C protocols.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
SOIC−8
W SUFFIX
CASE 751BD
TSOT−23
TB SUFFIX
CASE 419AE
Features
2
• Standard and Fast I C Protocol Compatible
PIN CONFIGURATIONS
• Supports 1 MHz Clock Frequency
• 1.7 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
SOIC
NC
NC
NC
V
CC
8
7
6
5
1
2
3
4
WP
• Hardware Write Protection for Entire Memory
2
SCL
SDA
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
V
(SCL and SDA)
SS
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial Temperature Range
(Top View)
TSOT−23
5
1
SCL
WP
• This Device is Pb−Free, Halogen Free/BFR Free and are RoHS
V
SS
2
Compliant
3
4
SDA
V
CC
V
CC
(Top View)
SCL
WP
PIN FUNCTION
CAT24AA16
SDA
Pin Name
SDA
Function
Serial Data Input/Output
Clock Input
SCL
WP
Write Protect
V
SS
V
CC
Power Supply
Ground
Figure 1. Functional Symbol
V
SS
NC
No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
August, 2009 − Rev. 1
CAT24AA16/D
CAT24AA16
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on any Pin with Respect to Ground (Note 1)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. REABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode @ 25°C
Table 3. DC OPERATING CHARACTERISTICS (V = 1.7 V to 5.5 V, T = −40°C to 85°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Read Current
Test Conditions
Min
Max
0.5
1
Units
mA
mA
mA
mA
V
I
Read, f
= 400 kHz
= 400 kHz
CCR
SCL
SCL
I
Write Current
Write, f
CCW
I
SB
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
All I/O Pins at GND or V
1
CC
I
L
Pin at GND or V
1
CC
V
IL
−0.5
V
x 0.3
CC
V
IH
V
x 0.7
V
+ 0.5
V
CC
CC
V
OL1
V
OL2
V
V
w 2.5 V, I = 3.0 mA
0.4
0.2
V
CC
OL
< 2.5 V, I = 1.0 mA
V
CC
OL
Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 1.7 V to 5.5 V, T = −40°C to 85°C, unless otherwise specified.)
CC
A
Symbol
Parameter
SDA I/O Pin Capacitance
Input Capacitance (Other Pins)
WP Input Current
Conditions
Max
8
Units
pF
C
C
I
(Note 4)
(Note 4)
(Note 5)
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 0 V
= 0 V
IN
IN
6
pF
mA
< 0.5 x V , V = 5.5 V
200
150
100
1
WP
CC
CC
< 0.5 x V , V = 3.3 V
CC
CC
< 0.5 x V , V = 1.8 V
CC
CC
CC
> 0.5 x V
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pull−down reverts to a weak current source.
CC
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2
CAT24AA16
Table 5. AC CHARACTERISTICS (Note 6) (V = 1.7 V to 5.5 V, T = −40°C to 85°C, unless otherwise specified.)
CC
A
Standard
Fast
1 MHz
V
CC
= 1.7 V − 5.5 V
V
CC
= 1.7 V − 5.5 V
V = 2.5 V − 5.5 V
CC
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Clock Frequency
Units
kHz
ms
F
SCL
100
400
1000
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
0.25
0.4
0.4
0.25
0
HD:STA
t
ms
LOW
t
ms
HIGH
t
4.7
0
ms
SU:STA
HD:DAT
t
ns
t
Data In Setup Time
250
100
100
ns
SU:DAT
t
(Note 7)
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
1000
300
300
300
300
100
ns
R
t (Note 7)
ns
F
t
4
0.6
1.3
0.25
0.5
ms
SU:STO
t
Bus Free Time Between STOP and
START
4.7
ms
BUF
t
SCL Low to Data Out Valid
Data Out Hold Time
3.5
0.9
0.4
ms
ns
ns
AA
t
100
50
50
DH
T (Note 7)
Noise Pulse Filtered at SCL and SDA
Inputs
100
100
100
i
t
WP Setup Time
0
0
0
1
ms
ms
SU:WP
t
WP Hold Time
2.5
2.5
HD:WP
t
Write Cycle Time
Power−up to Ready Mode
5
1
5
1
5
1
ms
ms
WR
t
PU
(Notes 7, 8)
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x V to 0.8 x V
CC
CC
Input Rise and Fall Times
Input Reference Levels
v 50 ns
0.3 x V , 0.7 x V
CC
CC
Output Reference Levels
Output Load
0.5 x V
CC
Current Source: I = 3 mA (V w 2.5 V); I = 1 mA (V < 2.5 V); C = 100 pF
OL
CC
OL
CC
L
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3
CAT24AA16
I2C Bus Protocol
The 2−wire I C bus consists of two lines, SCL and SDA,
connected to the V supply via pullup resistors. The Master
provides the clock to the SCL line, and the Master and Slaves
drive the SDA line. A ‘0’ is transmitted by pulling a line
LOW and a ‘1’ by releasing it HIGH. Data transfer may be
initiated only when the bus is not busy (see AC
Characteristics). During data transfer, SDA must remain
stable while SCL is HIGH.
Power−On Reset (POR)
2
Each CAT24AA16 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
CC
mode after V exceeds the POR trigger level and will
CC
power down into Reset mode when V drops below the
POR trigger level.
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
CC
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). A START is generated by a
HIGH to LOW transition, while a STOP is generated by a
LOW to HIGH transition. The START acts like a wake−up
call. Absent a START, no Slave will respond to the Master.
The STOP completes all commands.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and delivered on the negative
edge of SCL.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address
(Figure 3). The four most significant bits of the Slave
address are 1010 (Ah). The next three bits are internal
WP: When the Write Protect input pin is forced HIGH by an
external source, all write operations are inhibited. When the
pin is not driven by an external source, it is pulled LOW
internally.
address bits, a , a , a . The last bit, R/W, instructs the Slave
10
9
8
Functional Description
to either provide (1) or accept (0) data, i.e. it specifies a Read
(1) or a Write (0) operation.
The CAT24AA16 supports the Inter−Integrated Circuit
2
(I C) Bus protocol. The protocol relies on the use of a Master
Acknowledge
During the 9 clock cycle following every byte sent onto
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24AA16
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
th
the bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
a
10
a
9
a
8
R/W
Figure 3. Slave Address Bits
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4
CAT24AA16
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY
(RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (w t
)
SU:DAT
START
ACK DELAY (v t
)
AA
Figure 4. Acknowledge Timing
t
F
t
t
R
HIGH
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
HD:STA
t
SU:DAT
SU:STO
SDA IN
t
BUF
t
AA
t
DH
SDA OUT
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
Acknowledge Polling
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends an address
byte and a data byte and concludes the session by creating
a STOP condition on the bus. The Slave responds with ACK
after every byte sent by the Master (Figure 6). The STOP
starts the internal Write cycle, and while this operation is in
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24AA16 initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24AA16 is still busy
with the write operation, NoACK will be returned. If the
CAT24AA16 device has completed the internal write
operation, an ACK will be returned and the host can then
proceed with the next read or write operation.
progress (t ), the SDA output is tri−stated and the Slave
WR
does not acknowledge the Master (Figure 7).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 16 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
st
falling edge of SCL immediately preceding the 1 data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
written to memory in a single internal Write cycle (t ).
WR
Delivery State
The CAT24AA16 is shipped erased, i.e., all bytes are FFh.
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5
CAT24AA16
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
T
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
O
P
a
7
B a
d
7
B d
0
0
S
P
A
C
K
A
C
K
A
C
K
SLAVE
Figure 6. Byte Write Sequence
SCL
SDA
th
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+x
T
O
P
ADDRESS
BYTE
SLAVE
ADDRESS
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
n = 1
x v 15
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
8
a
9
1
8
d
SCL
SDA
a
7
d
7
0
0
t
SU:WP
WP
t
HD:WP
Figure 9. WP Timing
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6
CAT24AA16
READ OPERATIONS
Immediate Read
sequence by sending data, the Master then creates a START
condition and broadcasts a Slave address with the R/W bit
set to ‘1’. The Slave responds with ACK after every byte sent
by the Master and then sends out data residing at the selected
address. After receiving the data, the Master responds with
NoACK and then terminates the session by creating a STOP
condition on the bus (Figure 11).
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Sequential Read
Selective Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends an address
byte to the Slave. Rather than completing the Byte Write
N
S
O
BUS ACTIVITY:
MASTER
T
A
R
T
S
T
O
P
A
C
K
SLAVE
ADDRESS
S
P
A
C
K
DATA
BYTE
SLAVE
8
SCL
SDA
9
th
8
Bit
NO ACK
DATA OUT
STOP
Figure 10. Immediate Read Sequence and Timing
N
O
S
T
A
R
T
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
Figure 11. Selective Read Sequence
N
O
BUS ACTIVITY:
MASTER
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
ADDRESS
P
A
C
K
SLAVE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
Figure 12. Sequential Read Sequence
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7
CAT24AA16
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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8
CAT24AA16
PACKAGE DIMENSIONS
TSOT−23, 5 LEAD
CASE 419AE−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.00
0.10
0.90
0.45
0.20
D
A
A1
A2
b
e
0.01
0.80
0.30
0.12
0.05
0.87
c
0.15
D
2.90 BSC
2.80 BSC
1.60 BSC
0.95 TYP
0.40
E1
E
E
E1
e
L
0.30
0.50
L1
L2
θ
0.60 REF
0.25 BSC
0º
8º
TOP VIEW
A2 A
q
L
b
c
A1
L2
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-193.
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9
CAT24AA16
Example of Ordering Information
Prefix
Device #
Suffix
CAT
24AA16
TD
I
− G
T3
Temperature Range
Lead Finish
Tape & Reel
Company ID
G: NiPdAu
Blank: Matte−Tin
T: Tape & Reel
I = Industrial (−40°C to +85°C)
3: 3,000 Units / Reel
10: 10,000 Units / Reel
(Note 12)
Product Number
24AA16
Package
TD: TSOT−23 5−Lead
W: SOIC 8−Lead
9. All packages are RoHS−compliant (Lead−free, Halogen−free).
10.The standard lead finish is NiPdAu.
11. The device used in the above example is a CAT24AA16TDI−GT3 (TSOT−23 5−Lead, Industrial Temperature, NiPdAu, Tape & Reel,
3,000/Reel).
12.The 10,000/Reel option is only available for the TSOT−23 5−Lead package.
13.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
14.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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Order Literature: http://www.onsemi.com/orderlit
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Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
CAT24AA16/D
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