CAT1161LI45 [ONSEMI]
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CAT1161, CAT1162
Supervisory Circuits with
I2C Serial CMOS EEPROM,
Precision Reset Controller
and Watchdog Timer (16K)
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Description
The CAT1161/2 is a complete memory and supervisory solution for
microcontroller−based systems. A serial EEPROM memory (16K)
with hardware memory write protection, a system power supervisor
with brown out protection and a watchdog timer are integrated
together in low power CMOS technology. Memory interface is via an
PDIP−8
CASE 646AA
SOIC−8
CASE 751BD
2
I C bus.
The 1.6−second watchdog circuit returns a system to a known good
state if a software or hardware glitch halts or “hangs” the system. The
CAT1161 watchdog monitors the SDA line, making an additional PC
board trace unnecessary. The lower cost CAT1162 does not have a
watchdog timer.
The power supply monitor and reset circuit protects memory and
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
200 ms after the supply voltage exceeds the reset threshold level. With
both active high and low reset signals, interface to microcontrollers
and other ICs is simple. In addition, a reset pin can be used as a
debounced input for pushbutton manual reset capability.
PIN CONFIGURATION
DC
1
8
V
CC
RESET
2
7
RESET
CAT1161
CAT1162
3
4
6
5
WP
SCL
SDA
GND
PIN FUNCTIONS
Pin Name
Function
DC
RESET
WP
Do Not Connect
Active Low Reset I/O
Write Protect
The CAT1161/2 memory features a 16−byte page. In addition,
hardware data protection is provided by a write protect pin WP and by
GND
SDA
Ground
a V sense circuit that prevents writes to memory whenever V falls
CC
CC
Serial Data/Address
Clock Input
below the reset threshold or until V reaches the reset threshold
CC
SCL
during power up.
Available packages include an 8−pin DIP and a surface mount,
8−pin SO package.
RESET
Active High Reset I/O
Power Supply
V
CC
Features
• Watchdog Monitors SDA Signal (CAT1161)
ORDERING INFORMATION
2
• 400 kHz I C Bus Compatible
For Ordering Information details, see page 11.
• 2.7 V to 6 V Operation
• Low Power CMOS Technology
• 16−Byte Page Write Buffer
• 1,000,000 Program/Erase Cycles
• Built−in Inadvertent Write Protection
• Manual Reset
♦ V Lock Out
CC
♦ Write Protection Pin, WP
• 100 Year Data Retention
• Active High or Low Reset
• 8−Pin DIP or 8−Pin SOIC
♦ Precision Power Supply Voltage Monitor
♦ 5 V, 3.3 V and 3 V Systems
• Commercial and Industrial Temperature Ranges
• These Devices are Pb−Free, Halogen Free/BFR Free
♦ Five Threshold Voltage Options
and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
July, 2012 − Rev. 12
CAT1161/D
CAT1161, CAT1162
Table 1. RESET THRESHOLD OPTION
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
−45
−42
−30
−28
−25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
BLOCK DIAGRAM
EXTERNAL LOAD
SENSEAMPS
D
OUT
SHIFT REGISTERS
ACK
V
CC
WORDꢀADDRESS
BUFFERS
COLUMN
GND
DECODERS
STAꢀRT/ꢀSTOP
SDA
LOGIC
16K
EEPROM
XDEC
CONTROL
LOGIC
WP
DATA IN STORAGE
HIGHꢀVOLTAGE/
TIMING CONTROL
RESET Controller
Precision
STATE COUNTERS
SCL
SLAVE
ADDRESS
WATꢀCHꢀDOꢀG
Only for
CAT1161
Vcc Monitor
COMPARATORS
RESETꢁRESET
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2
CAT1161, CAT1162
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
°C
V
Temperature Under Bias
–55 to +125
–65 to +150
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
−2.0 to V + 2.0
CC
V
with Respect to Ground
−2.0 to 7.0
1.0
V
CC
Package Power Dissipation Capability (T = 25°C)
W
A
Lead Soldering Temperature (10 sec)
Output Short Circuit Current (Note 2)
300
°C
mA
100
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V +0.5 V, which may overshoot to V +2.0 V for periods of less than 20 ns.
CC
CC
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
(Note 3)
Parameter
Endurance
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Max
Units
Cycles/Byte
Years
N
END
T
(Note 3)
(Note 3)
Data Retention
DR
V
ESD Susceptibility
2000
Volts
ZAP
I
(Notes 3 & 4) Latch−Up
100
mA
LTH
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V +1 V.
CC
Table 4. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 6 V, unless otherwise specified.
Symbol
Parameter
Power Supply Current
Standby Current
Test Conditions
= 100 kHz
Min
Typ
Max
3
Units
mA
mA
I
f
SCL
CC
I
SB
V
V
V
V
= 3.3 V
= 5 V
40
50
2
CC
CC
mA
I
LI
Input Leakage Current
Output Leakage Current
Input Low Voltage
= GND or V
= GND or V
mA
IN
IN
CC
I
LO
10
mA
CC
V
IL
−1
V
x 0.3
V
V
V
CC
V
IH
Input High Voltage
V
x 0.7
V
+ 0.5
CC
CC
V
OL1
Output Low Voltage (SDA)
I
OL
= 3 mA, V = 3.0 V
0.4
CC
Table 5. CAPACITANCE
T = 25°C, f = 1.0 MHz, V = 5 V
A
CC
Symbol
(Note 3)
Test
Test Conditions
= 0 V
Max
8
Units
pF
C
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
V
V
I/O
I/O
C
(Note 3)
= 0 V
6
pF
IN
IN
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CAT1161, CAT1162
Table 6. AC CHARACTERISTICS
V
CC
= 2.7 V to 6.0 V unless otherwise specified. Output Load is TTL Gate and 100 pF.
Symbol
Parameter
Min
Max
100
200
3.5
Min
Max
400
200
1
Units
kHz
ns
F
SCL
Clock Frequency
T (Note 1)
1
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
t
AA
ms
t
(Note 1)
Time the Bus must be Free Before a New Transmission Can
Start
4.7
1.2
ms
BUF
t
Start Condition Hold Time
Clock Low Period
4
4.7
4
0.6
1.2
0.6
0.6
0
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
HD; STA
t
LOW
t
Clock High Period
HIGH
t
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
4.7
0
SU; STA
HD; DAT
t
t
Data in Setup Time
50
50
SU; DAT
t
(Note 1)
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
R
t (Note 1)
F
300
300
t
4
0.6
SU; STO
t
100
100
DH
1. This parameter is tested initially and after a design or process change that affects the parameter.
Table 7. WRITE CYCLE LIMITS
Symbol
Parameter
Min
Typ
Max
Units
t
Write Cycle Time
10
ms
WR
* The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Table 8. RESET CIRCUIT CHARACTERISTICS
Symbol
Parameter
Glitch Reject Pulse Width
CC
Min
Typ
Max
Units
ns
t
V
100
GLITCH
V
Reset Threshold Hysteresis
Reset Output Low Voltage (I
Reset Output High Voltage
15
mV
V
RT
V
OLRS
OHRS
= 1 mA)
OLRS
0.4
V
V
CC
− 0.75
V
V
Reset Threshold (V = 5 V), (CAT1161/2−45)
4.50
4.25
3.00
2.85
2.55
130
4.75
4.50
3.15
3.00
2.70
270
V
TH
CC
Reset Threshold (V = 5 V), (CAT1161/2−42)
CC
Reset Threshold (V = 3.3 V), (CAT1161/2−30)
CC
Reset Threshold (V = 3.3 V), (CAT1161/2−28)
CC
Reset Threshold (V = 3 V), (CAT1161/2−25)
CC
t
Power−Up Reset Timeout
ms
s
PURST
t
Watchdog Period
1.6
WP
t
V
to RESET Output Delay
5
ms
V
RPD
TH
V
RESET Output Valid
1
RVALID
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CAT1161, CAT1162
PIN DESCRIPTION
WP: WRITE PROTECT
SDA: SERIAL DATA ADDRESS
If the pin is tied to VCC the entire memory array becomes
Write Protected (READ only). When the pin is tied to GND
or left floating normal read/write operations are allowed to
the device.
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
If there is no transition on the SDA for more than
1.6 seconds, the watchdog timer times out.
RESET/RESET: RESET I/O
These are open drain pins and can be used as reset trigger
inputs. By forcing a reset condition on the pins the device
will initiate and maintain a reset condition. The RESET pin
must be connected through a pulldown resistor, and the
RESET pin must be connected through a pull−up resistor.
SCL: Serial Clock
Serial clock input.
DEVICE OPERATION
Reset Controller Description
after detecting a low to high transition and the RESET input
will initiate a reset timeout after detecting a high to low
transition.
The CAT1161/2 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain
RESET outputs. During power−up, the RESET outputs
Watchdog Timer
The Watchdog Timer provides an independent protection
for microcontrollers. During a system failure, the CAT1161
will respond with a reset signal after a time−out interval of
1.6 seconds for a lack of activity. The CAT1161 is designed
with the Watchdog Timer feature on the SDA input. If the
microcontroller does not toggle the SDA input pin within 1.6
seconds, the Watchdog Timer times out. This will generate
a reset condition on reset outputs. The Watchdog Timer is
cleared by any transition on SDA.
remain active until V reaches the V threshold and will
CC
TH
continue driving the outputs for approximately 200 ms
(t ) after reaching V . After the t timeout
PURST
TH
PURST
interval, the device will cease to drive the reset outputs. At
this point the reset outputs will be pulled up or down by their
respective pull up/down resistors. During power−down, the
RESET outputs will be active when V falls below V
.
CC
TH
The RESET outputs will be valid so long as V is > 1.0 V
CC
(V
).
RVALID
As long as reset signal is asserted, the Watchdog Timer
will not count and will stay cleared.
The CAT1162 does not have a Watchdog.
The RESET pins are I/Os; therefore, the CAT1161/2 can
act as a signal conditioning circuit for an externally applied
manual reset. The inputs are edge triggered; that is, the
RESET input in the CAT1161/2 will initiate a reset timeout
tGLITCH
VTH
V
RVAꢀLIꢀD
VCC
tRPD
tPURSꢀT
tPURSꢀT
RESET
tRPD
RESET
Figure 1. RESET Output Timing
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CAT1161, CAT1162
Hardware Data Protection
down) V or until V reaches the reset threshold
TH
CC
The CAT1161/2 is designed with the following hardware
data protection features to provide a high degree of data
integrity.
(power up) V . Any attempt to access the
TH
internal EEPROM is not recognized and an ACK
will not be sent on the SDA line when RESET or
RESET is active.
1. The CAT1161/2 features a WP pin. When the WP
pin is tied high the entire memory array becomes
write protected (read only).
Reset Threshold Voltage
The CAT1161/2 is offered with five reset threshold
voltage ranges. They are 4.50 ÷ 4.75 V, 4.25 ÷ 4.50 V,
3.00 ÷ 3.15 V, 2.85 ÷ 3.00 V and 2.55 ÷ 2.70 V.
2. The V sense provides write protection when
CC
V
CC
falls below the reset threshold value (V ).
TH
The V lock out inhibits writes to the serial
CC
EEPROM whenever V falls below (power
CC
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
AA
t
DH
SDA OUT
Figure 2. Bus Timing
SCL
SDA
8TH BIꢀT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Write Cycle Timing
SDA
SCL
START BIT
STOP BIT
Figure 4. Start/Stop Timing
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CAT1161, CAT1162
FUCTIONAL DESCRIPTION
2
STOP Condition
The CAT1161/2 supports the I C Bus data transmission
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
Device Addressing
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8−bit slave address are fixed as 1010.
The next three bits (Figure 6) define memory addressing.
For the CAT1161/2 the three bits define higher order bits.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1161/2 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The CAT1161/2 then
performs a Read or Write operation depending on the
R/W bit.
I2C Bus Protocol
The features of the I C bus protocol are defined as
2
follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1161/2 monitors the SDA and
SCL lines and will not respond until this condition is met.
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Acknowledge Timing
1
0
1
0
a10
a9
a8
R/W
CAT1161/2
Note: a8, a9 and a10 correspond to the address of the memory array address word.
Figure 6. Slave Address Bits
Acknowledge
responds with an acknowledge after receiving each 8−bit
byte.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT1161/2 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
When the CAT1161/2 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT1161/2 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
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CAT1161, CAT1162
WRITE OPERATIONS
Page Write
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends a 8−bit address
that is to be written into the address pointers of the
CAT1161/2. After receiving another acknowledge from the
Slave, the Master device transmits the data to be written into
the addressed memory location. The CAT1161/2
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an internal
programming cycle to non−volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
The CAT1161/2 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to 15
additional bytes. After each byte has been transmitted, the
CAT1161/2 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 16 bytes before sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1161/2 in a single write cycle.
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Byte Write Timing
S
T
A
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
R
DATAꢁn
DATA nꢀ+ꢀ1
DATA n+15
T
S
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Timing
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation, the
CAT1161/2 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the CAT1161/2 is still busy with the write
operation, no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can then
proceed with the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent memory array programming. If the WP
pin is tied to VCC, the entire memory array is protected and
becomes read only. The CAT1161/2 will accept both slave
and byte addresses, but the memory location accessed is
protected from programming by the device’s failure to send
an acknowledge after the first byte of data is received.
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CAT1161, CAT1162
READ OPERATIONS
The READ operation for the CAT1161/2 is initiated in the
same manner as the write operation with one exception, that
R/W bit is set to one. Three different READ operations are
if the last READ or WRITE access was to address N, the
READ immediately following would access data from
address N+1. For all devices, N=E=2047. The counter will
wrap around to Zero and continue to clock out valid data for
the 16K devices. After the CAT1161/2 receives its slave
address information (with the R/W bit set to one), it issues
an acknowledge, then transmits the 8−bit byte requested.
The master device does not send an acknowledge, but will
generate a STOP condition.
possible:
Immediate/Current
Address
READ,
Selective/Random READ and Sequential READ.
Immediate/Current Address Read
The CAT1161/2 address counter contains the address of
the last byte accessed, incremented by one. In other words,
S
T
A
R
T
S
T
O
P
BUS ꢀACTIVITꢀY:
MASTER
SLꢀAVE
ADDRESS
SDꢀA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCꢀL
8
9
SDꢀAꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂ8TH BIꢀT
DATA OUꢀT
NO ACK
STOP
Figure 9. Immediate Address Read Timing
Selective/Random Read
the entire memory array can be read during one operation.
If more than E (where E=2047 for the CAT1161/2) bytes are
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1161/2 acknowledges, the Master device
sends the START condition and the slave address again, this
time with the R/W bit set to one. The CAT1161/2 then
responds with its acknowledge and sends the 8−bit byte
requested. The master device does not send an acknowledge
but will generate a STOP condition.
Manual Reset Operation
The CAT116x RESET or RESET pin can also be used as
a manual reset input.
Only the “active” edge of the manual reset input is
internally sensed. The positive edge is sensed if RESET is
used as a manual reset input and the negative edge is sensed
if RESET is used as a manual reset input.
An internal counter starts a 200 ms count. During this
time, the complementary reset output will be kept in the
active state. If the manual reset input is forced active for
more than 200 ms, the complementary reset output will
switch back to the non active state after the 200 ms expired,
regardless for how long the manual reset input is forced
active.
The embedded EEPROM is disabled as long as a reset
condition is maintained on any RESET pin. If the external
forced RESET/RESET is longer than internal controlled
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1161/2 sends the inital 8−bit byte
requested, the Master will responds with an acknowledge
which tells the device it requires more data. The CAT1161/2
will continue to output an 8−bit byte for each acknowledge,
thus sending the STOP condition.
The data being transmitted from the CAT1161/2 is
outputted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT1161/2 address bits so that
time−out period, t , the memory will not respond with
PURST
an acknowledge for any access as long as the manual reset
input is active.
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CAT1161, CAT1162
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 10. Selective Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 11. Sequential Read Timing
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CAT1161, CAT1162
ORDERING INFORMATION
Orderable Part Numbers − CAT1161/2 Series
(See Notes 1 − 4)
Device
Reset Threshold
Voltage
Package−Pins
Shipping
CAT1161LI−45−G
CAT1161LI−42−G
CAT1161LI−30−G
CAT1161LI−28−G
CAT1161LI−25−G
CAT1161WI−45−GT3
CAT1161WI−42−GT3
CAT1161WI−30−GT3
CAT1161WI−28−GT3
CAT1161WI−25−GT3
CAT1162LI−45−G
CAT1162LI−42−G
CAT1162LI−30−G
CAT1162LI−28−G
CAT1162LI−25−G
CAT1162WI−45−GT3
CAT1162WI−42−GT3
CAT1162WI−30−GT3
CAT1162WI−28−GT3
CAT1162WI−25−GT3
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
4.50 V − 4.75 V
4.25 V − 4.50 V
3.00 V − 3.15 V
2.85 V − 3.00 V
2.55 V − 2.70 V
PDIP−8
SOIC−8
PDIP−8
SOIC−8
3000 Tape & Reel
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
http://onsemi.com
11
CAT1161, CAT1162
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
MAX
A
5.33
A1
A2
b
0.38
2.92
0.36
3.30
0.46
1.52
0.25
9.27
4.95
0.56
1.78
0.36
10.16
b2
c
1.14
0.20
9.02
E1
D
E
E1
e
7.62
6.10
7.87
6.35
8.25
7.11
2.54 BSC
7.87
2.92
10.92
3.80
eB
L
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
http://onsemi.com
12
CAT1161, CAT1162
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
0.25
0.51
0.25
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT1161/D
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