CAT1161LI-45-G [ONSEMI]
Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K); 监控电路，带有I2C串行EEPROM CMOS ，精密复位控制器和看门狗定时器（ 16K ）
| 型号： | CAT1161LI-45-G |
| 厂家： | 
ONSEMI |
| 描述： | Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K) |
| 文件： | 总14页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT1161, CAT1162
Supervisory Circuits with I2C Serial CMOS EEPROM,
Precision Reset Controller and Watchdog Timer (16K)
brown out protection and a watchdog timer are
integrated together in low power CMOS technology.
FEATURES
Memory interface is via an I2C bus.
Watchdog monitors SDA signal (CAT1161)
400kHz I2C bus compatible
The 1.6-second watchdog circuit returns a system to a
known good state if a software or hardware glitch
halts or “hangs” the system. The CAT1161 watchdog
monitors the SDA line, making an additional PC board
trace unnecessary. The lower cost CAT1162 does not
have a watchdog timer.
2.7V to 6.0V operation
Low power CMOS technology
16-Byte page write buffer
Built-in inadvertent write protection
The power supply monitor and reset circuit protects
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200ms after the supply
voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to
microcontrollers and other ICs is simple. In addition, a
reset pin can be used as a debounced input for push-
button manual reset capability.
—
—
VCC lock out
Write protect pin, WP
Active high or low reset
—
—
—
Precision power supply voltage monitor
5V, 3.3V and 3V systems
Five threshold voltage options
1,000,000 Program/Erase cycles
Manual Reset
100 Year data retention
8-pin DIP or 8-pin SOIC
The CAT1161/2 memory features a 16-byte page. In
addition, hardware data protection is provided by a
write protect pin WP and by a VCC sense circuit that
prevents writes to memory whenever VCC falls below
the reset threshold or until VCC reaches the reset
threshold during power up.
Commercial and industrial temperature ranges
For Ordering Information details, see page 13.
DESCRIPTION
Available packages include an 8-pin DIP and a
surface mount, 8-pin SO package.
The CAT1161/2 is a complete memory and supervi-
sory solution for microcontroller-based systems. A se-
rial EEPROM memory (16K) with hardware memory
write protection, a system power supervisor with
PIN FUNCTIONS
PIN CONFIGURATION
Pin Name Function
PDIP 8 Lead
SOIC 8 Lead
DC
¯¯¯¯¯¯
RESET
Do not Connect
Active Low Reset I/O
Write Protect
DC
1
2
3
4
8
7
6
5
VCC
WP
GND
SDA
¯¯¯¯¯¯
RESET
RESET
SCL
CAT1161
CAT1162
Ground
WP
Serial Data/Address
Clock Input
GND
SDA
SCL
RESET
VCC
Active High Reset I/O
Power Supply
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-3002 Rev. I
CAT1161, CAT1162
BLOCK DIAGRAM
RESET THRESHOLD OPTION
EXTERNAL LOAD
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
SENSEAMPS
SHIFT REGISTERS
D
OUT
ACK
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
V
CC
WORDADDRESS
BUFFERS
COLUMN
DECODERS
GND
START/STOP
LOGIC
SDA
16K
EEPROM
XDEC
CONTROL
LOGIC
WP
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
Precision
SLAVE
ADDRESS
COMPARATORS
WATCHDOG
Only for
CAT1161
Vcc Monitor
RESET RESET
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
–55 to +125
–65 to +150
–2.0 to VCC + 2.0
–2.0 to 7.0
1.0
Units
ºC
ºC
V
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground(2)
VCC with Respect to Ground
V
Package Power Dissipation Capability (TA = 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current(3)
W
300
ºC
mA
100
REABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
Cycles/Byte
Years
(4)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
(4)
TDR
Data Retention
ESD Susceptibility
Latch-up
(4)
VZAP
2000
Volts
(4)(5)
ILTH
100
mA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Doc. No. MD-3002 Rev. I
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1161, CAT1162
D.C. OPERATING CHARACTERISTICS
VCC = 2.7V to 6V, unless otherwise specified.
Symbol Parameter
Test Conditions
fSCL = 100 KHz
VCC = 3.3V
Min
Typ
Max
Units
mA
µA
µA
µA
µA
V
ICC
Power Supply Current
3
40
50
ISB
Standby Current
VCC = 5
ILI
ILO
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND or VCC
VIN = GND or VCC
2
10
VIL
-1
VCC x 0.3
VCC + 0.5
0.4
VIH
VOL1
Input High Voltage
VCC x 0.7
V
Output Low Voltage (SDA)
IOL = 3 mA, VCC = 3.0V
V
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
Test
Conditions
VI/O = 0V
VIN = 0V
Max
8
Units
pF
(1)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
(1)
CIN
6
pF
A.C. CHARACTERISTICS
CC = 2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF.
V
Symbol Parameter
Min
Max
100
200
3.5
Min
Max
400
200
1
Units
kHz
ns
FSCL
TI(1)
tAA
Clock Frequency
Noise Suppresion Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
µs
Time the Bus Must be Free Before a New Transmission
Can Start
(1)
tBUF
4.7
1.2
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
4.7
4
0.6
1.2
0.6
0.6
0
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
tHIGH
Clock High Period
tSU:STA
tHD:DAT
tSU:DAT
Start Condition Setup Time (for a Repeated Start Condition) 4.7
Data in Hold Time
0
Data in Setup Time
50
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
POWER-UP TIMING (1)(2)
Symbol Parameter
Max
1
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
ms
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specific operation can be initiated.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-3002 Rev. I
CAT1161, CAT1162
WRITE CYCLE LIMITS
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave address.
RESET CIRCUIT CHARACTERISTICS
Symbol Parameter
tGLITCH Glitch Reject Pulse Width
VRT
Min
Typ
Max
Units
ns
100
Reset Threshold Hystersis
15
mV
V
VOLRS
VOHRS
Reset Output Low Voltage (IOLRS=1mA)
Reset Output High Voltage
0.4
VCC - 0.75
4.50
V
Reset Threshold (VCC=5V)
(CAT1161/2-45)
4.75
4.50
3.15
3.00
Reset Threshold (VCC=5V)
(CAT1161/2-42)
4.25
3.00
2.85
Reset Threshold (VCC=3.3V)
(CAT1161/2-30)
VTH
V
Reset Threshold (VCC=3.3V)
(CAT1161/2-28)
Reset Threshold (VCC=3V)
(CAT1161/2-25)
2.55
130
2.70
270
tPURST
tWP
Power-Up Reset Timeout
Watchdog Period
ms
sec
µs
V
1.6
tRPD
VTH to RESET Output Delay
RESET Output Valid
5
VRVALID
1
Doc. No. MD-3002 Rev. I
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1161, CAT1162
RESET outputs. During power-up, the RESET outputs
remain active until VCC reaches the VTH threshold and
will continue driving the outputs for approximately
200ms (tPURST) after reaching VTH. After the tPURST
timeout interval, the device will cease to drive the
reset outputs. At this point the reset outputs will be
pulled up or down by their respective pull up/down
resistors. During power-down, the RESET outputs will
PIN DESCRIPTION
WP: WRITE PROTECT
If the pin is tied to VCC the entire memory array
becomes Write Protected (READ only). When the pin
is tied to GND or left floating normal read/write
operations are allowed to the device.
¯¯¯¯¯¯
be active when VCC falls below VTH. The RESET
¯¯¯¯¯¯
RESET/RESET: RESET I/O
outputs will be valid so long as VCC is >1.0V (VRVALID).
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins
the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-
down resistor, and the RESET pin must be connected
through a pull-up resistor.
The RESET pins are I/Os; therefore, the CAT1161/2
can act as a signal conditioning circuit for an
externally applied manual reset. The inputs are edge
triggered; that is, the RESET input in the CAT1161/2
will initiate a reset timeout after detecting a low to high
¯¯¯¯¯¯
¯¯¯¯¯¯
transition and the RESET input will initiate a reset
SDA: SERIAL DATA ADDRESS
timeout after detecting a high to low transition.
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
Watchdog Timer
The Watchdog Timer provides an independent
protection for microcontrollers. During a system
failure, the CAT1161 will respond with a reset signal
after a time-out interval of 1.6 seconds for a lack of
activity. The CAT1161 is designed with the Watchdog
Timer feature on the SDA input. If the microcontroller
does not toggle the SDA input pin within 1.6 seconds,
the Watchdog Timer times out. This will generate a
reset condition on reset outputs. The Watchdog Timer
is cleared by any transition on SDA.
If there is no transition on the SDA for more than 1.6
seconds, the watchdog timer times out.
SCL: SERIAL CLOCK
Serial clock input.
DEVICE OPERATION
Reset Controller Description
As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared.
The CAT1161/2 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain
The CAT1162 does not have a Watchdog.
Figure 1. RESET Output Timing
tGLITCH
VTH
V
RVALID
VCC
tRPD
tPURST
tPURST
RESET
tRPD
RESE T
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-3002 Rev. I
CAT1161, CAT1162
VCC lock out inhibits writes to the serial EEPROM
whenever VCC falls below (power down) VTH or
until VCC reaches the reset threshold (power up)
VTH. Any attempt to access the internal EEPROM
is not recognized and an ACK will not be sent on
Hardware Data Protection
The CAT1161/2 is designed with the following
hardware data protection features to provide a high
degree of data integrity.
¯¯¯¯¯¯
the SDA line when RESET or RESET is active.
(1) The CAT1161/2 features a WP pin. When the WP
pin is tied high the entire memory array becomes
write protected (read only).
(2) The VCC sense provides write protection when VCC
falls below the reset threshold value (VTH). The
Reset Threshold Voltage
The CAT1161/2 is offered with five reset threshold
voltage ranges. They are 4.50 ÷ 4.75V, 4.25 ÷ 4.50V,
3.00 ÷ 3.15V, 2.85 ÷ 3.00V and 2.55 ÷ 2.70V.
Figure 2. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 3. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 4. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. MD-3002 Rev. I
6
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1161, CAT1162
the SDA and SCL lines and will not respond until this
condition is met.
FUNCTIONAL DESCRIPTION
The CAT1161/2 supports the I2C Bus data transmis–
sion protocol. This Inter-Integrated Circuit Bus proto–
col defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master
device which generates the serial clock and all
START and STOP conditions for bus access. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls
which mode is activated.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
Device Addressing
The Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 1010.
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
The next three bits (Figure 6) define memory
addressing. For the CAT1161/2 the three bits define
higher order bits.
(1) Data transfer may be initiated only when the bus
is not busy.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
After the Master sends a START condition and the
slave address byte, the CAT1161/2 monitors the bus
and responds with an acknowledge (on the SDA line)
when its address matches the transmitted slave
address. The CAT1161/2 then performs a Read or
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT1161/2 monitors
¯¯
Write operation depending on the R/W bit.
Figure 5. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 6. Slave Address Bits
¯¯
R/W
CAT1161/2
1
0
1
0
a10 a9 a8
**a8, a9 and a10 correspond to the address of the memory array address word.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-3002 Rev. I
CAT1161, CAT1162
Acknowledge
receiving another acknowledge from the Slave, the
Master device transmits the data to be written into the
addressed memory location. The CAT1161/2 acknow–
ledges once more and the Master generates the STOP
condition. At this time, the device begins an internal
programming cycle to non-volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
The CAT1161/2 responds with an acknowledge after
receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
Page Write
The CAT1161/2 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted, the CAT1161/2 will respond with an
acknowledge and internally increment the lower order
address bits by one. The high order bits remain
unchanged.
When the CAT1161/2 begins a READ mode it
transmits 8 bits of data, releases the SDA line and
monitors the line for an acknowledge. Once it
receives this acknowledge, the CAT1161/2 will
continue to transmit data. If no acknowledge is sent
by the Master, the device terminates data
transmission and waits for a STOP condition.
WRITE OPERATIONS
Byte Write
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter
‘wraps around,’ and previously transmitted data will be
overwritten.
In the Byte Write mode, the Master device sends the
START condition and the slave address information
¯¯
(with the R/W bit set to zero) to the Slave device.
When all 16 bytes are received, and the STOP
condition has been sent by the Master, the internal
programming cycle begins. At this point, all received
data is written to the CAT1161/2 in a single write cycle.
After the Slave generates an acknowledge, the
Master sends a 8-bit address that is to be written
into the address pointers of the CAT1161/2. After
Figure 7. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc. No. MD-3002 Rev. I
8
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1161, CAT1162
Acknowledge Polling
READ OPERATIONS
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1161/2 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the CAT1161/2 is still busy with the write operation,
no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
The READ operation for the CAT1161/2 is initiated in the
same manner as the write operation with one exception,
¯¯
that R/W bit is set to one. Three different READ ope–
rations are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
Immediate/Current Address Read
The CAT1161/2 address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to
address N, the READ immediately following would
access data from address N+1. For all devices,
N=E=2047. The counter will wrap around to Zero and
continue to clock out valid data for the 16K devices.
After the CAT1161/2 receives its slave address
WRITE PROTECTION
The Write Protection feature allows the user to
protect against inadvertent memory array program-
ming. If the WP pin is tied to VCC, the entire memory
array is protected and becomes read only. The
CAT1161/2 will accept both slave and byte
addresses, but the memory location accessed is
protected from programming by the device’s failure
to send an acknowledge after the first byte of data is
received.
¯¯
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8-bit byte requested.
The master device does not send an acknowledge, but
will generate a STOP condition.
Figure 9. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVIT Y:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
Doc. No. MD-3002 Rev. I
CAT1161, CAT1162
Selective/Random Read
array can be read during one operation. If more than E
(where E=2047 for the CAT1161/2) bytes are read out,
the counter will ‘wrap around’ and continue to clock out
data bytes.
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1161/2 acknowledges, the Master device sends
the START condition and the slave address again,
this time with the R/W bit set to one. The CAT1161/2
then responds with its acknowledge and sends the
8-bit byte requested. The master device does not
send an acknowledge but will generate a STOP
condition.
Manual Reset Operation
¯¯¯¯¯¯
The CAT116x RESET or RESET pin can also be used
as a manual reset input.
Only the “active” edge of the manual reset input is
internally sensed. The positive edge is sensed if
RESET is used as a manual reset input and the
¯¯¯¯¯¯
negative edge is sensed if RESET is used as a manual
reset input.
An internal counter starts a 200ms count. During this
time, the complementary reset output will be kept in the
active state. If the manual reset input is forced active for
more than 200ms, the complementary reset output will
switch back to the non active state after the 200ms
expired, regardless for how long the manual reset input
is forced active.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective
READ operations. After the CAT1161/2 sends the
inital 8-bit byte requested, the Master will responds
with an acknowledge which tells the device it
requires more data. The CAT1161/2 will continue to
output an 8-bit byte for each acknowledge, thus
sending the STOP condition.
The embedded EEPROM is disabled as long as a reset
condition is maintained on any RESET pin. If the
¯¯¯¯¯¯
external forced RESET/RESET is longer than internal
The data being transmitted from the CAT1161/2 is
outputted sequentially with data from address N
followed by data from address N+1. The READ
operation address counter increments all of the
CAT1161/2 address bits so that the entire memory
, the memory will not
controlled time-out period, tPURST
respond with an acknowledge for any access as long as
the manual reset input is active.
Figure 10. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 11. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. MD-3002 Rev. I
10
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1161, CAT1162
PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300mils (L)(1)(2)
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
5.33
0.38
2.92
0.36
1.14
0.20
9.02
7.62
3.30
0.46
4.95
0.56
1.78
0.36
10.16
8.25
b2
c
1.52
E1
0.25
D
9.27
E
7.87
e
2.54 BSC
6.35
E1
eB
L
6.10
7.87
2.92
7.11
10.92
3.80
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
c
b2
L
eB
e
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-3002 Rev. I
CAT1161, CAT1162
(1)(2)
SOIC 8-Lead 150mils (W)
SYMBOL
MIN
NOM
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
A1
b
1.35
0.10
0.33
0.19
4.80
5.80
3.80
c
E1
E
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
Doc. No. MD-3002 Rev. I
12
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1161, CAT1162
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
Device # Suffix
CAT
1162
W
I
-30
– G
T3
Optional
Company ID
Temperature Range
I = Industrial (-40ºC to 85ºC)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Product
Number
1161: 16K
1162: 16K
Package
L: PDIP
W: SOIC
Reset Threshold Voltage
-45: 4.50V to 4.75V
-42: 4.25V to 4.50V
-30: 3.00V to 3.15V
-28: 2.85V to 3.00V
-25: 2.55V to 2.70V
Tape & Reel
T: Tape & Reel
3: 3,000/Reel
ORDERING INFORMATION
Orderable Part Number
CAT1161LI-25-G
Reset Threshold Voltage Package-Pins Lead Finish
25
28
CAT1161LI-28-G
PDIP-8
SOIC-8
PDIP-8
SOIC-8
CAT1161LI-30-G
30
42
45
25
28
30
42
45
25
28
30
42
45
25
28
30
42
45
CAT1161LI-42-G
CAT1161LI-45-G
CAT1161WI-25-GT3
CAT1161WI-28-GT3
CAT1161WI-30-GT3
CAT1161WI-42-GT3
CAT1161WI-45-GT3
CAT1162LI-25-G
NiPdAu
CAT1162LI-28-G
CAT1162LI-30-G
CAT1162LI-42-G
CAT1162LI-45-G
CAT1162WI-25-GT3
CAT1162WI-28-GT3
CAT1162WI-30-GT3
CAT1162WI-42-GT3
CAT1162WI-45-GT3
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT1162WI-30-GT3 (SOIC, Industrial Temperature, 3V to 3.15V, NiPdAu, Tape & Reel,
3,000/Reel).
(4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
13
Doc. No. MD-3002 Rev. I
CAT1161, CAT1162
REVISION HISTORY
Date
Rev. Description
Add Green Logo
Add Package Outline
Update Ordering Information
17-Feb-05
E
F
Update Package Outline
Update Example of Ordering Information
2-Feb-07
28-Nov07
Update Package Outline Drawings
Update Example of Ordering Information
Add “MD-“ to document number
G
10-Nov-08
05-Aug-09
H
I
Change logo and fine print to ON Semiconductor
Update Orderable Part Number table.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center:
Phone: 81-3-5773-3850
ON Semiconductor Website: www.onsemi.com
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
Doc. No. MD-3002 Rev. I
14
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
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